Add correct NEON encodings for the "multiple single elements" form of vld.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117984 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index 5757046..b276301 100644
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -99,7 +99,7 @@
unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op) const;
unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op) const;
-
+ unsigned getAddrMode6RegisterOperand(const MCInst &MI, unsigned Op) const;
unsigned getNumFixupKinds() const {
assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented.");
@@ -296,6 +296,22 @@
return Binary;
}
+unsigned ARMMCCodeEmitter::getAddrMode6RegisterOperand(const MCInst &MI,
+ unsigned Op) const {
+ const MCOperand &Reg = MI.getOperand(Op);
+ const MCOperand &Imm = MI.getOperand(Op+1);
+
+ unsigned RegNo = getARMRegisterNumbering(Reg.getReg());
+ unsigned Align = Imm.getImm();
+ switch(Align) {
+ case 8: Align = 0x01; break;
+ case 16: Align = 0x02; break;
+ case 32: Align = 0x03; break;
+ default: Align = 0x00;
+ }
+ return RegNo | (Align << 4);
+}
+
void ARMMCCodeEmitter::
EncodeInstruction(const MCInst &MI, raw_ostream &OS,
SmallVectorImpl<MCFixup> &Fixups) const {