commit da47e6e0d003c873da960361549e57ee4617c301
author Evan Cheng <evan.cheng@apple.com> Sat Mar 15 00:03:38 2008 +0000
committer Evan Cheng <evan.cheng@apple.com> Sat Mar 15 00:03:38 2008 +0000
tree 7aeba4e0c14a734364886783388f965e5854d4d9
parent af59b105bb3f9a31f1812e470eb9db28a8a1b491

Replace all target specific implicit def instructions with a target independent one: TargetInstrInfo::IMPLICIT_DEF.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48380 91177308-0d34-0410-b5e6-96231b3b80d8

utils/TableGen/CodeEmitterGen.cpp

diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp
index 60d196c..bebf1fd 100644
--- a/utils/TableGen/CodeEmitterGen.cpp
+++ b/utils/TableGen/CodeEmitterGen.cpp
@@ -29,7 +29,8 @@
         R->getName() == "LABEL" ||
         R->getName() == "DECLARE" ||
         R->getName() == "EXTRACT_SUBREG" ||
-        R->getName() == "INSERT_SUBREG") continue;
+        R->getName() == "INSERT_SUBREG" ||
+        R->getName() == "IMPLICIT_DEF") continue;
     
     BitsInit *BI = R->getValueAsBitsInit("Inst");
 
@@ -103,7 +104,8 @@
         R->getName() == "LABEL" ||
         R->getName() == "DECLARE" ||
         R->getName() == "EXTRACT_SUBREG" ||
-        R->getName() == "INSERT_SUBREG") {
+        R->getName() == "INSERT_SUBREG" ||
+        R->getName() == "IMPLICIT_DEF") {
       o << "    0U";
       continue;
     }
@@ -136,7 +138,8 @@
         InstName == "LABEL"||
         InstName == "DECLARE"||
         InstName == "EXTRACT_SUBREG" ||
-        InstName == "INSERT_SUBREG") continue;
+        InstName == "INSERT_SUBREG" ||
+        InstName == "IMPLICIT_DEF") continue;
     
     BitsInit *BI = R->getValueAsBitsInit("Inst");
     const std::vector<RecordVal> &Vals = R->getValues();