commit da9bb3578ed4f57b7e1f5393dfae85ccdf76b4af
author Dale Johannesen <dalej@apple.com> Mon Jan 21 01:00:34 2008 +0000
committer Dale Johannesen <dalej@apple.com> Mon Jan 21 01:00:34 2008 +0000
tree 371f52bf3c139bda1032aafa1e8c6ac13d99cb7f
parent e003813e9613f41ff2c6a10cb1d3ae3a5b8eab1f

Move DAG-changing code out of #ifndef NDEBUG.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@46204 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index be889ea..6b698f4 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1919,7 +1919,6 @@
            MVT::isFloatingPoint(N1.getValueType()) &&
            MVT::getSizeInBits(VT) <= MVT::getSizeInBits(N1.getValueType()) &&
            isa<ConstantSDNode>(N2) && "Invalid FP_ROUND!");
-    if (N1.getValueType() == VT) return N1;  // noop conversion.
     break;
   case ISD::AssertSext:
   case ISD::AssertZext:
@@ -2122,6 +2121,9 @@
     if (N2C && N2C->getValue() == 0)
       return N1;
     break;
+  case ISD::FP_ROUND:
+    if (N1.getValueType() == VT) return N1;  // noop conversion.
+    break;
   case ISD::FP_ROUND_INREG:
     if (cast<VTSDNode>(N2)->getVT() == VT) return N1;  // Not actually rounding.
     break;