commit dac237e18209b697a8ba122d0ddd9cad4dfba1f8
author Torok Edwin <edwintorok@gmail.com> Wed Jul 08 20:53:28 2009 +0000
committer Torok Edwin <edwintorok@gmail.com> Wed Jul 08 20:53:28 2009 +0000
tree 84addd27fd1610e6e8b5a9a82162914726abab4c
parent d1fbd142945f5ef0c273c3d756431f8cb9d25ded

Implement changes from Chris's feedback.
Finish converting lib/Target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaInstrInfo.cpp

diff --git a/lib/Target/Alpha/AlphaInstrInfo.cpp b/lib/Target/Alpha/AlphaInstrInfo.cpp
index 17a9bc2..62b5d4c 100644
--- a/lib/Target/Alpha/AlphaInstrInfo.cpp
+++ b/lib/Target/Alpha/AlphaInstrInfo.cpp
@@ -201,7 +201,7 @@
       .addReg(SrcReg, getKillRegState(isKill))
       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else
-    llvm_report_error("Unhandled register class");
+    LLVM_UNREACHABLE("Unhandled register class");
 }
 
 void AlphaInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
@@ -217,7 +217,7 @@
   else if (RC == Alpha::GPRCRegisterClass)
     Opc = Alpha::STQ;
   else
-    llvm_report_error("Unhandled register class");
+    LLVM_UNREACHABLE("Unhandled register class");
   DebugLoc DL = DebugLoc::getUnknownLoc();
   MachineInstrBuilder MIB = 
     BuildMI(MF, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill));
@@ -246,7 +246,7 @@
     BuildMI(MBB, MI, DL, get(Alpha::LDQ), DestReg)
       .addFrameIndex(FrameIdx).addReg(Alpha::F31);
   else
-    llvm_report_error("Unhandled register class");
+    LLVM_UNREACHABLE("Unhandled register class");
 }
 
 void AlphaInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
@@ -261,7 +261,7 @@
   else if (RC == Alpha::GPRCRegisterClass)
     Opc = Alpha::LDQ;
   else
-    llvm_report_error("Unhandled register class");
+    LLVM_UNREACHABLE("Unhandled register class");
   DebugLoc DL = DebugLoc::getUnknownLoc();
   MachineInstrBuilder MIB = 
     BuildMI(MF, DL, get(Opc), DestReg);