commit dac237e18209b697a8ba122d0ddd9cad4dfba1f8
author Torok Edwin <edwintorok@gmail.com> Wed Jul 08 20:53:28 2009 +0000
committer Torok Edwin <edwintorok@gmail.com> Wed Jul 08 20:53:28 2009 +0000
tree 84addd27fd1610e6e8b5a9a82162914726abab4c
parent d1fbd142945f5ef0c273c3d756431f8cb9d25ded

Implement changes from Chris's feedback.
Finish converting lib/Target.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@75043 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/CellSPU/SPUInstrInfo.cpp

diff --git a/lib/Target/CellSPU/SPUInstrInfo.cpp b/lib/Target/CellSPU/SPUInstrInfo.cpp
index e629c8d..eba1ca1 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.cpp
+++ b/lib/Target/CellSPU/SPUInstrInfo.cpp
@@ -19,6 +19,7 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/Support/Streams.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/ErrorHandling.h"
 
 using namespace llvm;
 
@@ -313,8 +314,7 @@
   } else if (RC == SPU::VECREGRegisterClass) {
     opc = (isValidFrameIdx) ? SPU::STQDv16i8 : SPU::STQXv16i8;
   } else {
-    assert(0 && "Unknown regclass!");
-    abort();
+    LLVM_UNREACHABLE("Unknown regclass!");
   }
 
   DebugLoc DL = DebugLoc::getUnknownLoc();
@@ -328,8 +328,7 @@
                                   SmallVectorImpl<MachineOperand> &Addr,
                                   const TargetRegisterClass *RC,
                                   SmallVectorImpl<MachineInstr*> &NewMIs) const {
-  cerr << "storeRegToAddr() invoked!\n";
-  abort();
+  llvm_report_error("storeRegToAddr() invoked!");
 
   if (Addr[0].isFI()) {
     /* do what storeRegToStackSlot does here */
@@ -348,8 +347,7 @@
     } else if (RC == SPU::VECREGRegisterClass) {
       /* Opc = PPC::STVX; */
     } else {
-      assert(0 && "Unknown regclass!");
-      abort();
+      LLVM_UNREACHABLE("Unknown regclass!");
     }
     DebugLoc DL = DebugLoc::getUnknownLoc();
     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
@@ -385,8 +383,7 @@
   } else if (RC == SPU::VECREGRegisterClass) {
     opc = (isValidFrameIdx) ? SPU::LQDv16i8 : SPU::LQXv16i8;
   } else {
-    assert(0 && "Unknown regclass in loadRegFromStackSlot!");
-    abort();
+    LLVM_UNREACHABLE("Unknown regclass in loadRegFromStackSlot!");
   }
 
   DebugLoc DL = DebugLoc::getUnknownLoc();
@@ -402,8 +399,7 @@
                                    const TargetRegisterClass *RC,
                                    SmallVectorImpl<MachineInstr*> &NewMIs)
     const {
-  cerr << "loadRegToAddr() invoked!\n";
-  abort();
+  llvm_report_error("loadRegToAddr() invoked!");
 
   if (Addr[0].isFI()) {
     /* do what loadRegFromStackSlot does here... */
@@ -424,8 +420,7 @@
     } else if (RC == SPU::GPRCRegisterClass) {
       /* Opc = something else! */
     } else {
-      assert(0 && "Unknown regclass!");
-      abort();
+      LLVM_UNREACHABLE("Unknown regclass!");
     }
     DebugLoc DL = DebugLoc::getUnknownLoc();
     MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);