commit dbd3c0e06dcd4b94c291388b365a93a3710335af
author Bob Wilson <bob.wilson@apple.com> Wed Aug 12 00:49:01 2009 +0000
committer Bob Wilson <bob.wilson@apple.com> Wed Aug 12 00:49:01 2009 +0000
tree 2a7e96e226a2779e7035614a289c9779a3703a40
parent 23b9b19b1a5a00faa9fce0788155c7dbfd00bfb1

Add missing chain operands for VLD* and VST* instructions.
Set "mayLoad" and "mayStore" on the load/store instructions.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78761 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMISelDAGToDAG.cpp

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index af1e57b..e8c1901 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -1357,8 +1357,9 @@
     case MVT::v2f32:
     case MVT::v2i32: Opc = ARM::VLD2d32; break;
     }
-    const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
-    return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 3);
+    SDValue Chain = N->getOperand(0);
+    const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
+    return CurDAG->getTargetNode(Opc, dl, VT, VT, MVT::Other, Ops, 4);
   }
 
   case ARMISD::VLD3D: {
@@ -1374,8 +1375,9 @@
     case MVT::v2f32:
     case MVT::v2i32: Opc = ARM::VLD3d32; break;
     }
-    const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
-    return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 3);
+    SDValue Chain = N->getOperand(0);
+    const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
+    return CurDAG->getTargetNode(Opc, dl, VT, VT, VT, MVT::Other, Ops, 4);
   }
 
   case ARMISD::VLD4D: {
@@ -1391,10 +1393,11 @@
     case MVT::v2f32:
     case MVT::v2i32: Opc = ARM::VLD4d32; break;
     }
-    const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc };
+    SDValue Chain = N->getOperand(0);
+    const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc, Chain };
     std::vector<EVT> ResTys(4, VT);
     ResTys.push_back(MVT::Other);
-    return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 3);
+    return CurDAG->getTargetNode(Opc, dl, ResTys, Ops, 4);
   }
 
   case ARMISD::VST2D: {
@@ -1409,9 +1412,10 @@
     case MVT::v2f32:
     case MVT::v2i32: Opc = ARM::VST2d32; break;
     }
+    SDValue Chain = N->getOperand(0);
     const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
-                            N->getOperand(2), N->getOperand(3) };
-    return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 5);
+                            N->getOperand(2), N->getOperand(3), Chain };
+    return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6);
   }
 
   case ARMISD::VST3D: {
@@ -1426,10 +1430,11 @@
     case MVT::v2f32:
     case MVT::v2i32: Opc = ARM::VST3d32; break;
     }
+    SDValue Chain = N->getOperand(0);
     const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
                             N->getOperand(2), N->getOperand(3),
-                            N->getOperand(4) };
-    return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 6);
+                            N->getOperand(4), Chain };
+    return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7);
   }
 
   case ARMISD::VST4D: {
@@ -1444,10 +1449,11 @@
     case MVT::v2f32:
     case MVT::v2i32: Opc = ARM::VST4d32; break;
     }
+    SDValue Chain = N->getOperand(0);
     const SDValue Ops[] = { MemAddr, MemUpdate, MemOpc,
                             N->getOperand(2), N->getOperand(3),
-                            N->getOperand(4), N->getOperand(5) };
-    return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 7);
+                            N->getOperand(4), N->getOperand(5), Chain };
+    return CurDAG->getTargetNode(Opc, dl, MVT::Other, Ops, 8);
   }
 
   case ISD::INTRINSIC_WO_CHAIN: {