Add initial support for immediates. This allows us to compile this:
int %rlwnm(int %A, int %B) {
%C = call int asm "rlwnm $0, $1, $2, $3, $4", "=r,r,r,n,n"(int %A, int %B, int 4, int 17)
ret int %C
}
into:
_rlwnm:
or r2, r3, r3
or r3, r4, r4
rlwnm r2, r2, r3, 4, 17 ;; note the immediates :)
or r3, r2, r2
blr
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25955 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index c0fd397..aff5d42 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -300,16 +300,26 @@
// Add all of the operand registers to the instruction.
for (unsigned i = 2; i != NumOps; i += 2) {
- unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
unsigned Flags =cast<ConstantSDNode>(Node->getOperand(i+1))->getValue();
MachineOperand::UseType UseTy;
switch (Flags) {
default: assert(0 && "Bad flags!");
- case 1: UseTy = MachineOperand::Use; break;
- case 2: UseTy = MachineOperand::Def; break;
- case 3: UseTy = MachineOperand::UseAndDef; break;
+ case 1: { // Use of register.
+ unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
+ MI->addMachineRegOperand(Reg, MachineOperand::Use);
+ break;
}
- MI->addMachineRegOperand(Reg, UseTy);
+ case 2: { // Def of register.
+ unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
+ MI->addMachineRegOperand(Reg, MachineOperand::Def);
+ break;
+ }
+ case 3: { // Immediate.
+ uint64_t Val = cast<ConstantSDNode>(Node->getOperand(i))->getValue();
+ MI->addZeroExtImm64Operand(Val);
+ break;
+ }
+ }
}
break;
}