hasFP() is now a virtual method of MRegisterInfo.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@33455 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/include/llvm/Target/MRegisterInfo.h b/include/llvm/Target/MRegisterInfo.h
index ad4d3a8..29fd6b1 100644
--- a/include/llvm/Target/MRegisterInfo.h
+++ b/include/llvm/Target/MRegisterInfo.h
@@ -367,6 +367,11 @@
return 0;
}
+ /// hasFP - Return true if the specified function should have a dedicated frame
+ /// pointer register. For most targets this is true only if the function has
+ /// variable sized allocas or if frame pointer elimination is disabled.
+ virtual bool hasFP(const MachineFunction &MF) const = 0;
+
/// getCallFrameSetup/DestroyOpcode - These methods return the opcode of the
/// frame setup/destroy instructions if they exist (-1 otherwise). Some
/// targets use pseudo instructions in order to abstract away the difference
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 979cb51..2b179cf 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -277,7 +277,7 @@
/// pointer register. This is true if the function has variable sized allocas
/// or if frame pointer elimination is disabled.
///
-static bool hasFP(const MachineFunction &MF) {
+bool ARMRegisterInfo::hasFP(const MachineFunction &MF) const {
return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
}
diff --git a/lib/Target/ARM/ARMRegisterInfo.h b/lib/Target/ARM/ARMRegisterInfo.h
index 6b9ac39..96a9698 100644
--- a/lib/Target/ARM/ARMRegisterInfo.h
+++ b/lib/Target/ARM/ARMRegisterInfo.h
@@ -68,6 +68,8 @@
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
+ bool hasFP(const MachineFunction &MF) const;
+
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;
diff --git a/lib/Target/ARM/ARMRegisterInfo.td b/lib/Target/ARM/ARMRegisterInfo.td
index cf33f8d..0dfd790 100644
--- a/lib/Target/ARM/ARMRegisterInfo.td
+++ b/lib/Target/ARM/ARMRegisterInfo.td
@@ -150,6 +150,7 @@
GPRClass::iterator
GPRClass::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
+ const MRegisterInfo *RI = TM.getRegisterInfo();
const ARMSubtarget &Subtarget = TM.getSubtarget<ARMSubtarget>();
GPRClass::iterator I;
if (Subtarget.isThumb())
@@ -167,7 +168,7 @@
}
// Mac OS X requires FP not to be clobbered for backtracing purpose.
- return (Subtarget.isTargetDarwin() || hasFP(MF)) ? I-1 : I;
+ return (Subtarget.isTargetDarwin() || RI->hasFP(MF)) ? I-1 : I;
}
}];
}
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 5ad7b19..37d4dee 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -186,7 +186,7 @@
// pointer register. This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled.
//
-static bool hasFP(const MachineFunction &MF) {
+bool AlphaRegisterInfo::hasFP(const MachineFunction &MF) const {
MachineFrameInfo *MFI = MF.getFrameInfo();
return MFI->hasVarSizedObjects();
}
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.h b/lib/Target/Alpha/AlphaRegisterInfo.h
index 6e76e4c..5c3f8ec 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.h
+++ b/lib/Target/Alpha/AlphaRegisterInfo.h
@@ -49,6 +49,8 @@
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
+ bool hasFP(const MachineFunction &MF) const;
+
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;
diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp
index 4e6ebd6..bd62852 100644
--- a/lib/Target/IA64/IA64RegisterInfo.cpp
+++ b/lib/Target/IA64/IA64RegisterInfo.cpp
@@ -114,7 +114,7 @@
// pointer register. This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled.
//
-static bool hasFP(const MachineFunction &MF) {
+bool IA64RegisterInfo::hasFP(const MachineFunction &MF) const {
return NoFramePointerElim || MF.getFrameInfo()->hasVarSizedObjects();
}
diff --git a/lib/Target/IA64/IA64RegisterInfo.h b/lib/Target/IA64/IA64RegisterInfo.h
index e107e7d..42a2567 100644
--- a/lib/Target/IA64/IA64RegisterInfo.h
+++ b/lib/Target/IA64/IA64RegisterInfo.h
@@ -48,6 +48,8 @@
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
+ bool hasFP(const MachineFunction &MF) const;
+
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const;
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 371ab7f..e4bea7c 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -410,7 +410,7 @@
// hasFP - Return true if the specified function actually has a dedicated frame
// pointer register. This is true if the function needs a frame pointer and has
// a non-zero stack size.
-static bool hasFP(const MachineFunction &MF) {
+bool PPCRegisterInfo::hasFP(const MachineFunction &MF) const {
const MachineFrameInfo *MFI = MF.getFrameInfo();
return MFI->getStackSize() && needsFP(MF);
}
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h
index 5af6138..5408c9f 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -58,6 +58,8 @@
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
+ bool hasFP(const MachineFunction &MF) const;
+
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index 0c88436..3cb5e50 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -122,6 +122,9 @@
return CalleeSavedRegClasses;
}
+bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
+ return false;
+}
void SparcRegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h
index 263a95f..6f80339 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.h
+++ b/lib/Target/Sparc/SparcRegisterInfo.h
@@ -52,6 +52,8 @@
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
+ bool hasFP(const MachineFunction &MF) const;
+
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 3579b84..1ca0f46 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -891,7 +891,7 @@
// pointer register. This is true if the function has variable sized allocas or
// if frame pointer elimination is disabled.
//
-static bool hasFP(const MachineFunction &MF) {
+bool X86RegisterInfo::hasFP(const MachineFunction &MF) const {
return (NoFramePointerElim ||
MF.getFrameInfo()->hasVarSizedObjects() ||
MF.getInfo<X86FunctionInfo>()->getForceFramePointer());
@@ -998,7 +998,7 @@
// Get the number of bytes to allocate from the FrameInfo
unsigned NumBytes = MFI->getStackSize();
- if (MFI->hasCalls() || MF.getFrameInfo()->hasVarSizedObjects()) {
+ if (MFI->hasCalls() || MFI->hasVarSizedObjects()) {
// When we have no frame pointer, we reserve argument space for call sites
// in the function immediately on entry to the current function. This
// eliminates the need for add/sub ESP brackets around call sites.
diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h
index d8bf486..904c1fb 100644
--- a/lib/Target/X86/X86RegisterInfo.h
+++ b/lib/Target/X86/X86RegisterInfo.h
@@ -78,6 +78,8 @@
/// length of this list match the getCalleeSavedRegs() list.
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
+ bool hasFP(const MachineFunction &MF) const;
+
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI) const;
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index 4728c0c..696068e 100644
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -197,10 +197,11 @@
GR8Class::iterator
GR8Class::allocation_order_begin(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
+ const MRegisterInfo *RI = TM.getRegisterInfo();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
if (!Subtarget.is64Bit())
return X86_GR8_AO_32;
- else if (hasFP(MF))
+ else if (RI->hasFP(MF))
return X86_GR8_AO_64_fp;
else
return X86_GR8_AO_64;
@@ -209,10 +210,11 @@
GR8Class::iterator
GR8Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
+ const MRegisterInfo *RI = TM.getRegisterInfo();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
if (!Subtarget.is64Bit())
return X86_GR8_AO_32 + (sizeof(X86_GR8_AO_32) / sizeof(unsigned));
- else if (hasFP(MF))
+ else if (RI->hasFP(MF))
return X86_GR8_AO_64_fp + (sizeof(X86_GR8_AO_64_fp) / sizeof(unsigned));
else
return X86_GR8_AO_64 + (sizeof(X86_GR8_AO_64) / sizeof(unsigned));
@@ -248,14 +250,15 @@
GR16Class::iterator
GR16Class::allocation_order_begin(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
+ const MRegisterInfo *RI = TM.getRegisterInfo();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
if (Subtarget.is64Bit()) {
- if (hasFP(MF))
+ if (RI->hasFP(MF))
return X86_GR16_AO_64_fp;
else
return X86_GR16_AO_64;
} else {
- if (hasFP(MF))
+ if (RI->hasFP(MF))
return X86_GR16_AO_32_fp;
else
return X86_GR16_AO_32;
@@ -265,14 +268,15 @@
GR16Class::iterator
GR16Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
+ const MRegisterInfo *RI = TM.getRegisterInfo();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
if (Subtarget.is64Bit()) {
- if (hasFP(MF))
+ if (RI->hasFP(MF))
return X86_GR16_AO_64_fp+(sizeof(X86_GR16_AO_64_fp)/sizeof(unsigned));
else
return X86_GR16_AO_64 + (sizeof(X86_GR16_AO_64) / sizeof(unsigned));
} else {
- if (hasFP(MF))
+ if (RI->hasFP(MF))
return X86_GR16_AO_32_fp+(sizeof(X86_GR16_AO_32_fp)/sizeof(unsigned));
else
return X86_GR16_AO_32 + (sizeof(X86_GR16_AO_32) / sizeof(unsigned));
@@ -309,14 +313,15 @@
GR32Class::iterator
GR32Class::allocation_order_begin(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
+ const MRegisterInfo *RI = TM.getRegisterInfo();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
if (Subtarget.is64Bit()) {
- if (hasFP(MF))
+ if (RI->hasFP(MF))
return X86_GR32_AO_64_fp;
else
return X86_GR32_AO_64;
} else {
- if (hasFP(MF))
+ if (RI->hasFP(MF))
return X86_GR32_AO_32_fp;
else
return X86_GR32_AO_32;
@@ -326,14 +331,15 @@
GR32Class::iterator
GR32Class::allocation_order_end(const MachineFunction &MF) const {
const TargetMachine &TM = MF.getTarget();
+ const MRegisterInfo *RI = TM.getRegisterInfo();
const X86Subtarget &Subtarget = TM.getSubtarget<X86Subtarget>();
if (Subtarget.is64Bit()) {
- if (hasFP(MF))
+ if (RI->hasFP(MF))
return X86_GR32_AO_64_fp+(sizeof(X86_GR32_AO_64_fp)/sizeof(unsigned));
else
return X86_GR32_AO_64 + (sizeof(X86_GR32_AO_64) / sizeof(unsigned));
} else {
- if (hasFP(MF))
+ if (RI->hasFP(MF))
return X86_GR32_AO_32_fp+(sizeof(X86_GR32_AO_32_fp)/sizeof(unsigned));
else
return X86_GR32_AO_32 + (sizeof(X86_GR32_AO_32) / sizeof(unsigned));
@@ -352,7 +358,9 @@
let MethodBodies = [{
GR64Class::iterator
GR64Class::allocation_order_end(const MachineFunction &MF) const {
- if (hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
+ const TargetMachine &TM = MF.getTarget();
+ const MRegisterInfo *RI = TM.getRegisterInfo();
+ if (RI->hasFP(MF)) // Does the function dedicate RBP to being a frame ptr?
return end()-2; // If so, don't allocate RSP or RBP
else
return end()-1; // If not, just don't allocate RSP