commit dd6fbd11368b9d9ae82f8620a4aa7af9b8baf47c
author Chris Lattner <sabre@nondot.org> Mon Mar 08 18:59:49 2010 +0000
committer Chris Lattner <sabre@nondot.org> Mon Mar 08 18:59:49 2010 +0000
tree 030ea384b8cbe43e6686a755ed326d41390b0e39
parent 3485b51c4d962de994b389d6ae10106c97e89cf6

disambiguate some types, add a fixme about some 
inconsistent intrinsics.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97959 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/CellSPU/CellSDKIntrinsics.td

diff --git a/lib/Target/CellSPU/CellSDKIntrinsics.td b/lib/Target/CellSPU/CellSDKIntrinsics.td
index 5d759a4..1fe7aff 100644
--- a/lib/Target/CellSPU/CellSDKIntrinsics.td
+++ b/lib/Target/CellSPU/CellSDKIntrinsics.td
@@ -205,6 +205,7 @@
 // Shift/rotate intrinsics:
 //===----------------------------------------------------------------------===//
 
+/* FIXME: These have (currently unenforced) type conflicts. */
 def CellSDKshli:
   Pat<(int_spu_si_shli (v4i32 VECREG:$rA), uimm7:$val),
       (SHLIv4i32 VECREG:$rA, uimm7:$val)>;

lib/Target/CellSPU/SPUInstrInfo.td

diff --git a/lib/Target/CellSPU/SPUInstrInfo.td b/lib/Target/CellSPU/SPUInstrInfo.td
index f24ffd2..b96b64e 100644
--- a/lib/Target/CellSPU/SPUInstrInfo.td
+++ b/lib/Target/CellSPU/SPUInstrInfo.td
@@ -2370,7 +2370,7 @@
 class ROTHVecInst<ValueType vectype>:
     ROTHInst<(outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB),
              [(set (vectype VECREG:$rT),
-                   (SPUvec_rotl VECREG:$rA, VECREG:$rB))]>;
+                   (SPUvec_rotl VECREG:$rA, (v8i16 VECREG:$rB)))]>;
 
 class ROTHRegInst<RegisterClass rclass>:
     ROTHInst<(outs rclass:$rT), (ins rclass:$rA, rclass:$rB),

lib/Target/CellSPU/SPUMathInstr.td

diff --git a/lib/Target/CellSPU/SPUMathInstr.td b/lib/Target/CellSPU/SPUMathInstr.td
index 80ebde3..ed7129e 100644
--- a/lib/Target/CellSPU/SPUMathInstr.td
+++ b/lib/Target/CellSPU/SPUMathInstr.td
@@ -45,9 +45,9 @@
 def MPYv4i32:
   Pat<(mul (v4i32 VECREG:$rA), (v4i32 VECREG:$rB)),
       (Av4i32
-        (Av4i32 (MPYHv4i32 VECREG:$rA, VECREG:$rB),
-                (MPYHv4i32 VECREG:$rB, VECREG:$rA)),
-        (MPYUv4i32 VECREG:$rA, VECREG:$rB))>;
+        (v4i32 (Av4i32 (v4i32 (MPYHv4i32 VECREG:$rA, VECREG:$rB)),
+                       (v4i32 (MPYHv4i32 VECREG:$rB, VECREG:$rA)))),
+        (v4i32 (MPYUv4i32 VECREG:$rA, VECREG:$rB)))>;
 
 def MPYi32:
   Pat<(mul R32C:$rA, R32C:$rB),

lib/Target/CellSPU/SPUNodes.td

diff --git a/lib/Target/CellSPU/SPUNodes.td b/lib/Target/CellSPU/SPUNodes.td
index c722e4b..8507861 100644
--- a/lib/Target/CellSPU/SPUNodes.td
+++ b/lib/Target/CellSPU/SPUNodes.td
@@ -26,7 +26,7 @@
 // Operand constraints:
 //===----------------------------------------------------------------------===//
 
-def SDT_SPUCall   : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
+def SDT_SPUCall   : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
 def SPUcall       : SDNode<"SPUISD::CALL", SDT_SPUCall,
                            [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;