add support for referencing registers and immediates,
building the tree to represent them but not emitting
table entries for them yet.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@96617 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/utils/TableGen/DAGISelMatcher.cpp b/utils/TableGen/DAGISelMatcher.cpp
index 8b8c9bf..fdefe46 100644
--- a/utils/TableGen/DAGISelMatcher.cpp
+++ b/utils/TableGen/DAGISelMatcher.cpp
@@ -10,6 +10,7 @@
#include "DAGISelMatcher.h"
#include "CodeGenDAGPatterns.h"
#include "CodeGenTarget.h"
+#include "Record.h"
#include "llvm/Support/raw_ostream.h"
using namespace llvm;
@@ -117,3 +118,19 @@
OS.indent(indent) << "CheckChainCompatibleMatcherNode " << PreviousOp << "\n";
printNext(OS, indent);
}
+
+void EmitIntegerMatcherNode::print(raw_ostream &OS, unsigned indent) const {
+ OS.indent(indent) << "EmitIntegerMatcherNode " << Val << " VT=" << VT << '\n';
+ printNext(OS, indent);
+}
+
+void EmitRegisterMatcherNode::print(raw_ostream &OS, unsigned indent) const {
+ OS.indent(indent) << "EmitRegisterMatcherNode ";
+ if (Reg)
+ OS << Reg->getName();
+ else
+ OS << "zero_reg";
+ OS << " VT=" << VT << '\n';
+ printNext(OS, indent);
+}
+