Remove more non-DebugLoc versions of getNode.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63969 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index ebe4710..dca3498 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4075,7 +4075,8 @@
if (UnsafeFPMath && N1CFP && N0.getOpcode() == ISD::FMUL &&
N0.getNode()->hasOneUse() && isa<ConstantFPSDNode>(N0.getOperand(1)))
return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0.getOperand(0),
- DAG.getNode(ISD::FMUL, VT, N0.getOperand(1), N1));
+ DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT,
+ N0.getOperand(1), N1));
return SDValue();
}
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index d29b4df..92b7b30 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -1110,7 +1110,7 @@
Hi = DAG.getNode(ISD::SRA, dl, NVT, InH,
DAG.getConstant(NVTBits-1, ShTy));
} else {
- Lo = DAG.getNode(ISD::OR, NVT,
+ Lo = DAG.getNode(ISD::OR, dl, NVT,
DAG.getNode(ISD::SRL, dl, NVT, InL,
DAG.getConstant(Amt, ShTy)),
DAG.getNode(ISD::SHL, dl, NVT, InH,
@@ -2205,7 +2205,7 @@
DAG.getConstant(NVT.getSizeInBits() - ExcessBits,
TLI.getPointerTy()));
Hi = DAG.getNode(ISD::OR, dl, NVT, Hi,
- DAG.getNode(ISD::SRL, NVT, Lo,
+ DAG.getNode(ISD::SRL, dl, NVT, Lo,
DAG.getConstant(ExcessBits,
TLI.getPointerTy())));
}
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
index ed4a891..ced2e1f 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
@@ -154,7 +154,7 @@
if (Idx.getValueType().bitsLT(TLI.getPointerTy()))
Idx = DAG.getNode(ISD::ZERO_EXTEND, dl, TLI.getPointerTy(), Idx);
- Idx = DAG.getNode(ISD::ADD, Idx.getValueType(), Idx, Idx);
+ Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx, Idx);
Lo = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NewVT, NewVec, Idx);
Idx = DAG.getNode(ISD::ADD, dl, Idx.getValueType(), Idx,
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 581bdef..5985614 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2428,11 +2428,6 @@
return SDValue();
}
-SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
- SDValue N1, SDValue N2) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
SDValue N1, SDValue N2) {
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
@@ -2793,11 +2788,6 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
- SDValue N1, SDValue N2, SDValue N3) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2, N3);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
SDValue N1, SDValue N2, SDValue N3) {
// Perform various simplifications.
@@ -2879,12 +2869,6 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
- SDValue N1, SDValue N2, SDValue N3,
- SDValue N4) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2, N3, N4);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
SDValue N1, SDValue N2, SDValue N3,
SDValue N4) {
@@ -2892,12 +2876,6 @@
return getNode(Opcode, DL, VT, Ops, 4);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, MVT VT,
- SDValue N1, SDValue N2, SDValue N3,
- SDValue N4, SDValue N5) {
- return getNode(Opcode, DebugLoc::getUnknownLoc(), VT, N1, N2, N3, N4, N5);
-}
-
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
SDValue N1, SDValue N2, SDValue N3,
SDValue N4, SDValue N5) {
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 0f7db6e..06fbf2a 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -723,6 +723,7 @@
/// constant and return true.
bool TargetLowering::TargetLoweringOpt::ShrinkDemandedConstant(SDValue Op,
const APInt &Demanded) {
+ DebugLoc dl = Op.getDebugLoc();
// FIXME: ISD::SELECT, ISD::SELECT_CC
switch (Op.getOpcode()) {
default: break;
@@ -732,7 +733,7 @@
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
if (C->getAPIntValue().intersects(~Demanded)) {
MVT VT = Op.getValueType();
- SDValue New = DAG.getNode(Op.getOpcode(), VT, Op.getOperand(0),
+ SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
DAG.getConstant(Demanded &
C->getAPIntValue(),
VT));
@@ -890,7 +891,7 @@
// (but not both) turn this into an *inclusive* or.
// e.g. (A & C1)^(B & C2) -> (A & C1)|(B & C2) iff C1&C2 == 0
if ((NewMask & ~KnownZero & ~KnownZero2) == 0)
- return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, Op.getValueType(),
+ return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::OR, dl, Op.getValueType(),
Op.getOperand(0),
Op.getOperand(1)));
@@ -1867,7 +1868,7 @@
case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
Temp = DAG.getNOT(dl, N0, MVT::i1);
- N0 = DAG.getNode(ISD::AND, MVT::i1, N1, Temp);
+ N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;