Build system infrastructure for multiple tblgens.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@141266 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/CMakeLists.txt b/CMakeLists.txt
index 874f381..039f619 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -187,6 +187,10 @@
include(AddLLVM)
include(TableGen)
+macro(llvm_tablegen)
+ tablegen(LLVM ${ARGN})
+endmacro()
+
if( MINGW )
# People report that -O3 is unreliable on MinGW. The traditional
# build also uses -O2 for that reason:
@@ -197,18 +201,8 @@
add_subdirectory(lib/Support)
add_subdirectory(lib/TableGen)
-set(LLVM_TABLEGEN "tblgen" CACHE
- STRING "Native TableGen executable. Saves building one when cross-compiling.")
-# Effective tblgen executable to be used:
-set(LLVM_TABLEGEN_EXE ${LLVM_TABLEGEN})
-
add_subdirectory(utils/TableGen)
-if( CMAKE_CROSSCOMPILING )
- # This adds a dependency on target `tblgen', so must go after utils/TableGen
- include( CrossCompileLLVM )
-endif( CMAKE_CROSSCOMPILING )
-
add_subdirectory(include/llvm)
add_subdirectory(lib)
diff --git a/Makefile.rules b/Makefile.rules
index c12ba1d..4d30d45 100644
--- a/Makefile.rules
+++ b/Makefile.rules
@@ -450,11 +450,11 @@
ifndef LLVMAS
LLVMAS := $(LLVMToolDir)/llvm-as$(EXEEXT)
endif
-ifndef TBLGEN
+ifndef LLVM_TBLGEN
ifeq ($(LLVM_CROSS_COMPILING),1)
- TBLGEN := $(BuildLLVMToolDir)/tblgen$(BUILD_EXEEXT)
+ LLVM_TBLGEN := $(BuildLLVMToolDir)/llvm-tblgen$(BUILD_EXEEXT)
else
- TBLGEN := $(LLVMToolDir)/tblgen$(EXEEXT)
+ LLVM_TBLGEN := $(LLVMToolDir)/llvm-tblgen$(EXEEXT)
endif
endif
LLVM_CONFIG := $(LLVMToolDir)/llvm-config
@@ -684,10 +684,11 @@
# When compiling under Mingw/Cygwin, the tblgen tool expects Windows
# paths. In this case, the SYSPATH function (defined in
# Makefile.config) transforms Unix paths into Windows paths.
-TableGen = $(TBLGEN) -I $(call SYSPATH, $(PROJ_SRC_DIR)) \
+TableGen.Flags= -I $(call SYSPATH, $(PROJ_SRC_DIR)) \
-I $(call SYSPATH, $(LLVM_SRC_ROOT)/include) \
-I $(call SYSPATH, $(PROJ_SRC_ROOT)/include) \
-I $(call SYSPATH, $(PROJ_SRC_ROOT)/lib/Target)
+LLVMTableGen = $(LLVM_TBLGEN) $(TableGen.Flags)
Archive = $(AR) $(AR.Flags)
LArchive = $(LLVMToolDir)/llvm-ar rcsf
@@ -1700,87 +1701,87 @@
$(LLVM_SRC_ROOT)/include/llvm/CodeGen/ValueTypes.td) \
$(wildcard $(LLVM_SRC_ROOT)/include/llvm/Intrinsics*.td)
-# All of these files depend on tblgen and the .td files.
-$(INCTMPFiles) : $(TBLGEN) $(TDFiles)
+# All .inc.tmp files depend on the .td files.
+$(INCTMPFiles) : $(TDFiles)
$(TARGET:%=$(ObjDir)/%GenRegisterInfo.inc.tmp): \
-$(ObjDir)/%GenRegisterInfo.inc.tmp : %.td $(ObjDir)/.dir
+$(ObjDir)/%GenRegisterInfo.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
$(Echo) "Building $(<F) register info implementation with tblgen"
- $(Verb) $(TableGen) -gen-register-info -o $(call SYSPATH, $@) $<
+ $(Verb) $(LLVMTableGen) -gen-register-info -o $(call SYSPATH, $@) $<
$(TARGET:%=$(ObjDir)/%GenInstrInfo.inc.tmp): \
-$(ObjDir)/%GenInstrInfo.inc.tmp : %.td $(ObjDir)/.dir
+$(ObjDir)/%GenInstrInfo.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
$(Echo) "Building $(<F) instruction information with tblgen"
- $(Verb) $(TableGen) -gen-instr-info -o $(call SYSPATH, $@) $<
+ $(Verb) $(LLVMTableGen) -gen-instr-info -o $(call SYSPATH, $@) $<
$(TARGET:%=$(ObjDir)/%GenAsmWriter.inc.tmp): \
-$(ObjDir)/%GenAsmWriter.inc.tmp : %.td $(ObjDir)/.dir
+$(ObjDir)/%GenAsmWriter.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
$(Echo) "Building $(<F) assembly writer with tblgen"
- $(Verb) $(TableGen) -gen-asm-writer -o $(call SYSPATH, $@) $<
+ $(Verb) $(LLVMTableGen) -gen-asm-writer -o $(call SYSPATH, $@) $<
$(TARGET:%=$(ObjDir)/%GenAsmWriter1.inc.tmp): \
-$(ObjDir)/%GenAsmWriter1.inc.tmp : %.td $(ObjDir)/.dir
+$(ObjDir)/%GenAsmWriter1.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
$(Echo) "Building $(<F) assembly writer #1 with tblgen"
- $(Verb) $(TableGen) -gen-asm-writer -asmwriternum=1 -o $(call SYSPATH, $@) $<
+ $(Verb) $(LLVMTableGen) -gen-asm-writer -asmwriternum=1 -o $(call SYSPATH, $@) $<
$(TARGET:%=$(ObjDir)/%GenAsmMatcher.inc.tmp): \
-$(ObjDir)/%GenAsmMatcher.inc.tmp : %.td $(ObjDir)/.dir
+$(ObjDir)/%GenAsmMatcher.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
$(Echo) "Building $(<F) assembly matcher with tblgen"
- $(Verb) $(TableGen) -gen-asm-matcher -o $(call SYSPATH, $@) $<
+ $(Verb) $(LLVMTableGen) -gen-asm-matcher -o $(call SYSPATH, $@) $<
$(TARGET:%=$(ObjDir)/%GenMCCodeEmitter.inc.tmp): \
-$(ObjDir)/%GenMCCodeEmitter.inc.tmp: %.td $(ObjDir)/.dir
+$(ObjDir)/%GenMCCodeEmitter.inc.tmp: %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
$(Echo) "Building $(<F) MC code emitter with tblgen"
- $(Verb) $(TableGen) -gen-emitter -mc-emitter -o $(call SYSPATH, $@) $<
+ $(Verb) $(LLVMTableGen) -gen-emitter -mc-emitter -o $(call SYSPATH, $@) $<
$(TARGET:%=$(ObjDir)/%GenMCPseudoLowering.inc.tmp): \
-$(ObjDir)/%GenMCPseudoLowering.inc.tmp: %.td $(ObjDir)/.dir
+$(ObjDir)/%GenMCPseudoLowering.inc.tmp: %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
$(Echo) "Building $(<F) MC Pseudo instruction expander with tblgen"
- $(Verb) $(TableGen) -gen-pseudo-lowering -o $(call SYSPATH, $@) $<
+ $(Verb) $(LLVMTableGen) -gen-pseudo-lowering -o $(call SYSPATH, $@) $<
$(TARGET:%=$(ObjDir)/%GenCodeEmitter.inc.tmp): \
-$(ObjDir)/%GenCodeEmitter.inc.tmp: %.td $(ObjDir)/.dir
+$(ObjDir)/%GenCodeEmitter.inc.tmp: %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
$(Echo) "Building $(<F) code emitter with tblgen"
- $(Verb) $(TableGen) -gen-emitter -o $(call SYSPATH, $@) $<
+ $(Verb) $(LLVMTableGen) -gen-emitter -o $(call SYSPATH, $@) $<
$(TARGET:%=$(ObjDir)/%GenDAGISel.inc.tmp): \
-$(ObjDir)/%GenDAGISel.inc.tmp : %.td $(ObjDir)/.dir
+$(ObjDir)/%GenDAGISel.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
$(Echo) "Building $(<F) DAG instruction selector implementation with tblgen"
- $(Verb) $(TableGen) -gen-dag-isel -o $(call SYSPATH, $@) $<
+ $(Verb) $(LLVMTableGen) -gen-dag-isel -o $(call SYSPATH, $@) $<
$(TARGET:%=$(ObjDir)/%GenDisassemblerTables.inc.tmp): \
-$(ObjDir)/%GenDisassemblerTables.inc.tmp : %.td $(ObjDir)/.dir
+$(ObjDir)/%GenDisassemblerTables.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
$(Echo) "Building $(<F) disassembly tables with tblgen"
- $(Verb) $(TableGen) -gen-disassembler -o $(call SYSPATH, $@) $<
+ $(Verb) $(LLVMTableGen) -gen-disassembler -o $(call SYSPATH, $@) $<
$(TARGET:%=$(ObjDir)/%GenEDInfo.inc.tmp): \
-$(ObjDir)/%GenEDInfo.inc.tmp : %.td $(ObjDir)/.dir
+$(ObjDir)/%GenEDInfo.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
$(Echo) "Building $(<F) enhanced disassembly information with tblgen"
- $(Verb) $(TableGen) -gen-enhanced-disassembly-info -o $(call SYSPATH, $@) $<
+ $(Verb) $(LLVMTableGen) -gen-enhanced-disassembly-info -o $(call SYSPATH, $@) $<
$(TARGET:%=$(ObjDir)/%GenFastISel.inc.tmp): \
-$(ObjDir)/%GenFastISel.inc.tmp : %.td $(ObjDir)/.dir
+$(ObjDir)/%GenFastISel.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
$(Echo) "Building $(<F) \"fast\" instruction selector implementation with tblgen"
- $(Verb) $(TableGen) -gen-fast-isel -o $(call SYSPATH, $@) $<
+ $(Verb) $(LLVMTableGen) -gen-fast-isel -o $(call SYSPATH, $@) $<
$(TARGET:%=$(ObjDir)/%GenSubtargetInfo.inc.tmp): \
-$(ObjDir)/%GenSubtargetInfo.inc.tmp : %.td $(ObjDir)/.dir
+$(ObjDir)/%GenSubtargetInfo.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
$(Echo) "Building $(<F) subtarget information with tblgen"
- $(Verb) $(TableGen) -gen-subtarget -o $(call SYSPATH, $@) $<
+ $(Verb) $(LLVMTableGen) -gen-subtarget -o $(call SYSPATH, $@) $<
$(TARGET:%=$(ObjDir)/%GenCallingConv.inc.tmp): \
-$(ObjDir)/%GenCallingConv.inc.tmp : %.td $(ObjDir)/.dir
+$(ObjDir)/%GenCallingConv.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
$(Echo) "Building $(<F) calling convention information with tblgen"
- $(Verb) $(TableGen) -gen-callingconv -o $(call SYSPATH, $@) $<
+ $(Verb) $(LLVMTableGen) -gen-callingconv -o $(call SYSPATH, $@) $<
$(TARGET:%=$(ObjDir)/%GenIntrinsics.inc.tmp): \
-$(ObjDir)/%GenIntrinsics.inc.tmp : %.td $(ObjDir)/.dir
+$(ObjDir)/%GenIntrinsics.inc.tmp : %.td $(ObjDir)/.dir $(LLVM_TBLGEN)
$(Echo) "Building $(<F) intrinsics information with tblgen"
- $(Verb) $(TableGen) -gen-tgt-intrinsic -o $(call SYSPATH, $@) $<
+ $(Verb) $(LLVMTableGen) -gen-tgt-intrinsic -o $(call SYSPATH, $@) $<
-$(ObjDir)/ARMGenDecoderTables.inc.tmp : ARM.td $(ObjDir)/.dir
+$(ObjDir)/ARMGenDecoderTables.inc.tmp : ARM.td $(ObjDir)/.dir $(LLVM_TBLGEN)
$(Echo) "Building $(<F) decoder tables with tblgen"
- $(Verb) $(TableGen) -gen-arm-decoder -o $(call SYSPATH, $@) $<
+ $(Verb) $(LLVMTableGen) -gen-arm-decoder -o $(call SYSPATH, $@) $<
clean-local::
diff --git a/cmake/modules/CrossCompileLLVM.cmake b/cmake/modules/CrossCompileLLVM.cmake
deleted file mode 100644
index 98e60a5..0000000
--- a/cmake/modules/CrossCompileLLVM.cmake
+++ /dev/null
@@ -1,26 +0,0 @@
-
-if( ${LLVM_TABLEGEN} STREQUAL "tblgen" )
- set(CX_NATIVE_TG_DIR "${CMAKE_BINARY_DIR}/native")
- set(LLVM_TABLEGEN_EXE "${CX_NATIVE_TG_DIR}/bin/tblgen")
-
- add_custom_command(OUTPUT ${CX_NATIVE_TG_DIR}
- COMMAND ${CMAKE_COMMAND} -E make_directory ${CX_NATIVE_TG_DIR}
- COMMENT "Creating ${CX_NATIVE_TG_DIR}...")
-
- add_custom_command(OUTPUT ${CX_NATIVE_TG_DIR}/CMakeCache.txt
- COMMAND ${CMAKE_COMMAND} -UMAKE_TOOLCHAIN_FILE -DCMAKE_BUILD_TYPE=Release ${CMAKE_SOURCE_DIR}
- WORKING_DIRECTORY ${CX_NATIVE_TG_DIR}
- DEPENDS ${CX_NATIVE_TG_DIR}
- COMMENT "Configuring native TableGen...")
-
- add_custom_command(OUTPUT ${LLVM_TABLEGEN_EXE}
- COMMAND ${CMAKE_BUILD_TOOL}
- DEPENDS ${CX_NATIVE_TG_DIR}/CMakeCache.txt
- WORKING_DIRECTORY ${CX_NATIVE_TG_DIR}/utils/TableGen
- COMMENT "Building native TableGen...")
- add_custom_target(NativeTableGen DEPENDS ${LLVM_TABLEGEN_EXE})
-
- add_dependencies(tblgen NativeTableGen)
-
- set_directory_properties(PROPERTIES ADDITIONAL_MAKE_CLEAN_FILES ${CX_NATIVE_TG_DIR})
-endif()
diff --git a/cmake/modules/TableGen.cmake b/cmake/modules/TableGen.cmake
index 580b9a9..3dc820b 100644
--- a/cmake/modules/TableGen.cmake
+++ b/cmake/modules/TableGen.cmake
@@ -2,7 +2,7 @@
# Extra parameters for `tblgen' may come after `ofn' parameter.
# Adds the name of the generated file to TABLEGEN_OUTPUT.
-macro(tablegen ofn)
+macro(tablegen project ofn)
file(GLOB local_tds "*.td")
file(GLOB_RECURSE global_tds "${LLVM_MAIN_SRC_DIR}/include/llvm/*.td")
@@ -14,14 +14,14 @@
endif()
add_custom_command(OUTPUT ${CMAKE_CURRENT_BINARY_DIR}/${ofn}.tmp
# Generate tablegen output in a temporary file.
- COMMAND ${LLVM_TABLEGEN_EXE} ${ARGN} -I ${CMAKE_CURRENT_SOURCE_DIR}
+ COMMAND ${${project}_TABLEGEN_EXE} ${ARGN} -I ${CMAKE_CURRENT_SOURCE_DIR}
-I ${LLVM_MAIN_SRC_DIR}/lib/Target -I ${LLVM_MAIN_INCLUDE_DIR}
${LLVM_TARGET_DEFINITIONS_ABSOLUTE}
-o ${CMAKE_CURRENT_BINARY_DIR}/${ofn}.tmp
# The file in LLVM_TARGET_DEFINITIONS may be not in the current
# directory and local_tds may not contain it, so we must
# explicitly list it here:
- DEPENDS ${LLVM_TABLEGEN_EXE} ${local_tds} ${global_tds}
+ DEPENDS ${${project}_TABLEGEN_EXE} ${local_tds} ${global_tds}
${LLVM_TARGET_DEFINITIONS_ABSOLUTE}
COMMENT "Building ${ofn}..."
)
@@ -53,3 +53,73 @@
add_dependencies(${target} ${LLVM_COMMON_DEPENDS})
endif( TABLEGEN_OUTPUT )
endfunction()
+
+if(CMAKE_CROSSCOMPILING)
+ set(CX_NATIVE_TG_DIR "${CMAKE_BINARY_DIR}/native")
+
+ add_custom_command(OUTPUT ${CX_NATIVE_TG_DIR}
+ COMMAND ${CMAKE_COMMAND} -E make_directory ${CX_NATIVE_TG_DIR}
+ COMMENT "Creating ${CX_NATIVE_TG_DIR}...")
+
+ add_custom_command(OUTPUT ${CX_NATIVE_TG_DIR}/CMakeCache.txt
+ COMMAND ${CMAKE_COMMAND} -UMAKE_TOOLCHAIN_FILE -DCMAKE_BUILD_TYPE=Release
+ -DLLVM_BUILD_POLLY=OFF ${CMAKE_SOURCE_DIR}
+ WORKING_DIRECTORY ${CX_NATIVE_TG_DIR}
+ DEPENDS ${CX_NATIVE_TG_DIR}
+ COMMENT "Configuring native TableGen...")
+
+ add_custom_target(ConfigureNativeTableGen DEPENDS ${CX_NATIVE_TG_DIR}/CMakeCache.txt)
+
+ set_directory_properties(PROPERTIES ADDITIONAL_MAKE_CLEAN_FILES ${CX_NATIVE_TG_DIR})
+endif()
+
+macro(add_tablegen target project)
+ set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${LLVM_TOOLS_BINARY_DIR})
+
+ add_llvm_utility(${target} ${ARGN})
+
+ set(${project}_TABLEGEN "${target}" CACHE
+ STRING "Native TableGen executable. Saves building one when cross-compiling.")
+
+ # Upgrade existing LLVM_TABLEGEN setting.
+ if(${project} STREQUAL LLVM)
+ if(${LLVM_TABLEGEN} STREQUAL tblgen)
+ set(LLVM_TABLEGEN "${target}" CACHE
+ STRING "Native TableGen executable. Saves building one when cross-compiling."
+ FORCE)
+ endif()
+ endif()
+
+ # Effective tblgen executable to be used:
+ set(${project}_TABLEGEN_EXE ${${project}_TABLEGEN} PARENT_SCOPE)
+
+ if(CMAKE_CROSSCOMPILING)
+ if( ${${project}_TABLEGEN} STREQUAL "${target}" )
+ set(${project}_TABLEGEN_EXE "${CX_NATIVE_TG_DIR}/bin/${target}")
+ set(${project}_TABLEGEN_EXE ${${project}_TABLEGEN_EXE} PARENT_SCOPE)
+
+ add_custom_command(OUTPUT ${${project}_TABLEGEN_EXE}
+ COMMAND ${CMAKE_BUILD_TOOL} ${target}
+ DEPENDS ${CX_NATIVE_TG_DIR}/CMakeCache.txt
+ WORKING_DIRECTORY ${CX_NATIVE_TG_DIR}
+ COMMENT "Building native TableGen...")
+ add_custom_target(${project}NativeTableGen DEPENDS ${${project}_TABLEGEN_EXE})
+ add_dependencies(${project}NativeTableGen ConfigureNativeTableGen)
+
+ add_dependencies(${target} ${project}NativeTableGen)
+ endif()
+ endif()
+
+ target_link_libraries(${target} LLVMSupport LLVMTableGen)
+ if( MINGW )
+ target_link_libraries(${target} imagehlp psapi)
+ if(CMAKE_SIZEOF_VOID_P MATCHES "8")
+ set_target_properties(${target} PROPERTIES LINK_FLAGS -Wl,--stack,16777216)
+ endif(CMAKE_SIZEOF_VOID_P MATCHES "8")
+ endif( MINGW )
+ if( LLVM_ENABLE_THREADS AND HAVE_LIBPTHREAD AND NOT BEOS )
+ target_link_libraries(${target} pthread)
+ endif()
+
+ install(TARGETS ${target} RUNTIME DESTINATION bin)
+endmacro()
diff --git a/include/llvm/CMakeLists.txt b/include/llvm/CMakeLists.txt
index 0c3ca1c..7956f8c 100644
--- a/include/llvm/CMakeLists.txt
+++ b/include/llvm/CMakeLists.txt
@@ -1,6 +1,6 @@
set(LLVM_TARGET_DEFINITIONS Intrinsics.td)
-tablegen(Intrinsics.gen -gen-intrinsic)
+llvm_tablegen(Intrinsics.gen -gen-intrinsic)
add_custom_target(intrinsics_gen ALL
DEPENDS ${llvm_builded_incs_dir}/Intrinsics.gen)
diff --git a/lib/Target/ARM/CMakeLists.txt b/lib/Target/ARM/CMakeLists.txt
index dc9f4d6..f045e83 100644
--- a/lib/Target/ARM/CMakeLists.txt
+++ b/lib/Target/ARM/CMakeLists.txt
@@ -1,18 +1,18 @@
set(LLVM_TARGET_DEFINITIONS ARM.td)
-tablegen(ARMGenRegisterInfo.inc -gen-register-info)
-tablegen(ARMGenInstrInfo.inc -gen-instr-info)
-tablegen(ARMGenCodeEmitter.inc -gen-emitter)
-tablegen(ARMGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
-tablegen(ARMGenMCPseudoLowering.inc -gen-pseudo-lowering)
-tablegen(ARMGenAsmWriter.inc -gen-asm-writer)
-tablegen(ARMGenAsmMatcher.inc -gen-asm-matcher)
-tablegen(ARMGenDAGISel.inc -gen-dag-isel)
-tablegen(ARMGenFastISel.inc -gen-fast-isel)
-tablegen(ARMGenCallingConv.inc -gen-callingconv)
-tablegen(ARMGenSubtargetInfo.inc -gen-subtarget)
-tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info)
-tablegen(ARMGenDisassemblerTables.inc -gen-disassembler)
+llvm_tablegen(ARMGenRegisterInfo.inc -gen-register-info)
+llvm_tablegen(ARMGenInstrInfo.inc -gen-instr-info)
+llvm_tablegen(ARMGenCodeEmitter.inc -gen-emitter)
+llvm_tablegen(ARMGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
+llvm_tablegen(ARMGenMCPseudoLowering.inc -gen-pseudo-lowering)
+llvm_tablegen(ARMGenAsmWriter.inc -gen-asm-writer)
+llvm_tablegen(ARMGenAsmMatcher.inc -gen-asm-matcher)
+llvm_tablegen(ARMGenDAGISel.inc -gen-dag-isel)
+llvm_tablegen(ARMGenFastISel.inc -gen-fast-isel)
+llvm_tablegen(ARMGenCallingConv.inc -gen-callingconv)
+llvm_tablegen(ARMGenSubtargetInfo.inc -gen-subtarget)
+llvm_tablegen(ARMGenEDInfo.inc -gen-enhanced-disassembly-info)
+llvm_tablegen(ARMGenDisassemblerTables.inc -gen-disassembler)
add_public_tablegen_target(ARMCommonTableGen)
add_llvm_target(ARMCodeGen
diff --git a/lib/Target/Alpha/CMakeLists.txt b/lib/Target/Alpha/CMakeLists.txt
index 63412c1..a6d5516 100644
--- a/lib/Target/Alpha/CMakeLists.txt
+++ b/lib/Target/Alpha/CMakeLists.txt
@@ -1,11 +1,11 @@
set(LLVM_TARGET_DEFINITIONS Alpha.td)
-tablegen(AlphaGenRegisterInfo.inc -gen-register-info)
-tablegen(AlphaGenInstrInfo.inc -gen-instr-info)
-tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)
-tablegen(AlphaGenDAGISel.inc -gen-dag-isel)
-tablegen(AlphaGenCallingConv.inc -gen-callingconv)
-tablegen(AlphaGenSubtargetInfo.inc -gen-subtarget)
+llvm_tablegen(AlphaGenRegisterInfo.inc -gen-register-info)
+llvm_tablegen(AlphaGenInstrInfo.inc -gen-instr-info)
+llvm_tablegen(AlphaGenAsmWriter.inc -gen-asm-writer)
+llvm_tablegen(AlphaGenDAGISel.inc -gen-dag-isel)
+llvm_tablegen(AlphaGenCallingConv.inc -gen-callingconv)
+llvm_tablegen(AlphaGenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(AlphaCommonTableGen)
add_llvm_target(AlphaCodeGen
diff --git a/lib/Target/Blackfin/CMakeLists.txt b/lib/Target/Blackfin/CMakeLists.txt
index a0b2e93..94d05fb 100644
--- a/lib/Target/Blackfin/CMakeLists.txt
+++ b/lib/Target/Blackfin/CMakeLists.txt
@@ -1,12 +1,12 @@
set(LLVM_TARGET_DEFINITIONS Blackfin.td)
-tablegen(BlackfinGenRegisterInfo.inc -gen-register-info)
-tablegen(BlackfinGenInstrInfo.inc -gen-instr-info)
-tablegen(BlackfinGenAsmWriter.inc -gen-asm-writer)
-tablegen(BlackfinGenDAGISel.inc -gen-dag-isel)
-tablegen(BlackfinGenSubtargetInfo.inc -gen-subtarget)
-tablegen(BlackfinGenCallingConv.inc -gen-callingconv)
-tablegen(BlackfinGenIntrinsics.inc -gen-tgt-intrinsic)
+llvm_tablegen(BlackfinGenRegisterInfo.inc -gen-register-info)
+llvm_tablegen(BlackfinGenInstrInfo.inc -gen-instr-info)
+llvm_tablegen(BlackfinGenAsmWriter.inc -gen-asm-writer)
+llvm_tablegen(BlackfinGenDAGISel.inc -gen-dag-isel)
+llvm_tablegen(BlackfinGenSubtargetInfo.inc -gen-subtarget)
+llvm_tablegen(BlackfinGenCallingConv.inc -gen-callingconv)
+llvm_tablegen(BlackfinGenIntrinsics.inc -gen-tgt-intrinsic)
add_public_tablegen_target(BlackfinCommonTableGen)
add_llvm_target(BlackfinCodeGen
diff --git a/lib/Target/CellSPU/CMakeLists.txt b/lib/Target/CellSPU/CMakeLists.txt
index c16e53c..158fb3e 100644
--- a/lib/Target/CellSPU/CMakeLists.txt
+++ b/lib/Target/CellSPU/CMakeLists.txt
@@ -1,12 +1,12 @@
set(LLVM_TARGET_DEFINITIONS SPU.td)
-tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
-tablegen(SPUGenCodeEmitter.inc -gen-emitter)
-tablegen(SPUGenRegisterInfo.inc -gen-register-info)
-tablegen(SPUGenInstrInfo.inc -gen-instr-info)
-tablegen(SPUGenDAGISel.inc -gen-dag-isel)
-tablegen(SPUGenSubtargetInfo.inc -gen-subtarget)
-tablegen(SPUGenCallingConv.inc -gen-callingconv)
+llvm_tablegen(SPUGenAsmWriter.inc -gen-asm-writer)
+llvm_tablegen(SPUGenCodeEmitter.inc -gen-emitter)
+llvm_tablegen(SPUGenRegisterInfo.inc -gen-register-info)
+llvm_tablegen(SPUGenInstrInfo.inc -gen-instr-info)
+llvm_tablegen(SPUGenDAGISel.inc -gen-dag-isel)
+llvm_tablegen(SPUGenSubtargetInfo.inc -gen-subtarget)
+llvm_tablegen(SPUGenCallingConv.inc -gen-callingconv)
add_public_tablegen_target(CellSPUCommonTableGen)
add_llvm_target(CellSPUCodeGen
diff --git a/lib/Target/MBlaze/CMakeLists.txt b/lib/Target/MBlaze/CMakeLists.txt
index 20b3b03..47b0db2 100644
--- a/lib/Target/MBlaze/CMakeLists.txt
+++ b/lib/Target/MBlaze/CMakeLists.txt
@@ -1,15 +1,15 @@
set(LLVM_TARGET_DEFINITIONS MBlaze.td)
-tablegen(MBlazeGenRegisterInfo.inc -gen-register-info)
-tablegen(MBlazeGenInstrInfo.inc -gen-instr-info)
-tablegen(MBlazeGenCodeEmitter.inc -gen-emitter)
-tablegen(MBlazeGenAsmWriter.inc -gen-asm-writer)
-tablegen(MBlazeGenAsmMatcher.inc -gen-asm-matcher)
-tablegen(MBlazeGenDAGISel.inc -gen-dag-isel)
-tablegen(MBlazeGenCallingConv.inc -gen-callingconv)
-tablegen(MBlazeGenSubtargetInfo.inc -gen-subtarget)
-tablegen(MBlazeGenIntrinsics.inc -gen-tgt-intrinsic)
-tablegen(MBlazeGenEDInfo.inc -gen-enhanced-disassembly-info)
+llvm_tablegen(MBlazeGenRegisterInfo.inc -gen-register-info)
+llvm_tablegen(MBlazeGenInstrInfo.inc -gen-instr-info)
+llvm_tablegen(MBlazeGenCodeEmitter.inc -gen-emitter)
+llvm_tablegen(MBlazeGenAsmWriter.inc -gen-asm-writer)
+llvm_tablegen(MBlazeGenAsmMatcher.inc -gen-asm-matcher)
+llvm_tablegen(MBlazeGenDAGISel.inc -gen-dag-isel)
+llvm_tablegen(MBlazeGenCallingConv.inc -gen-callingconv)
+llvm_tablegen(MBlazeGenSubtargetInfo.inc -gen-subtarget)
+llvm_tablegen(MBlazeGenIntrinsics.inc -gen-tgt-intrinsic)
+llvm_tablegen(MBlazeGenEDInfo.inc -gen-enhanced-disassembly-info)
add_public_tablegen_target(MBlazeCommonTableGen)
add_llvm_target(MBlazeCodeGen
diff --git a/lib/Target/MSP430/CMakeLists.txt b/lib/Target/MSP430/CMakeLists.txt
index 3840b03..0952b76 100644
--- a/lib/Target/MSP430/CMakeLists.txt
+++ b/lib/Target/MSP430/CMakeLists.txt
@@ -1,11 +1,11 @@
set(LLVM_TARGET_DEFINITIONS MSP430.td)
-tablegen(MSP430GenRegisterInfo.inc -gen-register-info)
-tablegen(MSP430GenInstrInfo.inc -gen-instr-info)
-tablegen(MSP430GenAsmWriter.inc -gen-asm-writer)
-tablegen(MSP430GenDAGISel.inc -gen-dag-isel)
-tablegen(MSP430GenCallingConv.inc -gen-callingconv)
-tablegen(MSP430GenSubtargetInfo.inc -gen-subtarget)
+llvm_tablegen(MSP430GenRegisterInfo.inc -gen-register-info)
+llvm_tablegen(MSP430GenInstrInfo.inc -gen-instr-info)
+llvm_tablegen(MSP430GenAsmWriter.inc -gen-asm-writer)
+llvm_tablegen(MSP430GenDAGISel.inc -gen-dag-isel)
+llvm_tablegen(MSP430GenCallingConv.inc -gen-callingconv)
+llvm_tablegen(MSP430GenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(MSP430CommonTableGen)
add_llvm_target(MSP430CodeGen
diff --git a/lib/Target/Mips/CMakeLists.txt b/lib/Target/Mips/CMakeLists.txt
index 9daa89e..1b4329b 100644
--- a/lib/Target/Mips/CMakeLists.txt
+++ b/lib/Target/Mips/CMakeLists.txt
@@ -1,11 +1,11 @@
set(LLVM_TARGET_DEFINITIONS Mips.td)
-tablegen(MipsGenRegisterInfo.inc -gen-register-info)
-tablegen(MipsGenInstrInfo.inc -gen-instr-info)
-tablegen(MipsGenAsmWriter.inc -gen-asm-writer)
-tablegen(MipsGenDAGISel.inc -gen-dag-isel)
-tablegen(MipsGenCallingConv.inc -gen-callingconv)
-tablegen(MipsGenSubtargetInfo.inc -gen-subtarget)
+llvm_tablegen(MipsGenRegisterInfo.inc -gen-register-info)
+llvm_tablegen(MipsGenInstrInfo.inc -gen-instr-info)
+llvm_tablegen(MipsGenAsmWriter.inc -gen-asm-writer)
+llvm_tablegen(MipsGenDAGISel.inc -gen-dag-isel)
+llvm_tablegen(MipsGenCallingConv.inc -gen-callingconv)
+llvm_tablegen(MipsGenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(MipsCommonTableGen)
add_llvm_target(MipsCodeGen
diff --git a/lib/Target/PTX/CMakeLists.txt b/lib/Target/PTX/CMakeLists.txt
index 2d5bc45..6e87b17 100644
--- a/lib/Target/PTX/CMakeLists.txt
+++ b/lib/Target/PTX/CMakeLists.txt
@@ -1,10 +1,10 @@
set(LLVM_TARGET_DEFINITIONS PTX.td)
-tablegen(PTXGenAsmWriter.inc -gen-asm-writer)
-tablegen(PTXGenDAGISel.inc -gen-dag-isel)
-tablegen(PTXGenInstrInfo.inc -gen-instr-info)
-tablegen(PTXGenRegisterInfo.inc -gen-register-info)
-tablegen(PTXGenSubtargetInfo.inc -gen-subtarget)
+llvm_tablegen(PTXGenAsmWriter.inc -gen-asm-writer)
+llvm_tablegen(PTXGenDAGISel.inc -gen-dag-isel)
+llvm_tablegen(PTXGenInstrInfo.inc -gen-instr-info)
+llvm_tablegen(PTXGenRegisterInfo.inc -gen-register-info)
+llvm_tablegen(PTXGenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(PTXCommonTableGen)
add_llvm_target(PTXCodeGen
diff --git a/lib/Target/PowerPC/CMakeLists.txt b/lib/Target/PowerPC/CMakeLists.txt
index ec0a918..73b4aba 100644
--- a/lib/Target/PowerPC/CMakeLists.txt
+++ b/lib/Target/PowerPC/CMakeLists.txt
@@ -1,13 +1,13 @@
set(LLVM_TARGET_DEFINITIONS PPC.td)
-tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
-tablegen(PPCGenCodeEmitter.inc -gen-emitter)
-tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
-tablegen(PPCGenRegisterInfo.inc -gen-register-info)
-tablegen(PPCGenInstrInfo.inc -gen-instr-info)
-tablegen(PPCGenDAGISel.inc -gen-dag-isel)
-tablegen(PPCGenCallingConv.inc -gen-callingconv)
-tablegen(PPCGenSubtargetInfo.inc -gen-subtarget)
+llvm_tablegen(PPCGenAsmWriter.inc -gen-asm-writer)
+llvm_tablegen(PPCGenCodeEmitter.inc -gen-emitter)
+llvm_tablegen(PPCGenMCCodeEmitter.inc -gen-emitter -mc-emitter)
+llvm_tablegen(PPCGenRegisterInfo.inc -gen-register-info)
+llvm_tablegen(PPCGenInstrInfo.inc -gen-instr-info)
+llvm_tablegen(PPCGenDAGISel.inc -gen-dag-isel)
+llvm_tablegen(PPCGenCallingConv.inc -gen-callingconv)
+llvm_tablegen(PPCGenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(PowerPCCommonTableGen)
add_llvm_target(PowerPCCodeGen
diff --git a/lib/Target/Sparc/CMakeLists.txt b/lib/Target/Sparc/CMakeLists.txt
index 0491229..5b87849 100644
--- a/lib/Target/Sparc/CMakeLists.txt
+++ b/lib/Target/Sparc/CMakeLists.txt
@@ -1,11 +1,11 @@
set(LLVM_TARGET_DEFINITIONS Sparc.td)
-tablegen(SparcGenRegisterInfo.inc -gen-register-info)
-tablegen(SparcGenInstrInfo.inc -gen-instr-info)
-tablegen(SparcGenAsmWriter.inc -gen-asm-writer)
-tablegen(SparcGenDAGISel.inc -gen-dag-isel)
-tablegen(SparcGenSubtargetInfo.inc -gen-subtarget)
-tablegen(SparcGenCallingConv.inc -gen-callingconv)
+llvm_tablegen(SparcGenRegisterInfo.inc -gen-register-info)
+llvm_tablegen(SparcGenInstrInfo.inc -gen-instr-info)
+llvm_tablegen(SparcGenAsmWriter.inc -gen-asm-writer)
+llvm_tablegen(SparcGenDAGISel.inc -gen-dag-isel)
+llvm_tablegen(SparcGenSubtargetInfo.inc -gen-subtarget)
+llvm_tablegen(SparcGenCallingConv.inc -gen-callingconv)
add_public_tablegen_target(SparcCommonTableGen)
add_llvm_target(SparcCodeGen
diff --git a/lib/Target/SystemZ/CMakeLists.txt b/lib/Target/SystemZ/CMakeLists.txt
index 41b4c78..7c09c0e 100644
--- a/lib/Target/SystemZ/CMakeLists.txt
+++ b/lib/Target/SystemZ/CMakeLists.txt
@@ -1,11 +1,11 @@
set(LLVM_TARGET_DEFINITIONS SystemZ.td)
-tablegen(SystemZGenRegisterInfo.inc -gen-register-info)
-tablegen(SystemZGenInstrInfo.inc -gen-instr-info)
-tablegen(SystemZGenAsmWriter.inc -gen-asm-writer)
-tablegen(SystemZGenDAGISel.inc -gen-dag-isel)
-tablegen(SystemZGenCallingConv.inc -gen-callingconv)
-tablegen(SystemZGenSubtargetInfo.inc -gen-subtarget)
+llvm_tablegen(SystemZGenRegisterInfo.inc -gen-register-info)
+llvm_tablegen(SystemZGenInstrInfo.inc -gen-instr-info)
+llvm_tablegen(SystemZGenAsmWriter.inc -gen-asm-writer)
+llvm_tablegen(SystemZGenDAGISel.inc -gen-dag-isel)
+llvm_tablegen(SystemZGenCallingConv.inc -gen-callingconv)
+llvm_tablegen(SystemZGenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(SystemZCommonTableGen)
add_llvm_target(SystemZCodeGen
diff --git a/lib/Target/X86/CMakeLists.txt b/lib/Target/X86/CMakeLists.txt
index f71c1ef..351e767 100644
--- a/lib/Target/X86/CMakeLists.txt
+++ b/lib/Target/X86/CMakeLists.txt
@@ -1,16 +1,16 @@
set(LLVM_TARGET_DEFINITIONS X86.td)
-tablegen(X86GenRegisterInfo.inc -gen-register-info)
-tablegen(X86GenDisassemblerTables.inc -gen-disassembler)
-tablegen(X86GenInstrInfo.inc -gen-instr-info)
-tablegen(X86GenAsmWriter.inc -gen-asm-writer)
-tablegen(X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
-tablegen(X86GenAsmMatcher.inc -gen-asm-matcher)
-tablegen(X86GenDAGISel.inc -gen-dag-isel)
-tablegen(X86GenFastISel.inc -gen-fast-isel)
-tablegen(X86GenCallingConv.inc -gen-callingconv)
-tablegen(X86GenSubtargetInfo.inc -gen-subtarget)
-tablegen(X86GenEDInfo.inc -gen-enhanced-disassembly-info)
+llvm_tablegen(X86GenRegisterInfo.inc -gen-register-info)
+llvm_tablegen(X86GenDisassemblerTables.inc -gen-disassembler)
+llvm_tablegen(X86GenInstrInfo.inc -gen-instr-info)
+llvm_tablegen(X86GenAsmWriter.inc -gen-asm-writer)
+llvm_tablegen(X86GenAsmWriter1.inc -gen-asm-writer -asmwriternum=1)
+llvm_tablegen(X86GenAsmMatcher.inc -gen-asm-matcher)
+llvm_tablegen(X86GenDAGISel.inc -gen-dag-isel)
+llvm_tablegen(X86GenFastISel.inc -gen-fast-isel)
+llvm_tablegen(X86GenCallingConv.inc -gen-callingconv)
+llvm_tablegen(X86GenSubtargetInfo.inc -gen-subtarget)
+llvm_tablegen(X86GenEDInfo.inc -gen-enhanced-disassembly-info)
add_public_tablegen_target(X86CommonTableGen)
set(sources
diff --git a/lib/Target/XCore/CMakeLists.txt b/lib/Target/XCore/CMakeLists.txt
index dce6e32..3dc51e1 100644
--- a/lib/Target/XCore/CMakeLists.txt
+++ b/lib/Target/XCore/CMakeLists.txt
@@ -1,11 +1,11 @@
set(LLVM_TARGET_DEFINITIONS XCore.td)
-tablegen(XCoreGenRegisterInfo.inc -gen-register-info)
-tablegen(XCoreGenInstrInfo.inc -gen-instr-info)
-tablegen(XCoreGenAsmWriter.inc -gen-asm-writer)
-tablegen(XCoreGenDAGISel.inc -gen-dag-isel)
-tablegen(XCoreGenCallingConv.inc -gen-callingconv)
-tablegen(XCoreGenSubtargetInfo.inc -gen-subtarget)
+llvm_tablegen(XCoreGenRegisterInfo.inc -gen-register-info)
+llvm_tablegen(XCoreGenInstrInfo.inc -gen-instr-info)
+llvm_tablegen(XCoreGenAsmWriter.inc -gen-asm-writer)
+llvm_tablegen(XCoreGenDAGISel.inc -gen-dag-isel)
+llvm_tablegen(XCoreGenCallingConv.inc -gen-callingconv)
+llvm_tablegen(XCoreGenSubtargetInfo.inc -gen-subtarget)
add_public_tablegen_target(XCoreCommonTableGen)
add_llvm_target(XCoreCodeGen
diff --git a/lib/VMCore/Makefile b/lib/VMCore/Makefile
index 03a4fc7..2b9b0f2 100644
--- a/lib/VMCore/Makefile
+++ b/lib/VMCore/Makefile
@@ -20,9 +20,9 @@
INTRINSICTD := $(PROJ_SRC_ROOT)/include/llvm/Intrinsics.td
INTRINSICTDS := $(wildcard $(PROJ_SRC_ROOT)/include/llvm/Intrinsics*.td)
-$(ObjDir)/Intrinsics.gen.tmp: $(ObjDir)/.dir $(INTRINSICTDS) $(TBLGEN)
+$(ObjDir)/Intrinsics.gen.tmp: $(ObjDir)/.dir $(INTRINSICTDS) $(LLVM_TBLGEN)
$(Echo) Building Intrinsics.gen.tmp from Intrinsics.td
- $(Verb) $(TableGen) $(call SYSPATH, $(INTRINSICTD)) -o $(call SYSPATH, $@) -gen-intrinsic
+ $(Verb) $(LLVMTableGen) $(call SYSPATH, $(INTRINSICTD)) -o $(call SYSPATH, $@) -gen-intrinsic
$(GENFILE): $(ObjDir)/Intrinsics.gen.tmp
$(Verb) $(CMP) -s $@ $< || ( $(CP) $< $@ && \
diff --git a/utils/TableGen/CMakeLists.txt b/utils/TableGen/CMakeLists.txt
index 9e9a3a1..a845ed2 100644
--- a/utils/TableGen/CMakeLists.txt
+++ b/utils/TableGen/CMakeLists.txt
@@ -1,9 +1,7 @@
set(LLVM_REQUIRES_EH 1)
set(LLVM_REQUIRES_RTTI 1)
-set(CMAKE_RUNTIME_OUTPUT_DIRECTORY ${LLVM_TOOLS_BINARY_DIR})
-
-add_llvm_utility(tblgen
+add_tablegen(llvm-tblgen LLVM
ARMDecoderEmitter.cpp
AsmMatcherEmitter.cpp
AsmWriterEmitter.cpp
@@ -42,15 +40,3 @@
X86DisassemblerTables.cpp
X86RecognizableInstr.cpp
)
-target_link_libraries(tblgen LLVMSupport LLVMTableGen)
-if( MINGW )
- target_link_libraries(tblgen imagehlp psapi)
- if(CMAKE_SIZEOF_VOID_P MATCHES "8")
- set_target_properties(tblgen PROPERTIES LINK_FLAGS -Wl,--stack,16777216)
- endif(CMAKE_SIZEOF_VOID_P MATCHES "8")
-endif( MINGW )
-if( LLVM_ENABLE_THREADS AND HAVE_LIBPTHREAD AND NOT BEOS )
- target_link_libraries(tblgen pthread)
-endif()
-
-install(TARGETS tblgen RUNTIME DESTINATION bin)
diff --git a/utils/TableGen/Makefile b/utils/TableGen/Makefile
index 17e94ea..0c4619d 100644
--- a/utils/TableGen/Makefile
+++ b/utils/TableGen/Makefile
@@ -8,7 +8,7 @@
##===----------------------------------------------------------------------===##
LEVEL = ../..
-TOOLNAME = tblgen
+TOOLNAME = llvm-tblgen
USEDLIBS = LLVMTableGen.a LLVMSupport.a
REQUIRES_EH := 1
REQUIRES_RTTI := 1