Convert tabs to spaces
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21439 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp
index 6790b3f..2189470 100644
--- a/lib/CodeGen/PHIElimination.cpp
+++ b/lib/CodeGen/PHIElimination.cpp
@@ -32,7 +32,7 @@
// Eliminate PHI instructions by inserting copies into predecessor blocks.
//
for (MachineFunction::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
- Changed |= EliminatePHINodes(Fn, *I);
+ Changed |= EliminatePHINodes(Fn, *I);
//std::cerr << "AFTER PHI NODE ELIM:\n";
//Fn.dump();
@@ -52,7 +52,7 @@
};
RegisterPass<PNE> X("phi-node-elimination",
- "Eliminate PHI nodes for register allocation");
+ "Eliminate PHI nodes for register allocation");
}
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 0ddf7c2..b27f1b7 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -91,7 +91,7 @@
/// getStackSpaceFor - This allocates space for the specified virtual
/// register to be held on the stack.
int RegAllocSimple::getStackSpaceFor(unsigned VirtReg,
- const TargetRegisterClass *RC) {
+ const TargetRegisterClass *RC) {
// Find the location VirtReg would belong...
std::map<unsigned, int>::iterator I =
StackSlotForVirtReg.lower_bound(VirtReg);
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 5b0c710..2eccb6b 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -981,7 +981,7 @@
case ISD::OR:
if (!C2)return N1; // X or 0 -> X
if (N2C->isAllOnesValue())
- return N2; // X or -1 -> -1
+ return N2; // X or -1 -> -1
break;
case ISD::XOR:
if (!C2) return N1; // X xor 0 -> X
@@ -1005,7 +1005,7 @@
return getNode(ISD::AND, VT, LHS, RHS);
}
}
- // X xor -1 -> not(x) ?
+ // X xor -1 -> not(x) ?
}
break;
}
@@ -1647,13 +1647,11 @@
dyn_cast<GlobalAddressSDNode>(this)) {
std::cerr << "<";
WriteAsOperand(std::cerr, GADN->getGlobal()) << ">";
- } else if (const FrameIndexSDNode *FIDN =
- dyn_cast<FrameIndexSDNode>(this)) {
+ } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(this)) {
std::cerr << "<" << FIDN->getIndex() << ">";
} else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(this)){
std::cerr << "<" << CP->getIndex() << ">";
- } else if (const BasicBlockSDNode *BBDN =
- dyn_cast<BasicBlockSDNode>(this)) {
+ } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(this)) {
std::cerr << "<";
const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock();
if (LBB)
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 62376e5..1697ad3 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -418,7 +418,7 @@
// If this is not a fall-through branch, emit the branch.
if (Succ0MBB != NextBlock)
DAG.setRoot(DAG.getNode(ISD::BR, MVT::Other, getRoot(),
- DAG.getBasicBlock(Succ0MBB)));
+ DAG.getBasicBlock(Succ0MBB)));
} else {
MachineBasicBlock *Succ1MBB = FuncInfo.MBBMap[I.getSuccessor(1)];
@@ -427,14 +427,14 @@
// If the condition is false, fall through. This means we should branch
// if the condition is true to Succ #0.
DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
- Cond, DAG.getBasicBlock(Succ0MBB)));
+ Cond, DAG.getBasicBlock(Succ0MBB)));
} else if (Succ0MBB == NextBlock) {
// If the condition is true, fall through. This means we should branch if
// the condition is false to Succ #1. Invert the condition first.
SDOperand True = DAG.getConstant(1, Cond.getValueType());
Cond = DAG.getNode(ISD::XOR, Cond.getValueType(), Cond, True);
DAG.setRoot(DAG.getNode(ISD::BRCOND, MVT::Other, getRoot(),
- Cond, DAG.getBasicBlock(Succ1MBB)));
+ Cond, DAG.getBasicBlock(Succ1MBB)));
} else {
std::vector<SDOperand> Ops;
Ops.push_back(getRoot());
@@ -537,7 +537,7 @@
// N = N + Offset
uint64_t Offset = TD.getStructLayout(StTy)->MemberOffsets[Field];
N = DAG.getNode(ISD::ADD, N.getValueType(), N,
- getIntPtrConstant(Offset));
+ getIntPtrConstant(Offset));
}
Ty = StTy->getElementType(Field);
} else {
@@ -558,7 +558,6 @@
IdxN = DAG.getNode(ISD::TRUNCATE, Scale.getValueType(), IdxN);
IdxN = DAG.getNode(ISD::MUL, N.getValueType(), IdxN, Scale);
-
N = DAG.getNode(ISD::ADD, N.getValueType(), N, IdxN);
}
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index e3304f4..2ed1fe4 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
@@ -73,13 +73,11 @@
} else if (const GlobalAddressSDNode *GADN =
dyn_cast<GlobalAddressSDNode>(Node)) {
Op += ": " + GADN->getGlobal()->getName();
- } else if (const FrameIndexSDNode *FIDN =
- dyn_cast<FrameIndexSDNode>(Node)) {
+ } else if (const FrameIndexSDNode *FIDN = dyn_cast<FrameIndexSDNode>(Node)) {
Op += " " + itostr(FIDN->getIndex());
} else if (const ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(Node)){
Op += "<" + utostr(CP->getIndex()) + ">";
- } else if (const BasicBlockSDNode *BBDN =
- dyn_cast<BasicBlockSDNode>(Node)) {
+ } else if (const BasicBlockSDNode *BBDN = dyn_cast<BasicBlockSDNode>(Node)) {
Op = "BB: ";
const Value *LBB = (const Value*)BBDN->getBasicBlock()->getBasicBlock();
if (LBB)