commit def390a30aa8c3eb94796a062b161762330fdbe4
author Rafael Espindola <rafael.espindola@gmail.com> Mon Aug 03 02:45:34 2009 +0000
committer Rafael Espindola <rafael.espindola@gmail.com> Mon Aug 03 02:45:34 2009 +0000
tree 3ef19bacf36cf203f7f78a4aeb024397ce332194
parent a8e8984ee4c197634839cf228f5b1d79a77fa4b9

Use movq to move 64 bits in and out of mmx registers.
Fixes PR4669



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77940 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/X86/X86ISelLowering.cpp

diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 59d3ab5..4db0e02 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -4447,6 +4447,11 @@
                                    DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32,
                                                Op.getOperand(0))));
 
+  if (Op.getValueType() == MVT::v1i64 && Op.getOperand(0).getValueType() == MVT::i64)
+    return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v1i64,
+                       DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64,
+                                   Op.getOperand(0)));
+
   SDValue AnyExt = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i32, Op.getOperand(0));
   MVT VT = MVT::v2i32;
   switch (Op.getValueType().getSimpleVT()) {