| commit | df1c3b8398d1df253ebd389ac1068ec732a2f28f | [log] [tgz] |
|---|---|---|
| author | Vikram S. Adve <vadve@cs.uiuc.edu> | Mon Nov 05 03:56:02 2001 +0000 |
| committer | Vikram S. Adve <vadve@cs.uiuc.edu> | Mon Nov 05 03:56:02 2001 +0000 |
| tree | 08f1c0ee9c0a8ab550605835168005ba01ffa2d4 | |
| parent | 0b12f2bb30757b92175b81d6099fe98f7579f2a8 [diff] [blame] |
Make reg. numbers signed ints. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@1137 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp index b4f275d..b620fa4 100644 --- a/lib/CodeGen/MachineInstr.cpp +++ b/lib/CodeGen/MachineInstr.cpp
@@ -66,7 +66,7 @@ void MachineInstr::SetMachineOperand(unsigned int i, - unsigned int regNum, bool isdef=false) + int regNum, bool isdef=false) { assert(i < operands.size()); operands[i].InitializeReg(regNum);