diff --git a/lib/Target/AArch64/AArch64.td b/lib/Target/AArch64/AArch64.td
index 750fec7..0e4f5fb 100644
--- a/lib/Target/AArch64/AArch64.td
+++ b/lib/Target/AArch64/AArch64.td
@@ -1,4 +1,4 @@
-//===- AArch64.td - Describe the AArch64 Target Machine ---------*- tblgen -*-==//
+//===- AArch64.td - Describe the AArch64 Target Machine -------*- tblgen -*-==//
 //
 //                     The LLVM Compiler Infrastructure
 //
diff --git a/lib/Target/AArch64/AArch64AsmPrinter.cpp b/lib/Target/AArch64/AArch64AsmPrinter.cpp
index 63cc88f..61839b6 100644
--- a/lib/Target/AArch64/AArch64AsmPrinter.cpp
+++ b/lib/Target/AArch64/AArch64AsmPrinter.cpp
@@ -34,7 +34,8 @@
   // expected to be created.
   assert(MI->getNumOperands() == 4 && MI->getOperand(0).isReg()
          && MI->getOperand(1).isImm() && "unexpected custom DBG_VALUE");
-  return MachineLocation(MI->getOperand(0).getReg(), MI->getOperand(1).getImm());
+  return MachineLocation(MI->getOperand(0).getReg(),
+                         MI->getOperand(1).getImm());
 }
 
 /// Try to print a floating-point register as if it belonged to a specified
@@ -90,7 +91,8 @@
   StringRef Name;
   StringRef Modifier;
   switch (MO.getType()) {
-  default: llvm_unreachable("Unexpected operand for symbolic address constraint");
+  default:
+    llvm_unreachable("Unexpected operand for symbolic address constraint");
   case MachineOperand::MO_GlobalAddress:
     Name = Mang->getSymbol(MO.getGlobal())->getName();
 
diff --git a/lib/Target/AArch64/AArch64ConstantIslandPass.cpp b/lib/Target/AArch64/AArch64ConstantIslandPass.cpp
index f5e5c64..ab482bd 100644
--- a/lib/Target/AArch64/AArch64ConstantIslandPass.cpp
+++ b/lib/Target/AArch64/AArch64ConstantIslandPass.cpp
@@ -46,7 +46,8 @@
 // FIXME: This option should be removed once it has received sufficient testing.
 static cl::opt<bool>
 AlignConstantIslands("aarch64-align-constant-islands", cl::Hidden,
-                     cl::init(true), cl::desc("Align constant islands in code"));
+                     cl::init(true),
+                     cl::desc("Align constant islands in code"));
 
 /// Return the worst case padding that could result from unknown offset bits.
 /// This does not include alignment padding caused by known offset bits.
@@ -828,7 +829,8 @@
 bool AArch64ConstantIslands::isCPEntryInRange(MachineInstr *MI,
                                               unsigned UserOffset,
                                               MachineInstr *CPEMI,
-                                              unsigned OffsetBits, bool DoDump) {
+                                              unsigned OffsetBits,
+                                              bool DoDump) {
   unsigned CPEOffset  = getOffsetOf(CPEMI);
 
   if (DoDump) {
@@ -930,7 +932,8 @@
     // Removing CPEs can leave empty entries, skip
     if (CPEs[i].CPEMI == NULL)
       continue;
-    if (isCPEntryInRange(UserMI, UserOffset, CPEs[i].CPEMI, U.getOffsetBits())) {
+    if (isCPEntryInRange(UserMI, UserOffset, CPEs[i].CPEMI,
+                         U.getOffsetBits())) {
       DEBUG(dbgs() << "Replacing CPE#" << CPI << " with CPE#"
                    << CPEs[i].CPI << "\n");
       // Point the CPUser node to the replacement
diff --git a/lib/Target/AArch64/AArch64FrameLowering.cpp b/lib/Target/AArch64/AArch64FrameLowering.cpp
index 2301114..24d1576 100644
--- a/lib/Target/AArch64/AArch64FrameLowering.cpp
+++ b/lib/Target/AArch64/AArch64FrameLowering.cpp
@@ -180,7 +180,8 @@
 
     for (std::vector<CalleeSavedInfo>::const_iterator I = CSI.begin(),
            E = CSI.end(); I != E; ++I) {
-      MachineLocation Dst(MachineLocation::VirtualFP, MFI->getObjectOffset(I->getFrameIdx()));
+      MachineLocation Dst(MachineLocation::VirtualFP,
+                          MFI->getObjectOffset(I->getFrameIdx()));
       MachineLocation Src(I->getReg());
       Moves.push_back(MachineMove(CSLabel, Dst, Src));
     }
@@ -537,7 +538,8 @@
         State = RegState::Define;
       }
 
-      NewMI = BuildMI(MBB, MBBI, DL, TII.get(PossClasses[ClassIdx].SingleOpcode))
+      NewMI = BuildMI(MBB, MBBI, DL,
+                      TII.get(PossClasses[ClassIdx].SingleOpcode))
                 .addReg(CSI[i].getReg(), State);
     }
 
@@ -549,9 +551,9 @@
     Flags = isPrologue ? MachineMemOperand::MOStore : MachineMemOperand::MOLoad;
     MachineMemOperand *MMO =
       MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(FrameIdx),
-                              Flags,
-                              Pair ? TheClass.getSize() * 2 : TheClass.getSize(),
-                              MFI.getObjectAlignment(FrameIdx));
+                             Flags,
+                             Pair ? TheClass.getSize() * 2 : TheClass.getSize(),
+                             MFI.getObjectAlignment(FrameIdx));
 
     NewMI.addFrameIndex(FrameIdx)
       .addImm(0)                  // address-register offset
diff --git a/lib/Target/AArch64/AArch64FrameLowering.h b/lib/Target/AArch64/AArch64FrameLowering.h
index dfa66ec..a14c2bb 100644
--- a/lib/Target/AArch64/AArch64FrameLowering.h
+++ b/lib/Target/AArch64/AArch64FrameLowering.h
@@ -29,7 +29,7 @@
   struct LoadStoreMethod {
     const TargetRegisterClass *RegClass; // E.g. GPR64RegClass
 
-    // The preferred instruction. 
+    // The preferred instruction.
     unsigned PairOpcode; // E.g. LSPair64_STR
 
     // Sometimes only a single register can be handled at once.
diff --git a/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index 28f152c..c933555 100644
--- a/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -72,7 +72,8 @@
 
   bool SelectFPZeroOperand(SDValue N, SDValue &Dummy);
 
-  bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos, unsigned RegWidth);
+  bool SelectCVTFixedPosOperand(SDValue N, SDValue &FixedPos,
+                                unsigned RegWidth);
 
   bool SelectInlineAsmMemoryOperand(const SDValue &Op,
                                     char ConstraintCode,
@@ -130,8 +131,8 @@
 
 bool
 AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
-                                                  char ConstraintCode,
-                                                  std::vector<SDValue> &OutOps) {
+                                                 char ConstraintCode,
+                                                 std::vector<SDValue> &OutOps) {
   switch (ConstraintCode) {
   default: llvm_unreachable("Unrecognised AArch64 memory constraint");
   case 'm':
@@ -152,7 +153,7 @@
   ConstantFPSDNode *Imm = dyn_cast<ConstantFPSDNode>(N);
   if (!Imm || !Imm->getValueAPF().isPosZero())
     return false;
-  
+
   // Doesn't actually carry any information, but keeps TableGen quiet.
   Dummy = CurDAG->getTargetConstant(0, MVT::i32);
   return true;
diff --git a/lib/Target/AArch64/AArch64ISelLowering.cpp b/lib/Target/AArch64/AArch64ISelLowering.cpp
index 9b26b1f..2158b05 100644
--- a/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -841,7 +841,8 @@
                                            DebugLoc DL, SDValue &Chain) const {
   MachineFunction &MF = DAG.getMachineFunction();
   MachineFrameInfo *MFI = MF.getFrameInfo();
-  AArch64MachineFunctionInfo *FuncInfo = MF.getInfo<AArch64MachineFunctionInfo>();
+  AArch64MachineFunctionInfo *FuncInfo
+    = MF.getInfo<AArch64MachineFunctionInfo>();
 
   SmallVector<SDValue, 8> MemOps;
 
@@ -1045,10 +1046,11 @@
   SDValue Flag;
 
   for (unsigned i = 0, e = RVLocs.size(); i != e; ++i) {
-    // PCS: "If the type, T, of the result of a function is such that void func(T
-    // arg) would require that arg be passed as a value in a register (or set of
-    // registers) according to the rules in 5.4, then the result is returned in
-    // the same registers as would be used for such an argument.
+    // PCS: "If the type, T, of the result of a function is such that
+    // void func(T arg) would require that arg be passed as a value in a
+    // register (or set of registers) according to the rules in 5.4, then the
+    // result is returned in the same registers as would be used for such an
+    // argument.
     //
     // Otherwise, the caller shall reserve a block of memory of sufficient
     // size and alignment to hold the result. The address of the memory block
@@ -1166,7 +1168,8 @@
   if (!IsSibCall)
     Chain = DAG.getCALLSEQ_START(Chain, DAG.getIntPtrConstant(NumBytes, true));
 
-  SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, AArch64::XSP, getPointerTy());
+  SDValue StackPtr = DAG.getCopyFromReg(Chain, dl, AArch64::XSP,
+                                        getPointerTy());
 
   SmallVector<SDValue, 8> MemOpChains;
   SmallVector<std::pair<unsigned, SDValue>, 8> RegsToPass;
@@ -1874,9 +1877,10 @@
 
   if (Alignment == 0) {
     const PointerType *GVPtrTy = cast<PointerType>(GV->getType());
-    if (GVPtrTy->getElementType()->isSized())
-      Alignment = getDataLayout()->getABITypeAlignment(GVPtrTy->getElementType());
-    else {
+    if (GVPtrTy->getElementType()->isSized()) {
+      Alignment
+        = getDataLayout()->getABITypeAlignment(GVPtrTy->getElementType());
+    } else {
       // Be conservative if we can't guess, not that it really matters:
       // functions and labels aren't valid for loads, and the methods used to
       // actually calculate an address work with any alignment.
@@ -1954,7 +1958,8 @@
   Ops.push_back(Glue);
 
   SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
-  Chain = DAG.getNode(AArch64ISD::TLSDESCCALL, DL, NodeTys, &Ops[0], Ops.size());
+  Chain = DAG.getNode(AArch64ISD::TLSDESCCALL, DL, NodeTys, &Ops[0],
+                      Ops.size());
   Glue = Chain.getValue(1);
 
   // After the call, the offset from TPIDR_EL0 is in X0, copy it out and pass it
@@ -1995,7 +2000,8 @@
 
     TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar,
                                        DAG.getTargetConstant(0, MVT::i32)), 0);
-    TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT, TPOff, LoVar,
+    TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT,
+                                       TPOff, LoVar,
                                        DAG.getTargetConstant(0, MVT::i32)), 0);
   } else if (Model == TLSModel::GeneralDynamic) {
     // Accesses used in this sequence go via the TLS descriptor which lives in
@@ -2005,7 +2011,8 @@
     SDValue LoDesc = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
                                                 AArch64II::MO_TLSDESC_LO12);
     SDValue DescAddr = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
-                                   HiDesc, LoDesc, DAG.getConstant(8, MVT::i32));
+                                   HiDesc, LoDesc,
+                                   DAG.getConstant(8, MVT::i32));
     SDValue SymAddr = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0);
 
     TPOff = LowerTLSDescCall(SymAddr, DescAddr, DL, DAG);
@@ -2027,7 +2034,8 @@
     SDValue LoDesc = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT,
                                                 AArch64II::MO_TLSDESC_LO12);
     SDValue DescAddr = DAG.getNode(AArch64ISD::WrapperSmall, DL, PtrVT,
-                                   HiDesc, LoDesc, DAG.getConstant(8, MVT::i32));
+                                   HiDesc, LoDesc,
+                                   DAG.getConstant(8, MVT::i32));
     SDValue SymAddr = DAG.getTargetExternalSymbol("_TLS_MODULE_BASE_", PtrVT);
 
     ThreadBase = LowerTLSDescCall(SymAddr, DescAddr, DL, DAG);
@@ -2040,7 +2048,8 @@
 
     TPOff = SDValue(DAG.getMachineNode(AArch64::MOVZxii, DL, PtrVT, HiVar,
                                        DAG.getTargetConstant(0, MVT::i32)), 0);
-    TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT, TPOff, LoVar,
+    TPOff = SDValue(DAG.getMachineNode(AArch64::MOVKxii, DL, PtrVT,
+                                       TPOff, LoVar,
                                        DAG.getTargetConstant(0, MVT::i32)), 0);
   } else
       llvm_unreachable("Unsupported TLS access model");
@@ -2123,7 +2132,8 @@
   SDValue A64cc = DAG.getConstant(CondCode, MVT::i32);
   SDValue SetCC = DAG.getNode(AArch64ISD::SETCC, dl, MVT::i32, LHS, RHS,
                               DAG.getCondCode(CC));
-  SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl, Op.getValueType(),
+  SDValue A64SELECT_CC = DAG.getNode(AArch64ISD::SELECT_CC, dl,
+                                     Op.getValueType(),
                                      SetCC, IfTrue, IfFalse, A64cc);
 
   if (Alternative != A64CC::Invalid) {
@@ -2231,7 +2241,8 @@
   // The layout of the va_list struct is specified in the AArch64 Procedure Call
   // Standard, section B.3.
   MachineFunction &MF = DAG.getMachineFunction();
-  AArch64MachineFunctionInfo *FuncInfo = MF.getInfo<AArch64MachineFunctionInfo>();
+  AArch64MachineFunctionInfo *FuncInfo
+    = MF.getInfo<AArch64MachineFunctionInfo>();
   DebugLoc DL = Op.getDebugLoc();
 
   SDValue Chain = Op.getOperand(0);
@@ -2365,7 +2376,7 @@
 }
 
 static SDValue PerformATOMIC_FENCECombine(SDNode *FenceNode,
-                                          TargetLowering::DAGCombinerInfo &DCI) {
+                                         TargetLowering::DAGCombinerInfo &DCI) {
   // An atomic operation followed by an acquiring atomic fence can be reduced to
   // an acquiring load. The atomic operation provides a convenient pointer to
   // load from. If the original operation was a load anyway we can actually
@@ -2407,7 +2418,7 @@
 }
 
 static SDValue PerformATOMIC_STORECombine(SDNode *N,
-                                          TargetLowering::DAGCombinerInfo &DCI) {
+                                         TargetLowering::DAGCombinerInfo &DCI) {
   // A releasing atomic fence followed by an atomic store can be combined into a
   // single store operation.
   SelectionDAG &DAG = DCI.DAG;
@@ -2821,7 +2832,8 @@
   }
 
   // FIXME: Ump, Utf, Usa, Ush
-  // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes, whatever they may be
+  // Ump: A memory address suitable for ldp/stp in SI, DI, SF and DF modes,
+  //      whatever they may be
   // Utf: A memory address suitable for ldp/stp in TF mode, whatever it may be
   // Usa: An absolute symbolic address
   // Ush: The high part (bits 32:12) of a pc-relative symbolic address
@@ -2893,7 +2905,8 @@
     if (const GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(Op)) {
       Result = DAG.getTargetGlobalAddress(GA->getGlobal(), Op.getDebugLoc(),
                                           GA->getValueType(0));
-    } else if (const BlockAddressSDNode *BA = dyn_cast<BlockAddressSDNode>(Op)) {
+    } else if (const BlockAddressSDNode *BA
+                 = dyn_cast<BlockAddressSDNode>(Op)) {
       Result = DAG.getTargetBlockAddress(BA->getBlockAddress(),
                                          BA->getValueType(0));
     } else if (const ExternalSymbolSDNode *ES
@@ -2924,8 +2937,9 @@
 }
 
 std::pair<unsigned, const TargetRegisterClass*>
-AArch64TargetLowering::getRegForInlineAsmConstraint(const std::string &Constraint,
-                                                    EVT VT) const {
+AArch64TargetLowering::getRegForInlineAsmConstraint(
+                                                  const std::string &Constraint,
+                                                  EVT VT) const {
   if (Constraint.size() == 1) {
     switch (Constraint[0]) {
     case 'r':
diff --git a/lib/Target/AArch64/AArch64ISelLowering.h b/lib/Target/AArch64/AArch64ISelLowering.h
index ec4e432..4960d28 100644
--- a/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/lib/Target/AArch64/AArch64ISelLowering.h
@@ -161,8 +161,8 @@
                                     SelectionDAG& DAG) const;
 
   /// Finds the incoming stack arguments which overlap the given fixed stack
-  /// object and incorporates their load into the current chain. This prevents an
-  /// upcoming store from clobbering the stack argument before it's used.
+  /// object and incorporates their load into the current chain. This prevents
+  /// an upcoming store from clobbering the stack argument before it's used.
   SDValue addTokenForArgument(SDValue Chain, SelectionDAG &DAG,
                               MachineFrameInfo *MFI, int ClobberedFI) const;
 
diff --git a/lib/Target/AArch64/AArch64InstrFormats.td b/lib/Target/AArch64/AArch64InstrFormats.td
index ce66396..c6aa265 100644
--- a/lib/Target/AArch64/AArch64InstrFormats.td
+++ b/lib/Target/AArch64/AArch64InstrFormats.td
@@ -16,8 +16,7 @@
 // architecture.
 class A64Inst<dag outs, dag ins, string asmstr, list<dag> patterns,
               InstrItinClass itin>
-    : Instruction
-{
+    : Instruction {
   // All A64 instructions are 32-bit. This field will be filled in
   // graually going down the hierarchy.
   field bits<32> Inst;
@@ -40,8 +39,7 @@
   let Itinerary = itin;
 }
 
-class PseudoInst<dag outs, dag ins, list<dag> patterns> : Instruction
-{
+class PseudoInst<dag outs, dag ins, list<dag> patterns> : Instruction {
   let Namespace = "AArch64";
 
   let OutOperandList = outs;
@@ -54,8 +52,7 @@
 // Represents a pseudo-instruction that represents a single A64 instruction for
 // whatever reason, the eventual result will be a 32-bit real instruction.
 class A64PseudoInst<dag outs, dag ins, list<dag> patterns>
-  : PseudoInst<outs, ins, patterns>
-{
+  : PseudoInst<outs, ins, patterns> {
   let Size = 4;
 }
 
@@ -70,8 +67,7 @@
 
 class A64InstRd<dag outs, dag ins, string asmstr,
                 list<dag> patterns, InstrItinClass itin>
-  : A64Inst<outs, ins, asmstr, patterns, itin>
-{
+  : A64Inst<outs, ins, asmstr, patterns, itin> {
   bits<5> Rd;
 
   let Inst{4-0} = Rd;
@@ -79,8 +75,7 @@
 
 class A64InstRt<dag outs, dag ins, string asmstr,
                 list<dag> patterns, InstrItinClass itin>
-  : A64Inst<outs, ins, asmstr, patterns, itin>
-{
+  : A64Inst<outs, ins, asmstr, patterns, itin> {
   bits<5> Rt;
 
   let Inst{4-0} = Rt;
@@ -89,8 +84,7 @@
 
 class A64InstRdn<dag outs, dag ins, string asmstr,
                  list<dag> patterns, InstrItinClass itin>
-    : A64InstRd<outs, ins, asmstr, patterns, itin>
-{
+    : A64InstRd<outs, ins, asmstr, patterns, itin> {
   // Inherit rdt
   bits<5> Rn;
 
@@ -99,8 +93,7 @@
 
 class A64InstRtn<dag outs, dag ins, string asmstr,
                 list<dag> patterns, InstrItinClass itin>
-    : A64InstRt<outs, ins, asmstr, patterns, itin>
-{
+    : A64InstRt<outs, ins, asmstr, patterns, itin> {
   // Inherit rdt
   bits<5> Rn;
 
@@ -110,8 +103,7 @@
 // Instructions taking Rt,Rt2,Rn
 class A64InstRtt2n<dag outs, dag ins, string asmstr,
                    list<dag> patterns, InstrItinClass itin>
-  : A64InstRtn<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRtn<outs, ins, asmstr, patterns, itin> {
   bits<5> Rt2;
 
   let Inst{14-10} = Rt2;
@@ -119,8 +111,7 @@
 
 class A64InstRdnm<dag outs, dag ins, string asmstr,
                   list<dag> patterns, InstrItinClass itin>
-  : A64InstRdn<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRdn<outs, ins, asmstr, patterns, itin> {
   bits<5> Rm;
 
   let Inst{20-16} = Rm;
@@ -135,8 +126,7 @@
 class A64I_addsubext<bit sf, bit op, bit S, bits<2> opt, bits<3> option,
                      dag outs, dag ins, string asmstr, list<dag> patterns,
                      InstrItinClass itin>
-    : A64InstRdnm<outs, ins, asmstr, patterns, itin>
-{
+    : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
     bits<3> Imm3;
 
     let Inst{31} = sf;
@@ -156,8 +146,7 @@
 class A64I_addsubimm<bit sf, bit op, bit S, bits<2> shift,
                      dag outs, dag ins, string asmstr,
                      list<dag> patterns, InstrItinClass itin>
-  : A64InstRdn<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRdn<outs, ins, asmstr, patterns, itin> {
   bits<12> Imm12;
 
   let Inst{31} = sf;
@@ -172,8 +161,7 @@
 class A64I_addsubshift<bit sf, bit op, bit S, bits<2> shift,
                        dag outs, dag ins, string asmstr, list<dag> patterns,
                        InstrItinClass itin>
-    : A64InstRdnm<outs, ins, asmstr, patterns, itin>
-{
+    : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
     bits<6> Imm6;
 
     let Inst{31} = sf;
@@ -192,8 +180,7 @@
 class A64I_addsubcarry<bit sf, bit op, bit S, bits<6> opcode2,
                        dag outs, dag ins, string asmstr, list<dag> patterns,
                        InstrItinClass itin>
-    : A64InstRdnm<outs, ins, asmstr, patterns, itin>
-{
+    : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
     let Inst{31} = sf;
     let Inst{30} = op;
     let Inst{29} = S;
@@ -209,8 +196,7 @@
 class A64I_bitfield<bit sf, bits<2> opc, bit n,
                     dag outs, dag ins, string asmstr,
                     list<dag> patterns, InstrItinClass itin>
-  : A64InstRdn<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRdn<outs, ins, asmstr, patterns, itin> {
   bits<6> ImmR;
   bits<6> ImmS;
 
@@ -228,8 +214,7 @@
 class A64I_cmpbr<bit sf, bit op,
                   dag outs, dag ins, string asmstr,
                   list<dag> patterns, InstrItinClass itin>
-  : A64InstRt<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRt<outs, ins, asmstr, patterns, itin> {
   bits<19> Label;
 
   let Inst{31} = sf;
@@ -243,8 +228,7 @@
 class A64I_condbr<bit o1, bit o0,
                   dag outs, dag ins, string asmstr,
                   list<dag> patterns, InstrItinClass itin>
-  : A64Inst<outs, ins, asmstr, patterns, itin>
-{
+  : A64Inst<outs, ins, asmstr, patterns, itin> {
   bits<19> Label;
   bits<4> Cond;
 
@@ -259,8 +243,7 @@
 class A64I_condcmpimm<bit sf, bit op, bit o2, bit o3, bit s,
                       dag outs, dag ins, string asmstr,
                       list<dag> patterns, InstrItinClass itin>
-  : A64Inst<outs, ins, asmstr, patterns, itin>
-{
+  : A64Inst<outs, ins, asmstr, patterns, itin> {
   bits<5> Rn;
   bits<5> UImm5;
   bits<4> NZCVImm;
@@ -283,8 +266,7 @@
 class A64I_condcmpreg<bit sf, bit op, bit o2, bit o3, bit s,
                       dag outs, dag ins, string asmstr,
                       list<dag> patterns, InstrItinClass itin>
-  : A64Inst<outs, ins, asmstr, patterns, itin>
-{
+  : A64Inst<outs, ins, asmstr, patterns, itin> {
   bits<5> Rn;
   bits<5> Rm;
   bits<4> NZCVImm;
@@ -308,8 +290,7 @@
 class A64I_condsel<bit sf, bit op, bit s, bits<2> op2,
                    dag outs, dag ins, string asmstr,
                    list<dag> patterns, InstrItinClass itin>
-  : A64InstRdnm<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
   bits<4> Cond;
 
   let Inst{31} = sf;
@@ -327,8 +308,7 @@
 class A64I_dp_1src<bit sf, bit S, bits<5> opcode2, bits<6> opcode,
                 string asmstr, dag outs, dag ins,
                 list<dag> patterns, InstrItinClass itin>
-  : A64InstRdn<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRdn<outs, ins, asmstr, patterns, itin> {
   let Inst{31} = sf;
   let Inst{30} = 0b1;
   let Inst{29} = S;
@@ -341,8 +321,7 @@
 class A64I_dp_2src<bit sf, bits<6> opcode, bit S,
                 string asmstr, dag outs, dag ins,
                 list<dag> patterns, InstrItinClass itin>
-  : A64InstRdnm<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
   let Inst{31} = sf;
   let Inst{30} = 0b0;
   let Inst{29} = S;
@@ -355,8 +334,7 @@
 class A64I_dp3<bit sf, bits<6> opcode,
                dag outs, dag ins, string asmstr,
                list<dag> patterns, InstrItinClass itin>
-  : A64InstRdnm<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
   bits<5> Ra;
 
   let Inst{31} = sf;
@@ -374,8 +352,7 @@
 class A64I_exception<bits<3> opc, bits<3> op2, bits<2> ll,
                      dag outs, dag ins, string asmstr,
                      list<dag> patterns, InstrItinClass itin>
-  : A64Inst<outs, ins, asmstr, patterns, itin>
-{
+  : A64Inst<outs, ins, asmstr, patterns, itin> {
   bits<16> UImm16;
 
   let Inst{31-24} = 0b11010100;
@@ -389,8 +366,7 @@
 class A64I_extract<bit sf, bits<3> op, bit n,
                    dag outs, dag ins, string asmstr,
                    list<dag> patterns, InstrItinClass itin>
-  : A64InstRdnm<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
   bits<6> LSB;
 
   let Inst{31} = sf;
@@ -408,8 +384,7 @@
 class A64I_fpcmp<bit m, bit s, bits<2> type, bits<2> op, bits<5> opcode2,
                 dag outs, dag ins, string asmstr,
                 list<dag> patterns, InstrItinClass itin>
-  : A64Inst<outs, ins, asmstr, patterns, itin>
-{
+  : A64Inst<outs, ins, asmstr, patterns, itin> {
   bits<5> Rn;
   bits<5> Rm;
 
@@ -430,8 +405,7 @@
 class A64I_fpccmp<bit m, bit s, bits<2> type, bit op,
                  dag outs, dag ins, string asmstr,
                  list<dag> patterns, InstrItinClass itin>
-  : A64InstRdn<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRdn<outs, ins, asmstr, patterns, itin> {
   bits<5> Rn;
   bits<5> Rm;
   bits<4> NZCVImm;
@@ -455,8 +429,7 @@
 class A64I_fpcondsel<bit m, bit s, bits<2> type,
                      dag outs, dag ins, string asmstr,
                      list<dag> patterns, InstrItinClass itin>
-  : A64InstRdnm<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
   bits<4> Cond;
 
   let Inst{31} = m;
@@ -477,8 +450,7 @@
 class A64I_fpdp1<bit m, bit s, bits<2> type, bits<6> opcode,
                  dag outs, dag ins, string asmstr,
                  list<dag> patterns, InstrItinClass itin>
-  : A64InstRdn<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRdn<outs, ins, asmstr, patterns, itin> {
   let Inst{31} = m;
   let Inst{30} = 0b0;
   let Inst{29} = s;
@@ -495,8 +467,7 @@
 class A64I_fpdp2<bit m, bit s, bits<2> type, bits<4> opcode,
                  dag outs, dag ins, string asmstr,
                  list<dag> patterns, InstrItinClass itin>
-  : A64InstRdnm<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
   let Inst{31} = m;
   let Inst{30} = 0b0;
   let Inst{29} = s;
@@ -514,8 +485,7 @@
 class A64I_fpdp3<bit m, bit s, bits<2> type, bit o1, bit o0,
                  dag outs, dag ins, string asmstr,
                  list<dag> patterns, InstrItinClass itin>
-  : A64InstRdnm<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
   bits<5> Ra;
 
   let Inst{31} = m;
@@ -535,8 +505,7 @@
 class A64I_fpfixed<bit sf, bit s, bits<2> type, bits<2> mode, bits<3> opcode,
                  dag outs, dag ins, string asmstr,
                  list<dag> patterns, InstrItinClass itin>
-  : A64InstRdn<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRdn<outs, ins, asmstr, patterns, itin> {
   bits<6> Scale;
 
   let Inst{31} = sf;
@@ -556,8 +525,7 @@
 class A64I_fpint<bit sf, bit s, bits<2> type, bits<2> rmode, bits<3> opcode,
                  dag outs, dag ins, string asmstr,
                  list<dag> patterns, InstrItinClass itin>
-  : A64InstRdn<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRdn<outs, ins, asmstr, patterns, itin> {
   let Inst{31} = sf;
   let Inst{30} = 0b0;
   let Inst{29} = s;
@@ -576,8 +544,7 @@
 class A64I_fpimm<bit m, bit s, bits<2> type, bits<5> imm5,
                  dag outs, dag ins, string asmstr,
                  list<dag> patterns, InstrItinClass itin>
-  : A64InstRd<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRd<outs, ins, asmstr, patterns, itin> {
   bits<8> Imm8;
 
   let Inst{31} = m;
@@ -596,8 +563,7 @@
 class A64I_LDRlit<bits<2> opc, bit v,
                   dag outs, dag ins, string asmstr,
                   list<dag> patterns, InstrItinClass itin>
-  : A64InstRt<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRt<outs, ins, asmstr, patterns, itin> {
   bits<19> Imm19;
 
   let Inst{31-30} = opc;
@@ -612,8 +578,7 @@
 class A64I_LDSTex_tn<bits<2> size, bit o2, bit L, bit o1, bit o0,
                  dag outs, dag ins, string asmstr,
                  list <dag> patterns, InstrItinClass itin>
-  : A64InstRtn<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRtn<outs, ins, asmstr, patterns, itin> {
   let Inst{31-30} = size;
   let Inst{29-24} = 0b001000;
   let Inst{23} = o2;
@@ -650,8 +615,7 @@
 class A64I_LSpostind<bits<2> size, bit v, bits<2> opc,
                      dag outs, dag ins, string asmstr,
                      list<dag> patterns, InstrItinClass itin>
-  : A64InstRtn<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRtn<outs, ins, asmstr, patterns, itin> {
   bits<9> SImm9;
 
   let Inst{31-30} = size;
@@ -670,8 +634,7 @@
 class A64I_LSpreind<bits<2> size, bit v, bits<2> opc,
                     dag outs, dag ins, string asmstr,
                     list<dag> patterns, InstrItinClass itin>
-  : A64InstRtn<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRtn<outs, ins, asmstr, patterns, itin> {
   bits<9> SImm9;
 
 
@@ -691,8 +654,7 @@
 class A64I_LSunpriv<bits<2> size, bit v, bits<2> opc,
                     dag outs, dag ins, string asmstr,
                     list<dag> patterns, InstrItinClass itin>
-  : A64InstRtn<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRtn<outs, ins, asmstr, patterns, itin> {
   bits<9> SImm9;
 
 
@@ -712,8 +674,7 @@
 class A64I_LSunalimm<bits<2> size, bit v, bits<2> opc,
                      dag outs, dag ins, string asmstr,
                      list<dag> patterns, InstrItinClass itin>
-  : A64InstRtn<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRtn<outs, ins, asmstr, patterns, itin> {
   bits<9> SImm9;
 
   let Inst{31-30} = size;
@@ -733,8 +694,7 @@
 class A64I_LSunsigimm<bits<2> size, bit v, bits<2> opc,
                       dag outs, dag ins, string asmstr,
                       list<dag> patterns, InstrItinClass itin>
-  : A64InstRtn<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRtn<outs, ins, asmstr, patterns, itin> {
   bits<12> UImm12;
 
   let Inst{31-30} = size;
@@ -749,8 +709,7 @@
 class A64I_LSregoff<bits<2> size, bit v, bits<2> opc, bit optionlo,
                     dag outs, dag ins, string asmstr,
                     list<dag> patterns, InstrItinClass itin>
-  : A64InstRtn<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRtn<outs, ins, asmstr, patterns, itin> {
   bits<5> Rm;
 
   // Complex operand selection needed for these instructions, so they
@@ -780,8 +739,7 @@
 class A64I_LSPoffset<bits<2> opc, bit v, bit l,
                       dag outs, dag ins, string asmstr,
                       list<dag> patterns, InstrItinClass itin>
-  : A64InstRtt2n<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRtt2n<outs, ins, asmstr, patterns, itin> {
   bits<7> SImm7;
 
   let Inst{31-30} = opc;
@@ -799,8 +757,7 @@
 class A64I_LSPpostind<bits<2> opc, bit v, bit l,
                       dag outs, dag ins, string asmstr,
                       list<dag> patterns, InstrItinClass itin>
-  : A64InstRtt2n<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRtt2n<outs, ins, asmstr, patterns, itin> {
   bits<7> SImm7;
 
   let Inst{31-30} = opc;
@@ -818,8 +775,7 @@
 class A64I_LSPpreind<bits<2> opc, bit v, bit l,
                       dag outs, dag ins, string asmstr,
                       list<dag> patterns, InstrItinClass itin>
-  : A64InstRtt2n<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRtt2n<outs, ins, asmstr, patterns, itin> {
   bits<7> SImm7;
 
   let Inst{31-30} = opc;
@@ -837,8 +793,7 @@
 class A64I_LSPnontemp<bits<2> opc, bit v, bit l,
                       dag outs, dag ins, string asmstr,
                       list<dag> patterns, InstrItinClass itin>
-  : A64InstRtt2n<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRtt2n<outs, ins, asmstr, patterns, itin> {
   bits<7> SImm7;
 
   let Inst{31-30} = opc;
@@ -856,8 +811,7 @@
 class A64I_logicalimm<bit sf, bits<2> opc,
                       dag outs, dag ins, string asmstr,
                       list<dag> patterns, InstrItinClass itin>
-  : A64InstRdn<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRdn<outs, ins, asmstr, patterns, itin> {
   bit N;
   bits<6> ImmR;
   bits<6> ImmS;
@@ -883,8 +837,7 @@
 class A64I_logicalshift<bit sf, bits<2> opc, bits<2> shift, bit N,
                         dag outs, dag ins, string asmstr,
                         list<dag> patterns, InstrItinClass itin>
-  : A64InstRdnm<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRdnm<outs, ins, asmstr, patterns, itin> {
   bits<6> Imm6;
 
   let Inst{31} = sf;
@@ -902,8 +855,7 @@
 class A64I_movw<bit sf, bits<2> opc,
                 dag outs, dag ins, string asmstr,
                 list<dag> patterns, InstrItinClass itin>
-  : A64InstRd<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRd<outs, ins, asmstr, patterns, itin> {
   bits<16> UImm16;
   bits<2> Shift; // Called "hw" officially
 
@@ -919,8 +871,7 @@
 class A64I_PCADR<bit op,
                  dag outs, dag ins, string asmstr,
                  list<dag> patterns, InstrItinClass itin>
-  : A64InstRd<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRd<outs, ins, asmstr, patterns, itin> {
   bits<21> Label;
 
   let Inst{31} = op;
@@ -933,8 +884,7 @@
 class A64I_system<bit l,
                   dag outs, dag ins, string asmstr,
                   list<dag> patterns, InstrItinClass itin>
-  : A64Inst<outs, ins, asmstr, patterns, itin>
-{
+  : A64Inst<outs, ins, asmstr, patterns, itin> {
   bits<2> Op0;
   bits<3> Op1;
   bits<4> CRn;
@@ -959,8 +909,7 @@
 class A64I_Bimm<bit op,
                 dag outs, dag ins, string asmstr,
                 list<dag> patterns, InstrItinClass itin>
-  : A64Inst<outs, ins, asmstr, patterns, itin>
-{
+  : A64Inst<outs, ins, asmstr, patterns, itin> {
   // Doubly special in not even sharing register fields with other
   // instructions, so we create our own Rn here.
   bits<26> Label;
@@ -974,8 +923,7 @@
 class A64I_TBimm<bit op,
                 dag outs, dag ins, string asmstr,
                 list<dag> patterns, InstrItinClass itin>
-  : A64InstRt<outs, ins, asmstr, patterns, itin>
-{
+  : A64InstRt<outs, ins, asmstr, patterns, itin> {
   // Doubly special in not even sharing register fields with other
   // instructions, so we create our own Rn here.
   bits<6> Imm;
@@ -995,8 +943,7 @@
 class A64I_Breg<bits<4> opc, bits<5> op2, bits<6> op3, bits<5> op4,
                 dag outs, dag ins, string asmstr,
                 list<dag> patterns, InstrItinClass itin>
-  : A64Inst<outs, ins, asmstr, patterns, itin>
-{
+  : A64Inst<outs, ins, asmstr, patterns, itin> {
   // Doubly special in not even sharing register fields with other
   // instructions, so we create our own Rn here.
   bits<5> Rn;
diff --git a/lib/Target/AArch64/AArch64InstrInfo.cpp b/lib/Target/AArch64/AArch64InstrInfo.cpp
index d59f2f1..94b3429 100644
--- a/lib/Target/AArch64/AArch64InstrInfo.cpp
+++ b/lib/Target/AArch64/AArch64InstrInfo.cpp
@@ -613,7 +613,8 @@
   llvm_unreachable("Unimplemented rewriteFrameIndex");
 }
 
-void llvm::emitRegUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
+void llvm::emitRegUpdate(MachineBasicBlock &MBB,
+                         MachineBasicBlock::iterator MBBI,
                          DebugLoc dl, const TargetInstrInfo &TII,
                          unsigned DstReg, unsigned SrcReg, unsigned ScratchReg,
                          int64_t NumBytes, MachineInstr::MIFlag MIFlags) {
@@ -695,7 +696,8 @@
     LDTLSCleanup() : MachineFunctionPass(ID) {}
 
     virtual bool runOnMachineFunction(MachineFunction &MF) {
-      AArch64MachineFunctionInfo* MFI = MF.getInfo<AArch64MachineFunctionInfo>();
+      AArch64MachineFunctionInfo* MFI
+        = MF.getInfo<AArch64MachineFunctionInfo>();
       if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
         // No point folding accesses if there isn't at least two.
         return false;
diff --git a/lib/Target/AArch64/AArch64InstrInfo.td b/lib/Target/AArch64/AArch64InstrInfo.td
index 3c15200..673e051 100644
--- a/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/lib/Target/AArch64/AArch64InstrInfo.td
@@ -113,7 +113,8 @@
 def SDTTLSDescCall : SDTypeProfile<0, -2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
 
 def A64tlsdesc_blr : SDNode<"AArch64ISD::TLSDESCCALL", SDTTLSDescCall,
-                            [SDNPInGlue, SDNPOutGlue, SDNPHasChain, SDNPVariadic]>;
+                            [SDNPInGlue, SDNPOutGlue, SDNPHasChain,
+                             SDNPVariadic]>;
 
 
 def SDT_AArch64CallSeqStart : SDCallSeqStart<[ SDTCisPtrTy<0> ]>;
@@ -132,8 +133,7 @@
 // arguments passed on the stack. Here we select those markers to
 // pseudo-instructions which explicitly set the stack, and finally in the
 // RegisterInfo we convert them to a true stack adjustment.
-let Defs = [XSP], Uses = [XSP] in
-{
+let Defs = [XSP], Uses = [XSP] in {
   def ADJCALLSTACKDOWN : PseudoInst<(outs), (ins i64imm:$amt),
                                     [(AArch64callseq_start timm:$amt)]>;
 
@@ -146,16 +146,15 @@
 //===----------------------------------------------------------------------===//
 
 let usesCustomInserter = 1, Defs = [NZCV] in {
-multiclass AtomicSizes<string opname>
-{
+multiclass AtomicSizes<string opname> {
   def _I8 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr),
     [(set GPR32:$dst, (!cast<SDNode>(opname # "_8") GPR64:$ptr, GPR32:$incr))]>;
   def _I16 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr),
-    [(set GPR32:$dst, (!cast<SDNode>(opname # "_16") GPR64:$ptr, GPR32:$incr))]>;
+   [(set GPR32:$dst, (!cast<SDNode>(opname # "_16") GPR64:$ptr, GPR32:$incr))]>;
   def _I32 : PseudoInst<(outs GPR32:$dst), (ins GPR64:$ptr, GPR32:$incr),
-    [(set GPR32:$dst, (!cast<SDNode>(opname # "_32") GPR64:$ptr, GPR32:$incr))]>;
+   [(set GPR32:$dst, (!cast<SDNode>(opname # "_32") GPR64:$ptr, GPR32:$incr))]>;
   def _I64 : PseudoInst<(outs GPR64:$dst), (ins GPR64:$ptr, GPR64:$incr),
-    [(set GPR64:$dst, (!cast<SDNode>(opname # "_64") GPR64:$ptr, GPR64:$incr))]>;
+   [(set GPR64:$dst, (!cast<SDNode>(opname # "_64") GPR64:$ptr, GPR64:$incr))]>;
 }
 }
 
@@ -205,17 +204,15 @@
 // is not optional in that case (but can explicitly be 0), and the
 // entire suffix can be skipped (e.g. "add sp, x3, x2").
 
-multiclass extend_operands<string PREFIX>
-{
-     def _asmoperand : AsmOperandClass
-     {
+multiclass extend_operands<string PREFIX> {
+     def _asmoperand : AsmOperandClass {
          let Name = PREFIX;
          let RenderMethod = "addRegExtendOperands";
          let PredicateMethod = "isRegExtend<A64SE::" # PREFIX # ">";
      }
 
-     def _operand : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 4; }]>
-     {
+     def _operand : Operand<i64>,
+                    ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 4; }]> {
          let PrintMethod = "printRegExtendOperand<A64SE::" # PREFIX # ">";
          let DecoderMethod = "DecodeRegExtendOperand";
          let ParserMatchClass = !cast<AsmOperandClass>(PREFIX # "_asmoperand");
@@ -231,14 +228,12 @@
 defm SXTW : extend_operands<"SXTW">;
 defm SXTX : extend_operands<"SXTX">;
 
-def LSL_extasmoperand : AsmOperandClass
-{
+def LSL_extasmoperand : AsmOperandClass {
     let Name = "RegExtendLSL";
     let RenderMethod = "addRegExtendOperands";
 }
 
-def LSL_extoperand : Operand<i64>
-{
+def LSL_extoperand : Operand<i64> {
     let ParserMatchClass = LSL_extasmoperand;
 }
 
@@ -247,14 +242,12 @@
 // non-uniform because everything has already been promoted to the
 // legal i64 and i32 types. We'll wrap the various variants up in a
 // class for use later.
-class extend_types
-{
+class extend_types {
     dag uxtb; dag uxth; dag uxtw; dag uxtx;
     dag sxtb; dag sxth; dag sxtw; dag sxtx;
 }
 
-def extends_to_i64 : extend_types
-{
+def extends_to_i64 : extend_types {
     let uxtb = (and (anyext GPR32:$Rm), 255);
     let uxth = (and (anyext GPR32:$Rm), 65535);
     let uxtw = (zext GPR32:$Rm);
@@ -267,8 +260,7 @@
 }
 
 
-def extends_to_i32 : extend_types
-{
+def extends_to_i32 : extend_types {
     let uxtb = (and GPR32:$Rm, 255);
     let uxth = (and GPR32:$Rm, 65535);
     let uxtw = (i32 GPR32:$Rm);
@@ -290,9 +282,9 @@
 //     + Patterns are very different as well.
 //     + Passing different registers would be ugly (more fields in extend_types
 //       would probably be the best option).
-multiclass addsub_exts<bit sf, bit op, bit S, string asmop, SDPatternOperator opfrag,
-                       dag outs, extend_types exts, RegisterClass GPRsp>
-{
+multiclass addsub_exts<bit sf, bit op, bit S, string asmop,
+                       SDPatternOperator opfrag,
+                       dag outs, extend_types exts, RegisterClass GPRsp> {
     def w_uxtb : A64I_addsubext<sf, op, S, 0b00, 0b000,
                       outs,
                       (ins GPRsp:$Rn, GPR32:$Rm, UXTB_operand:$Imm3),
@@ -334,8 +326,8 @@
 
 // These two could be merge in with the above, but their patterns aren't really
 // necessary and the naming-scheme would necessarily break:
-multiclass addsub_xxtx<bit op, bit S, string asmop, SDPatternOperator opfrag, dag outs>
-{
+multiclass addsub_xxtx<bit op, bit S, string asmop, SDPatternOperator opfrag,
+                       dag outs> {
     def x_uxtx : A64I_addsubext<0b1, op, S, 0b00, 0b011,
                    outs,
                    (ins GPR64xsp:$Rn, GPR64:$Rm, UXTX_operand:$Imm3),
@@ -351,8 +343,7 @@
                    NoItinerary>;
 }
 
-multiclass addsub_wxtx<bit op, bit S, string asmop, dag outs>
-{
+multiclass addsub_wxtx<bit op, bit S, string asmop, dag outs> {
     def w_uxtx : A64I_addsubext<0b0, op, S, 0b00, 0b011,
                               outs,
                               (ins GPR32wsp:$Rn, GPR32:$Rm, UXTX_operand:$Imm3),
@@ -429,8 +420,7 @@
 // created for uxtx/sxtx since they're non-uniform and it's expected that
 // add/sub (shifted register) will handle those cases anyway.
 multiclass addsubext_noshift_patterns<string prefix, SDPatternOperator nodeop,
-                                      RegisterClass GPRsp, extend_types exts>
-{
+                                      RegisterClass GPRsp, extend_types exts> {
     def : Pat<(nodeop GPRsp:$Rn, exts.uxtb),
               (!cast<Instruction>(prefix # "w_uxtb") GPRsp:$Rn, GPR32:$Rm, 0)>;
     def : Pat<(nodeop GPRsp:$Rn, exts.uxth),
@@ -461,8 +451,7 @@
 // operation. Also permitted in this case is complete omission of the argument,
 // which implies "lsl #0".
 multiclass lsl_aliases<string asmop, Instruction inst, RegisterClass GPR_Rd,
-                       RegisterClass GPR_Rn, RegisterClass GPR_Rm>
-{
+                       RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
     def : InstAlias<!strconcat(asmop, " $Rd, $Rn, $Rm"),
                     (inst GPR_Rd:$Rd, GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
 
@@ -490,8 +479,7 @@
 // CMP unfortunately has to be different because the instruction doesn't have a
 // dest register.
 multiclass cmp_lsl_aliases<string asmop, Instruction inst,
-                       RegisterClass GPR_Rn, RegisterClass GPR_Rm>
-{
+                       RegisterClass GPR_Rn, RegisterClass GPR_Rm> {
     def : InstAlias<!strconcat(asmop, " $Rn, $Rm"),
                     (inst GPR_Rn:$Rn, GPR_Rm:$Rm, 0)>;
 
@@ -547,16 +535,13 @@
 // should be parsed: there was no way to accommodate an "lsl #12".
 
 let ParserMethod = "ParseImmWithLSLOperand",
-    RenderMethod = "addImmWithLSLOperands" in
-{
+    RenderMethod = "addImmWithLSLOperands" in {
   // Derived PredicateMethod fields are different for each
-  def addsubimm_lsl0_asmoperand : AsmOperandClass
-  {
+  def addsubimm_lsl0_asmoperand : AsmOperandClass {
     let Name = "AddSubImmLSL0";
   }
 
-  def addsubimm_lsl12_asmoperand : AsmOperandClass
-  {
+  def addsubimm_lsl12_asmoperand : AsmOperandClass {
     let Name = "AddSubImmLSL12";
   }
 }
@@ -574,12 +559,10 @@
 }]>;
 
 
-multiclass addsub_imm_operands<ValueType ty>
-{
+multiclass addsub_imm_operands<ValueType ty> {
  let PrintMethod = "printAddSubImmLSL0Operand",
       EncoderMethod = "getAddSubImmOpValue",
-      ParserMatchClass = addsubimm_lsl0_asmoperand in
-  {
+      ParserMatchClass = addsubimm_lsl0_asmoperand in {
     def _posimm_lsl0 : Operand<ty>,
         ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff) == 0; }]>;
     def _negimm_lsl0 : Operand<ty>,
@@ -589,8 +572,7 @@
 
   let PrintMethod = "printAddSubImmLSL12Operand",
       EncoderMethod = "getAddSubImmOpValue",
-      ParserMatchClass = addsubimm_lsl12_asmoperand in
-  {
+      ParserMatchClass = addsubimm_lsl12_asmoperand in {
     def _posimm_lsl12 : Operand<ty>,
         ImmLeaf<ty, [{ return Imm >= 0 && (Imm & ~0xfff000) == 0; }],
                 shr_12_XFORM>;
@@ -609,8 +591,7 @@
                                string asmop, string cmpasmop,
                                Operand imm_operand, Operand cmp_imm_operand,
                                RegisterClass GPR, RegisterClass GPRsp,
-                               AArch64Reg ZR>
-{
+                               AArch64Reg ZR> {
     // All registers for non-S variants allow SP
   def _s : A64I_addsubimm<sf, op, 0b0, shift,
                          (outs GPRsp:$Rd),
@@ -639,8 +620,7 @@
                             !strconcat(cmpasmop, " $Rn, $Imm12"),
                             [(set NZCV,
                               (A64cmp GPRsp:$Rn, cmp_imm_operand:$Imm12))],
-                            NoItinerary>
-  {
+                            NoItinerary> {
     let Rd = 0b11111;
     let Defs = [NZCV];
     let isCompare = 1;
@@ -650,8 +630,7 @@
 
 multiclass addsubimm_shifts<string prefix, bit sf, bit op,
            string asmop, string cmpasmop, string operand, string cmpoperand,
-           RegisterClass GPR, RegisterClass GPRsp, AArch64Reg ZR>
-{
+           RegisterClass GPR, RegisterClass GPRsp, AArch64Reg ZR> {
   defm _lsl0 : addsubimm_varieties<prefix # "_lsl0", sf, op, 0b00,
                                    asmop, cmpasmop,
                                    !cast<Operand>(operand # "_lsl0"),
@@ -682,8 +661,7 @@
                               "addsubimm_operand_i64_posimm",
                               GPR64, GPR64xsp, XZR>;
 
-multiclass MOVsp<RegisterClass GPRsp, RegisterClass SP, Instruction addop>
-{
+multiclass MOVsp<RegisterClass GPRsp, RegisterClass SP, Instruction addop> {
   def _fromsp : InstAlias<"mov $Rd, $Rn",
                           (addop GPRsp:$Rd, SP:$Rn, 0),
                           0b1>;
@@ -706,10 +684,8 @@
 // 1. The "shifed register" operands. Shared with logical insts.
 //===-------------------------------
 
-multiclass shift_operands<string prefix, string form>
-{
-  def _asmoperand_i32 : AsmOperandClass
-  {
+multiclass shift_operands<string prefix, string form> {
+  def _asmoperand_i32 : AsmOperandClass {
     let Name = "Shift" # form # "i32";
     let RenderMethod = "addShiftOperands";
     let PredicateMethod
@@ -718,24 +694,21 @@
 
   // Note that the operand type is intentionally i64 because the DAGCombiner
   // puts these into a canonical form.
-  def _i32 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]>
-  {
+  def _i32 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
     let ParserMatchClass
           = !cast<AsmOperandClass>(prefix # "_asmoperand_i32");
     let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
     let DecoderMethod = "Decode32BitShiftOperand";
   }
 
-  def _asmoperand_i64 : AsmOperandClass
-  {
+  def _asmoperand_i64 : AsmOperandClass {
       let Name = "Shift" # form # "i64";
       let RenderMethod = "addShiftOperands";
       let PredicateMethod
             = "isShift<A64SE::" # form # ", true>";
   }
 
-  def _i64 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]>
-  {
+  def _i64 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
     let ParserMatchClass
           = !cast<AsmOperandClass>(prefix # "_asmoperand_i64");
     let PrintMethod = "printShiftOperand<A64SE::" # form # ">";
@@ -758,8 +731,7 @@
 // when the revolution comes.
 multiclass addsub_shifts<string prefix, bit sf, bit op, bit s, bit commutable,
                          string asmop, SDPatternOperator opfrag, string sty,
-                         RegisterClass GPR, list<Register> defs>
-{
+                         RegisterClass GPR, list<Register> defs> {
   let isCommutable = commutable, Defs = defs in {
   def _lsl : A64I_addsubshift<sf, op, s, 0b00,
                        (outs GPR:$Rd),
@@ -803,8 +775,7 @@
 
 multiclass addsub_sizes<string prefix, bit op, bit s, bit commutable,
                          string asmop, SDPatternOperator opfrag,
-                         list<Register> defs>
-{
+                         list<Register> defs> {
   defm xxx : addsub_shifts<prefix # "xxx", 0b1, op, s,
                            commutable, asmop, opfrag, "i64", GPR64, defs>;
   defm www : addsub_shifts<prefix # "www", 0b0, op, s,
@@ -823,8 +794,7 @@
 //===-------------------------------
 
 multiclass neg_alias<Instruction INST, RegisterClass GPR,
-                     Register ZR, Operand shift_operand, SDNode shiftop>
-{
+                     Register ZR, Operand shift_operand, SDNode shiftop> {
    def : InstAlias<"neg $Rd, $Rm, $Imm6",
                    (INST GPR:$Rd, ZR, GPR:$Rm, shift_operand:$Imm6)>;
 
@@ -867,8 +837,7 @@
 
 multiclass cmp_shifts<string prefix, bit sf, bit op, bit commutable,
                       string asmop, SDPatternOperator opfrag, string sty,
-                      RegisterClass GPR>
-{
+                      RegisterClass GPR> {
   let isCommutable = commutable, Rd = 0b11111, Defs = [NZCV] in {
   def _lsl : A64I_addsubshift<sf, op, 0b1, 0b00,
                        (outs),
@@ -920,10 +889,8 @@
 //===----------------------------------------------------------------------===//
 // Contains: ADC, ADCS, SBC, SBCS + aliases NGC, NGCS
 
-multiclass A64I_addsubcarrySizes<bit op, bit s, string asmop>
-{
-  let Uses = [NZCV] in
-  {
+multiclass A64I_addsubcarrySizes<bit op, bit s, string asmop> {
+  let Uses = [NZCV] in {
     def www : A64I_addsubcarry<0b0, op, s, 0b000000,
                                (outs GPR32:$Rd), (ins GPR32:$Rn, GPR32:$Rm),
                                !strconcat(asmop, "\t$Rd, $Rn, $Rm"),
@@ -936,17 +903,14 @@
   }
 }
 
-let isCommutable = 1 in
-{
+let isCommutable = 1 in {
   defm ADC : A64I_addsubcarrySizes<0b0, 0b0, "adc">;
 }
 
 defm SBC : A64I_addsubcarrySizes<0b1, 0b0, "sbc">;
 
-let Defs = [NZCV] in
-{
-  let isCommutable = 1 in
-  {
+let Defs = [NZCV] in {
+  let isCommutable = 1 in {
     defm ADCS : A64I_addsubcarrySizes<0b0, 0b1, "adcs">;
   }
 
@@ -988,23 +952,20 @@
 // 1. The architectural BFM instructions
 //===-------------------------------
 
-def uimm5_asmoperand : AsmOperandClass
-{
+def uimm5_asmoperand : AsmOperandClass {
   let Name = "UImm5";
   let PredicateMethod = "isUImm<5>";
   let RenderMethod = "addImmOperands";
 }
 
-def uimm6_asmoperand : AsmOperandClass
-{
+def uimm6_asmoperand : AsmOperandClass {
   let Name = "UImm6";
   let PredicateMethod = "isUImm<6>";
   let RenderMethod = "addImmOperands";
 }
 
 def bitfield32_imm : Operand<i64>,
-                     ImmLeaf<i64, [{ return Imm >= 0 && Imm < 32; }]>
-{
+                     ImmLeaf<i64, [{ return Imm >= 0 && Imm < 32; }]> {
   let ParserMatchClass = uimm5_asmoperand;
 
   let DecoderMethod = "DecodeBitfield32ImmOperand";
@@ -1012,28 +973,24 @@
 
 
 def bitfield64_imm : Operand<i64>,
-                     ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]>
-{
+                     ImmLeaf<i64, [{ return Imm >= 0 && Imm < 64; }]> {
   let ParserMatchClass = uimm6_asmoperand;
 
   // Default decoder works in 64-bit case: the 6-bit field can take any value.
 }
 
-multiclass A64I_bitfieldSizes<bits<2> opc, string asmop>
-{
+multiclass A64I_bitfieldSizes<bits<2> opc, string asmop> {
   def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
                     (ins GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
                     !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
-                    [], NoItinerary>
-  {
+                    [], NoItinerary> {
     let DecoderMethod = "DecodeBitfieldInstruction";
   }
 
   def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
                     (ins GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
                     !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
-                    [], NoItinerary>
-  {
+                    [], NoItinerary> {
     let DecoderMethod = "DecodeBitfieldInstruction";
   }
 }
@@ -1046,8 +1003,7 @@
 def BFMwwii :
   A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
         (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bitfield32_imm:$ImmS),
-        "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>
-{
+        "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
   let DecoderMethod = "DecodeBitfieldInstruction";
   let Constraints = "$src = $Rd";
 }
@@ -1055,8 +1011,7 @@
 def BFMxxii :
   A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
         (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bitfield64_imm:$ImmS),
-        "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>
-{
+        "bfm\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
   let DecoderMethod = "DecodeBitfieldInstruction";
   let Constraints = "$src = $Rd";
 }
@@ -1078,8 +1033,7 @@
   : A64I_bitfield<sf, opc, sf,
                   (outs GPRDest:$Rd), (ins GPR32:$Rn),
                   !strconcat(asmop, "\t$Rd, $Rn"),
-                  [(set GPRDest:$Rd, pattern)], NoItinerary>
-{
+                  [(set GPRDest:$Rd, pattern)], NoItinerary> {
   let ImmR = 0b000000;
   let ImmS = imms;
 }
@@ -1103,8 +1057,7 @@
 
 // The 64-bit unsigned variants are not strictly architectural but recommended
 // for consistency.
-let isAsmParserOnly = 1 in
-{
+let isAsmParserOnly = 1 in {
   def UXTBxw : A64I_bf_ext<0b0, 0b10, GPR64, "uxtb", 7,
                            (and (anyext GPR32:$Rn), 255)>;
   def UXTHxw : A64I_bf_ext<0b0, 0b10, GPR64, "uxth", 15,
@@ -1129,14 +1082,12 @@
 
 // These also handle their own decoding because ImmS being set makes
 // them take precedence over BFM.
-multiclass A64I_shift<bits<2> opc, string asmop, SDNode opnode>
-{
+multiclass A64I_shift<bits<2> opc, string asmop, SDNode opnode> {
   def wwi : A64I_bitfield<0b0, opc, 0b0,
                     (outs GPR32:$Rd), (ins GPR32:$Rn, bitfield32_imm:$ImmR),
                     !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
                     [(set GPR32:$Rd, (opnode GPR32:$Rn, bitfield32_imm:$ImmR))],
-                    NoItinerary>
-  {
+                    NoItinerary> {
     let ImmS = 31;
   }
 
@@ -1144,8 +1095,7 @@
                     (outs GPR64:$Rd), (ins GPR64:$Rn, bitfield64_imm:$ImmR),
                     !strconcat(asmop, "\t$Rd, $Rn, $ImmR"),
                     [(set GPR64:$Rd, (opnode GPR64:$Rn, bitfield64_imm:$ImmR))],
-                    NoItinerary>
-  {
+                    NoItinerary> {
     let ImmS = 63;
   }
 
@@ -1170,15 +1120,13 @@
 // outweighed the benefits in this case (custom asmparser, printer and selection
 // vs custom encoder).
 def bitfield32_lsl_imm : Operand<i64>,
-                         ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]>
-{
+                         ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
   let ParserMatchClass = uimm5_asmoperand;
   let EncoderMethod = "getBitfield32LSLOpValue";
 }
 
 def bitfield64_lsl_imm : Operand<i64>,
-                         ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]>
-{
+                         ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
   let ParserMatchClass = uimm6_asmoperand;
   let EncoderMethod = "getBitfield64LSLOpValue";
 }
@@ -1187,8 +1135,7 @@
   : A64I_bitfield<sf, 0b10, sf, (outs GPR:$Rd), (ins GPR:$Rn, operand:$FullImm),
                   "lsl\t$Rd, $Rn, $FullImm",
                   [(set GPR:$Rd, (shl GPR:$Rn, operand:$FullImm))],
-                  NoItinerary>
-{
+                  NoItinerary> {
   bits<12> FullImm;
   let ImmR = FullImm{5-0};
   let ImmS = FullImm{11-6};
@@ -1205,41 +1152,35 @@
 // 5. Aliases for bitfield extract instructions
 //===-------------------------------
 
-def bfx32_width_asmoperand : AsmOperandClass
-{
+def bfx32_width_asmoperand : AsmOperandClass {
   let Name = "BFX32Width";
   let PredicateMethod = "isBitfieldWidth<32>";
   let RenderMethod = "addBFXWidthOperands";
 }
 
-def bfx32_width : Operand<i64>, ImmLeaf<i64, [{ return true; }]>
-{
+def bfx32_width : Operand<i64>, ImmLeaf<i64, [{ return true; }]> {
   let PrintMethod = "printBFXWidthOperand";
   let ParserMatchClass = bfx32_width_asmoperand;
 }
 
-def bfx64_width_asmoperand : AsmOperandClass
-{
+def bfx64_width_asmoperand : AsmOperandClass {
   let Name = "BFX64Width";
   let PredicateMethod = "isBitfieldWidth<64>";
   let RenderMethod = "addBFXWidthOperands";
 }
 
-def bfx64_width : Operand<i64>
-{
+def bfx64_width : Operand<i64> {
   let PrintMethod = "printBFXWidthOperand";
   let ParserMatchClass = bfx64_width_asmoperand;
 }
 
 
-multiclass A64I_bitfield_extract<bits<2> opc, string asmop, SDNode op>
-{
+multiclass A64I_bitfield_extract<bits<2> opc, string asmop, SDNode op> {
   def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
                        (ins GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
                        !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
                        [(set GPR32:$Rd, (op GPR32:$Rn, imm:$ImmR, imm:$ImmS))],
-                       NoItinerary>
-  {
+                       NoItinerary> {
     // As above, no disassembler allowed.
     let isAsmParserOnly = 1;
   }
@@ -1248,8 +1189,7 @@
                        (ins GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
                        !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
                        [(set GPR64:$Rd, (op GPR64:$Rn, imm:$ImmR, imm:$ImmS))],
-                       NoItinerary>
-  {
+                       NoItinerary> {
     // As above, no disassembler allowed.
     let isAsmParserOnly = 1;
   }
@@ -1261,8 +1201,7 @@
 // Again, variants based on BFM modify Rd so need it as an input too.
 def BFXILwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
            (ins GPR32:$src, GPR32:$Rn, bitfield32_imm:$ImmR, bfx32_width:$ImmS),
-           "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>
-{
+           "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
   // As above, no disassembler allowed.
   let isAsmParserOnly = 1;
   let Constraints = "$src = $Rd";
@@ -1270,8 +1209,7 @@
 
 def BFXILxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
            (ins GPR64:$src, GPR64:$Rn, bitfield64_imm:$ImmR, bfx64_width:$ImmS),
-           "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>
-{
+           "bfxil\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
   // As above, no disassembler allowed.
   let isAsmParserOnly = 1;
   let Constraints = "$src = $Rd";
@@ -1285,34 +1223,33 @@
 
 // UBFX makes sense as an implementation of a 64-bit zero-extension too. Could
 // use either 64-bit or 32-bit variant, but 32-bit might be more efficient.
-def : Pat<(zext GPR32:$Rn), (SUBREG_TO_REG (i64 0), (UBFXwwii GPR32:$Rn, 0, 31), sub_32)>;
+def : Pat<(zext GPR32:$Rn), (SUBREG_TO_REG (i64 0), (UBFXwwii GPR32:$Rn, 0, 31),
+                                           sub_32)>;
 
 //===-------------------------------
 // 6. Aliases for bitfield insert instructions
 //===-------------------------------
 
-def bfi32_lsb_asmoperand : AsmOperandClass
-{
+def bfi32_lsb_asmoperand : AsmOperandClass {
   let Name = "BFI32LSB";
   let PredicateMethod = "isUImm<5>";
   let RenderMethod = "addBFILSBOperands<32>";
 }
 
-def bfi32_lsb : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]>
-{
+def bfi32_lsb : Operand<i64>,
+                ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 31; }]> {
   let PrintMethod = "printBFILSBOperand<32>";
   let ParserMatchClass = bfi32_lsb_asmoperand;
 }
 
-def bfi64_lsb_asmoperand : AsmOperandClass
-{
+def bfi64_lsb_asmoperand : AsmOperandClass {
   let Name = "BFI64LSB";
   let PredicateMethod = "isUImm<6>";
   let RenderMethod = "addBFILSBOperands<64>";
 }
 
-def bfi64_lsb : Operand<i64>, ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]>
-{
+def bfi64_lsb : Operand<i64>,
+                ImmLeaf<i64, [{ return Imm >= 0 && Imm <= 63; }]> {
   let PrintMethod = "printBFILSBOperand<64>";
   let ParserMatchClass = bfi64_lsb_asmoperand;
 }
@@ -1320,41 +1257,35 @@
 // Width verification is performed during conversion so width operand can be
 // shared between 32/64-bit cases. Still needed for the print method though
 // because ImmR encodes "width - 1".
-def bfi32_width_asmoperand : AsmOperandClass
-{
+def bfi32_width_asmoperand : AsmOperandClass {
   let Name = "BFI32Width";
   let PredicateMethod = "isBitfieldWidth<32>";
   let RenderMethod = "addBFIWidthOperands";
 }
 
 def bfi32_width : Operand<i64>,
-                  ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 32; }]>
-{
+                  ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 32; }]> {
   let PrintMethod = "printBFIWidthOperand";
   let ParserMatchClass = bfi32_width_asmoperand;
 }
 
-def bfi64_width_asmoperand : AsmOperandClass
-{
+def bfi64_width_asmoperand : AsmOperandClass {
   let Name = "BFI64Width";
   let PredicateMethod = "isBitfieldWidth<64>";
   let RenderMethod = "addBFIWidthOperands";
 }
 
 def bfi64_width : Operand<i64>,
-                  ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 64; }]>
-{
+                  ImmLeaf<i64, [{ return Imm >= 1 && Imm <= 64; }]> {
   let PrintMethod = "printBFIWidthOperand";
   let ParserMatchClass = bfi64_width_asmoperand;
 }
 
-multiclass A64I_bitfield_insert<bits<2> opc, string asmop>
-{
+multiclass A64I_bitfield_insert<bits<2> opc, string asmop> {
   def wwii : A64I_bitfield<0b0, opc, 0b0, (outs GPR32:$Rd),
                            (ins GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
                            !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
-                           [], NoItinerary>
-  {
+                           [], NoItinerary> {
     // As above, no disassembler allowed.
     let isAsmParserOnly = 1;
   }
@@ -1362,12 +1293,10 @@
   def xxii : A64I_bitfield<0b1, opc, 0b1, (outs GPR64:$Rd),
                            (ins GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
                            !strconcat(asmop, "\t$Rd, $Rn, $ImmR, $ImmS"),
-                           [], NoItinerary>
-  {
+                           [], NoItinerary> {
     // As above, no disassembler allowed.
     let isAsmParserOnly = 1;
   }
-
 }
 
 defm SBFIZ :  A64I_bitfield_insert<0b00, "sbfiz">;
@@ -1375,18 +1304,16 @@
 
 
 def BFIwwii : A64I_bitfield<0b0, 0b01, 0b0, (outs GPR32:$Rd),
-                  (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
-                  "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>
-{
+                (ins GPR32:$src, GPR32:$Rn, bfi32_lsb:$ImmR, bfi32_width:$ImmS),
+                "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
   // As above, no disassembler allowed.
   let isAsmParserOnly = 1;
   let Constraints = "$src = $Rd";
 }
 
 def BFIxxii : A64I_bitfield<0b1, 0b01, 0b1, (outs GPR64:$Rd),
-                  (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
-                  "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary>
-{
+                (ins GPR64:$src, GPR64:$Rn, bfi64_lsb:$ImmR, bfi64_width:$ImmS),
+                "bfi\t$Rd, $Rn, $ImmR, $ImmS", [], NoItinerary> {
   // As above, no disassembler allowed.
   let isAsmParserOnly = 1;
   let Constraints = "$src = $Rd";
@@ -1397,8 +1324,7 @@
 //===----------------------------------------------------------------------===//
 // Contains: CBZ, CBNZ
 
-class label_asmoperand<int width, int scale> : AsmOperandClass
-{
+class label_asmoperand<int width, int scale> : AsmOperandClass {
   let Name = "Label" # width # "_" # scale;
   let PredicateMethod = "isLabel<" # width # "," # scale # ">";
   let RenderMethod = "addLabelOperands<" # width # ", " # scale # ">";
@@ -1408,8 +1334,7 @@
 
 // All conditional immediate branches are the same really: 19 signed bits scaled
 // by the instruction-size (4).
-def bcc_target : Operand<OtherVT>
-{
+def bcc_target : Operand<OtherVT> {
   // This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
   let ParserMatchClass = label_wid19_scal4_asmoperand;
   let PrintMethod = "printLabelOperand<19, 4>";
@@ -1417,8 +1342,7 @@
   let OperandType = "OPERAND_PCREL";
 }
 
-multiclass cmpbr_sizes<bit op, string asmop, ImmLeaf SETOP>
-{
+multiclass cmpbr_sizes<bit op, string asmop, ImmLeaf SETOP> {
   let isBranch = 1, isTerminator = 1 in {
   def x : A64I_cmpbr<0b1, op,
                      (outs),
@@ -1448,15 +1372,13 @@
 //===----------------------------------------------------------------------===//
 // Contains: B.cc
 
-def cond_code_asmoperand : AsmOperandClass
-{
+def cond_code_asmoperand : AsmOperandClass {
   let Name = "CondCode";
 }
 
 def cond_code : Operand<i32>, ImmLeaf<i32, [{
   return Imm >= 0 && Imm <= 15;
-}]>
-{
+}]> {
   let PrintMethod = "printCondCodeOperand";
   let ParserMatchClass = cond_code_asmoperand;
 }
@@ -1464,8 +1386,7 @@
 def Bcc : A64I_condbr<0b0, 0b0, (outs),
                 (ins cond_code:$Cond, bcc_target:$Label),
                 "b.$Cond $Label", [(A64br_cc NZCV, (i32 imm:$Cond), bb:$Label)],
-                NoItinerary>
-{
+                NoItinerary> {
   let Uses = [NZCV];
   let isBranch = 1;
   let isTerminator = 1;
@@ -1476,36 +1397,31 @@
 //===----------------------------------------------------------------------===//
 // Contains: CCMN, CCMP
 
-def uimm4_asmoperand : AsmOperandClass
-{
+def uimm4_asmoperand : AsmOperandClass {
   let Name = "UImm4";
   let PredicateMethod = "isUImm<4>";
   let RenderMethod = "addImmOperands";
 }
 
-def uimm4 : Operand<i32>
-{
+def uimm4 : Operand<i32> {
   let ParserMatchClass = uimm4_asmoperand;
 }
 
-def uimm5 : Operand<i32>
-{
+def uimm5 : Operand<i32> {
   let ParserMatchClass = uimm5_asmoperand;
 }
 
 // The only difference between this operand and the one for instructions like
 // B.cc is that it's parsed manually. The other get parsed implicitly as part of
 // the mnemonic handling.
-def cond_code_op_asmoperand : AsmOperandClass
-{
+def cond_code_op_asmoperand : AsmOperandClass {
   let Name = "CondCodeOp";
   let RenderMethod = "addCondCodeOperands";
   let PredicateMethod = "isCondCode";
   let ParserMethod = "ParseCondCodeOperand";
 }
 
-def cond_code_op : Operand<i32>
-{
+def cond_code_op : Operand<i32> {
   let PrintMethod = "printCondCodeOperand";
   let ParserMatchClass = cond_code_op_asmoperand;
 }
@@ -1514,8 +1430,7 @@
   : A64I_condcmpimm<sf, op, 0b0, 0b0, 0b1, (outs),
                 (ins GPR:$Rn, uimm5:$UImm5, uimm4:$NZCVImm, cond_code_op:$Cond),
                 !strconcat(asmop, "\t$Rn, $UImm5, $NZCVImm, $Cond"),
-                [], NoItinerary>
-{
+                [], NoItinerary> {
   let Defs = [NZCV];
 }
 
@@ -1534,8 +1449,7 @@
                     (outs),
                     (ins GPR:$Rn, GPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
                     !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
-                    [], NoItinerary>
-{
+                    [], NoItinerary> {
   let Defs = [NZCV];
 }
 
@@ -1551,16 +1465,14 @@
 
 // Condition code which is encoded as the inversion (semantically rather than
 // bitwise) in the instruction.
-def inv_cond_code_op_asmoperand : AsmOperandClass
-{
+def inv_cond_code_op_asmoperand : AsmOperandClass {
   let Name = "InvCondCodeOp";
   let RenderMethod = "addInvCondCodeOperands";
   let PredicateMethod = "isCondCode";
   let ParserMethod = "ParseCondCodeOperand";
 }
 
-def inv_cond_code_op : Operand<i32>
-{
+def inv_cond_code_op : Operand<i32> {
   let ParserMatchClass = inv_cond_code_op_asmoperand;
 }
 
@@ -1576,10 +1488,8 @@
 
 
 multiclass A64I_condselSizes<bit op, bits<2> op2, string asmop,
-                             SDPatternOperator select>
-{
-  let Uses = [NZCV] in
-  {
+                             SDPatternOperator select> {
+  let Uses = [NZCV] in {
     def wwwc : A64I_condsel<0b0, op, 0b0, op2,
                             (outs GPR32:$Rd),
                             (ins GPR32:$Rn, GPR32:$Rm, cond_code_op:$Cond),
@@ -1667,9 +1577,11 @@
 // No commutable pattern for CSEL since the commuted version is isomorphic.
 
 // CSINC
-def :Pat<(A64select_cc NZCV, (add GPR32:$Rm, 1), GPR32:$Rn, inv_cond_code:$Cond),
+def :Pat<(A64select_cc NZCV, (add GPR32:$Rm, 1), GPR32:$Rn,
+         inv_cond_code:$Cond),
          (CSINCwwwc GPR32:$Rn, GPR32:$Rm, inv_cond_code:$Cond)>;
-def :Pat<(A64select_cc NZCV, (add GPR64:$Rm, 1), GPR64:$Rn, inv_cond_code:$Cond),
+def :Pat<(A64select_cc NZCV, (add GPR64:$Rm, 1), GPR64:$Rn,
+         inv_cond_code:$Cond),
          (CSINCxxxc GPR64:$Rn, GPR64:$Rm, inv_cond_code:$Cond)>;
 
 // CSINV
@@ -1763,7 +1675,8 @@
    def www : dp_2src_impl<0b0,
                          opcode,
                          asmop,
-                         [(set GPR32:$Rd, (op GPR32:$Rn, (i64 (zext GPR32:$Rm))))],
+                         [(set GPR32:$Rd,
+                               (op GPR32:$Rn, (i64 (zext GPR32:$Rm))))],
                          GPR32,
                          NoItinerary>;
    def xxx : dp_2src_impl<0b1,
@@ -1829,8 +1742,7 @@
   : A64I_dp3<sf, opcode,
              (outs AccReg:$Rd), (ins SrcReg:$Rn, SrcReg:$Rm, AccReg:$Ra),
              !strconcat(asmop, "\t$Rd, $Rn, $Rm, $Ra"),
-             [(set AccReg:$Rd, pattern)], NoItinerary>
-{
+             [(set AccReg:$Rd, pattern)], NoItinerary> {
   RegisterClass AccGPR = AccReg;
   RegisterClass SrcGPR = SrcReg;
 }
@@ -1855,8 +1767,7 @@
 def UMSUBLxwwx : A64I_dp3_4operand<0b1, 0b001011, GPR64, GPR32, "umsubl",
                (sub GPR64:$Ra, (mul (i64 (zext GPR32:$Rn)), (zext GPR32:$Rm)))>;
 
-let isCommutable = 1, PostEncoderMethod = "fixMulHigh" in
-{
+let isCommutable = 1, PostEncoderMethod = "fixMulHigh" in {
   def UMULHxxx : A64I_dp3<0b1, 0b001100, (outs GPR64:$Rd),
                           (ins GPR64:$Rn, GPR64:$Rm),
                           "umulh\t$Rd, $Rn, $Rm",
@@ -1871,8 +1782,7 @@
 }
 
 multiclass A64I_dp3_3operand<string asmop, A64I_dp3_4operand INST,
-                             Register ZR, dag pattern>
-{
+                             Register ZR, dag pattern> {
   def : InstAlias<asmop # " $Rd, $Rn, $Rm",
                   (INST INST.AccGPR:$Rd, INST.SrcGPR:$Rn, INST.SrcGPR:$Rm, ZR)>;
 
@@ -1890,12 +1800,12 @@
 defm : A64I_dp3_3operand<"smull", SMADDLxwwx, XZR,
                          (mul (i64 (sext GPR32:$Rn)), (sext GPR32:$Rm))>;
 defm : A64I_dp3_3operand<"smnegl", SMSUBLxwwx, XZR,
-                        (sub 0, (mul (i64 (sext GPR32:$Rn)), (sext GPR32:$Rm)))>;
+                       (sub 0, (mul (i64 (sext GPR32:$Rn)), (sext GPR32:$Rm)))>;
 
 defm : A64I_dp3_3operand<"umull", UMADDLxwwx, XZR,
                          (mul (i64 (zext GPR32:$Rn)), (zext GPR32:$Rm))>;
 defm : A64I_dp3_3operand<"umnegl", UMSUBLxwwx, XZR,
-                        (sub 0, (mul (i64 (zext GPR32:$Rn)), (zext GPR32:$Rm)))>;
+                       (sub 0, (mul (i64 (zext GPR32:$Rn)), (zext GPR32:$Rm)))>;
 
 
 //===----------------------------------------------------------------------===//
@@ -1903,22 +1813,19 @@
 //===----------------------------------------------------------------------===//
 // Contains: SVC, HVC, SMC, BRK, HLT, DCPS1, DCPS2, DCPS3
 
-def uimm16_asmoperand : AsmOperandClass
-{
+def uimm16_asmoperand : AsmOperandClass {
   let Name = "UImm16";
   let PredicateMethod = "isUImm<16>";
   let RenderMethod = "addImmOperands";
 }
 
-def uimm16 : Operand<i32>
-{
+def uimm16 : Operand<i32> {
   let ParserMatchClass = uimm16_asmoperand;
 }
 
 class A64I_exceptImpl<bits<3> opc, bits<2> ll, string asmop>
   : A64I_exception<opc, 0b000, ll, (outs), (ins uimm16:$UImm16),
-                   !strconcat(asmop, "\t$UImm16"), [], NoItinerary>
-{
+                   !strconcat(asmop, "\t$UImm16"), [], NoItinerary> {
   let isBranch = 1;
   let isTerminator = 1;
 }
@@ -1973,38 +1880,34 @@
 //===----------------------------------------------------------------------===//
 // Contains: FCMP, FCMPE
 
-def fpzero_asmoperand : AsmOperandClass
-{
+def fpzero_asmoperand : AsmOperandClass {
   let Name = "FPZero";
   let ParserMethod = "ParseFPImmOperand";
 }
 
-def fpz32 : Operand<f32>, ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]>
-{
+def fpz32 : Operand<f32>,
+            ComplexPattern<f32, 1, "SelectFPZeroOperand", [fpimm]> {
   let ParserMatchClass = fpzero_asmoperand;
   let PrintMethod = "printFPZeroOperand";
 }
 
-def fpz64 : Operand<f64>, ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]>
-{
+def fpz64 : Operand<f64>,
+            ComplexPattern<f64, 1, "SelectFPZeroOperand", [fpimm]> {
   let ParserMatchClass = fpzero_asmoperand;
   let PrintMethod = "printFPZeroOperand";
 }
 
 multiclass A64I_fpcmpSignal<bits<2> type, bit imm, dag ins, string asmop2,
-                            dag pattern>
-{
+                            dag pattern> {
   def _quiet : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b0, imm, 0b0, 0b0, 0b0},
                           (outs), ins, !strconcat("fcmp\t$Rn, ", asmop2),
-                          [pattern], NoItinerary>
-  {
+                          [pattern], NoItinerary> {
     let Defs = [NZCV];
   }
 
   def _sig : A64I_fpcmp<0b0, 0b0, type, 0b00, {0b1, imm, 0b0, 0b0, 0b0},
                         (outs), ins, !strconcat("fcmpe\t$Rn, ", asmop2),
-                        [], NoItinerary>
-  {
+                        [], NoItinerary> {
     let Defs = [NZCV];
   }
 }
@@ -2016,8 +1919,7 @@
 
 // What would be Rm should be written as 0, but anything is valid for
 // disassembly so we can't set the bits
-let PostEncoderMethod = "fixFCMPImm" in
-{
+let PostEncoderMethod = "fixFCMPImm" in {
   defm FCMPsi : A64I_fpcmpSignal<0b00, 0b1, (ins FPR32:$Rn, fpz32:$Imm), "$Imm",
                               (set NZCV, (A64cmp (f32 FPR32:$Rn), fpz32:$Imm))>;
 
@@ -2036,8 +1938,7 @@
                 (outs),
                 (ins FPR:$Rn, FPR:$Rm, uimm4:$NZCVImm, cond_code_op:$Cond),
                 !strconcat(asmop, "\t$Rn, $Rm, $NZCVImm, $Cond"),
-                [], NoItinerary>
-{
+                [], NoItinerary> {
   let Defs = [NZCV];
 }
 
@@ -2051,8 +1952,7 @@
 //===----------------------------------------------------------------------===//
 // Contains: FCSEL
 
-let Uses = [NZCV] in
-{
+let Uses = [NZCV] in {
   def FCSELsssc : A64I_fpcondsel<0b0, 0b0, 0b00, (outs FPR32:$Rd),
                                  (ins FPR32:$Rn, FPR32:$Rm, cond_code_op:$Cond),
                                  "fcsel\t$Rd, $Rn, $Rm, $Cond",
@@ -2082,8 +1982,7 @@
 // First we do the fairly trivial bunch with uniform "OP s, s" and "OP d, d"
 // syntax. Default to no pattern because most are odd enough not to have one.
 multiclass A64I_fpdp1sizes<bits<6> opcode, string asmstr,
-                           SDPatternOperator opnode = FPNoUnop>
-{
+                           SDPatternOperator opnode = FPNoUnop> {
   def ss : A64I_fpdp1<0b0, 0b0, 0b00, opcode, (outs FPR32:$Rd), (ins FPR32:$Rn),
                      !strconcat(asmstr, "\t$Rd, $Rn"),
                      [(set (f32 FPR32:$Rd), (opnode FPR32:$Rn))],
@@ -2111,8 +2010,7 @@
 // The FCVT instrucitons have different source and destination register-types,
 // but the fields are uniform everywhere a D-register (say) crops up. Package
 // this information in a Record.
-class FCVTRegType<RegisterClass rc, bits<2> fld, ValueType vt>
-{
+class FCVTRegType<RegisterClass rc, bits<2> fld, ValueType vt> {
     RegisterClass Class = rc;
     ValueType VT = vt;
     bit t1 = fld{1};
@@ -2148,8 +2046,7 @@
                       [{ (void)N; return false; }]>;
 
 multiclass A64I_fpdp2sizes<bits<4> opcode, string asmstr,
-                           SDPatternOperator opnode>
-{
+                           SDPatternOperator opnode> {
   def sss : A64I_fpdp2<0b0, 0b0, 0b00, opcode,
                       (outs FPR32:$Rd),
                       (ins FPR32:$Rn, FPR32:$Rm),
@@ -2219,16 +2116,14 @@
 // Contains: FCVTZS, FCVTZU, SCVTF, UCVTF
 
 // #1-#32 allowed, encoded as "64 - <specified imm>
-def fixedpos_asmoperand_i32 : AsmOperandClass
-{
+def fixedpos_asmoperand_i32 : AsmOperandClass {
   let Name = "CVTFixedPos32";
   let RenderMethod = "addCVTFixedPosOperands";
   let PredicateMethod = "isCVTFixedPos<32>";
 }
 
 // Also encoded as "64 - <specified imm>" but #1-#64 allowed.
-def fixedpos_asmoperand_i64 : AsmOperandClass
-{
+def fixedpos_asmoperand_i64 : AsmOperandClass {
   let Name = "CVTFixedPos64";
   let RenderMethod = "addCVTFixedPosOperands";
   let PredicateMethod = "isCVTFixedPos<64>";
@@ -2240,8 +2135,7 @@
 //   + Assembly parsing and decoding depend on integer width
 class cvtfix_i32_op<ValueType FloatVT>
   : Operand<FloatVT>,
-    ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm]>
-{
+    ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<32>", [fpimm]> {
   let ParserMatchClass = fixedpos_asmoperand_i32;
   let DecoderMethod = "DecodeCVT32FixedPosOperand";
   let PrintMethod = "printCVTFixedPosOperand";
@@ -2249,8 +2143,7 @@
 
 class cvtfix_i64_op<ValueType FloatVT>
   : Operand<FloatVT>,
-    ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm]>
-{
+    ComplexPattern<FloatVT, 1, "SelectCVTFixedPosOperand<64>", [fpimm]> {
   let ParserMatchClass = fixedpos_asmoperand_i64;
   let PrintMethod = "printCVTFixedPosOperand";
 }
@@ -2322,17 +2215,24 @@
   : A64I_fpint<sf, 0b0, type, rmode, opcode, (outs DestPR:$Rd), (ins SrcPR:$Rn),
                !strconcat(asmop, "\t$Rd, $Rn"), [], NoItinerary>;
 
-multiclass A64I_fptointRM<bits<2> rmode, bit o2, string asmop>
-{
-  def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0}, GPR32, FPR32, asmop # "s">;
-  def Sxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 0}, GPR64, FPR32, asmop # "s">;
-  def Uws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 1}, GPR32, FPR32, asmop # "u">;
-  def Uxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 1}, GPR64, FPR32, asmop # "u">;
+multiclass A64I_fptointRM<bits<2> rmode, bit o2, string asmop> {
+  def Sws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 0},
+                        GPR32, FPR32, asmop # "s">;
+  def Sxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 0},
+                        GPR64, FPR32, asmop # "s">;
+  def Uws : A64I_fpintI<0b0, 0b00, rmode, {o2, 0, 1},
+                        GPR32, FPR32, asmop # "u">;
+  def Uxs : A64I_fpintI<0b1, 0b00, rmode, {o2, 0, 1},
+                        GPR64, FPR32, asmop # "u">;
 
-  def Swd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 0}, GPR32, FPR64, asmop # "s">;
-  def Sxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 0}, GPR64, FPR64, asmop # "s">;
-  def Uwd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 1}, GPR32, FPR64, asmop # "u">;
-  def Uxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 1}, GPR64, FPR64, asmop # "u">;
+  def Swd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 0},
+                        GPR32, FPR64, asmop # "s">;
+  def Sxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 0},
+                        GPR64, FPR64, asmop # "s">;
+  def Uwd : A64I_fpintI<0b0, 0b01, rmode, {o2, 0, 1},
+                        GPR32, FPR64, asmop # "u">;
+  def Uxd : A64I_fpintI<0b1, 0b01, rmode, {o2, 0, 1},
+                        GPR64, FPR64, asmop # "u">;
 }
 
 defm FCVTN : A64I_fptointRM<0b00, 0b0, "fcvtn">;
@@ -2350,8 +2250,7 @@
 def : Pat<(i32 (fp_to_uint (f64 FPR64:$Rn))), (FCVTZUwd FPR64:$Rn)>;
 def : Pat<(i64 (fp_to_uint (f64 FPR64:$Rn))), (FCVTZUxd FPR64:$Rn)>;
 
-multiclass A64I_inttofp<bit o0, string asmop>
-{
+multiclass A64I_inttofp<bit o0, string asmop> {
   def CVTFsw : A64I_fpintI<0b0, 0b00, 0b00, {0, 1, o0}, FPR32, GPR32, asmop>;
   def CVTFsx : A64I_fpintI<0b1, 0b00, 0b00, {0, 1, o0}, FPR32, GPR64, asmop>;
   def CVTFdw : A64I_fpintI<0b0, 0b01, 0b00, {0, 1, o0}, FPR64, GPR32, asmop>;
@@ -2380,20 +2279,17 @@
 def : Pat<(i64 (bitconvert (f64 FPR64:$Rn))), (FMOVxd FPR64:$Rn)>;
 def : Pat<(f64 (bitconvert (i64 GPR64:$Rn))), (FMOVdx GPR64:$Rn)>;
 
-def lane1_asmoperand : AsmOperandClass
-{
+def lane1_asmoperand : AsmOperandClass {
   let Name = "Lane1";
   let RenderMethod = "addImmOperands";
 }
 
-def lane1 : Operand<i32>
-{
+def lane1 : Operand<i32> {
   let ParserMatchClass = lane1_asmoperand;
   let PrintMethod = "printBareImmOperand";
 }
 
-let DecoderMethod =  "DecodeFMOVLaneInstruction" in
-{
+let DecoderMethod =  "DecodeFMOVLaneInstruction" in {
   def FMOVxv : A64I_fpint<0b1, 0b0, 0b10, 0b01, 0b110,
                           (outs GPR64:$Rd), (ins VPR128:$Rn, lane1:$Lane),
                           "fmov\t$Rd, $Rn.d[$Lane]", [], NoItinerary>;
@@ -2414,8 +2310,7 @@
 //===----------------------------------------------------------------------===//
 // Contains: FMOV
 
-def fpimm_asmoperand : AsmOperandClass
-{
+def fpimm_asmoperand : AsmOperandClass {
   let Name = "FMOVImm";
   let ParserMethod = "ParseFPImmOperand";
 }
@@ -2430,8 +2325,7 @@
 class fmov_operand<ValueType FT>
   : Operand<i32>,
     PatLeaf<(FT fpimm), [{ return A64Imms::isFPImm(N->getValueAPF()); }],
-            SDXF_fpimm>
-{
+            SDXF_fpimm> {
   let PrintMethod = "printFPImmOperand";
   let ParserMatchClass = fpimm_asmoperand;
 }
@@ -2456,14 +2350,12 @@
 //===----------------------------------------------------------------------===//
 // Contains: LDR, LDRSW, PRFM
 
-def ldrlit_label_asmoperand : AsmOperandClass
-{
+def ldrlit_label_asmoperand : AsmOperandClass {
   let Name = "LoadLitLabel";
   let RenderMethod = "addLabelOperands<19, 4>";
 }
 
-def ldrlit_label : Operand<i64>
-{
+def ldrlit_label : Operand<i64> {
   let EncoderMethod = "getLoadLitLabelOpValue";
 
   // This label is a 19-bit offset from PC, scaled by the instruction-width: 4.
@@ -2475,18 +2367,15 @@
 // Various instructions take an immediate value (which can always be used),
 // where some numbers have a symbolic name to make things easier. These operands
 // and the associated functions abstract away the differences.
-multiclass namedimm<string prefix, string mapper>
-{
-  def _asmoperand : AsmOperandClass
-  {
+multiclass namedimm<string prefix, string mapper> {
+  def _asmoperand : AsmOperandClass {
     let Name = "NamedImm" # prefix;
     let PredicateMethod = "isUImm";
     let RenderMethod = "addImmOperands";
     let ParserMethod = "ParseNamedImmOperand<" # mapper # ">";
   }
 
-  def _op : Operand<i32>
-  {
+  def _op : Operand<i32> {
     let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
     let PrintMethod = "printNamedImmOperand<" # mapper # ">";
     let DecoderMethod = "DecodeNamedImmOperand<" # mapper # ">";
@@ -2500,8 +2389,7 @@
    : A64I_LDRlit<opc, v, (outs OutReg:$Rt), (ins ldrlit_label:$Imm19),
                  "ldr\t$Rt, $Imm19", patterns, NoItinerary>;
 
-let mayLoad = 1 in
-{
+let mayLoad = 1 in {
   def LDRw_lit : A64I_LDRlitSimple<0b00, 0b0, GPR32>;
   def LDRx_lit : A64I_LDRlitSimple<0b01, 0b0, GPR64>;
 }
@@ -2511,8 +2399,7 @@
 def LDRd_lit  : A64I_LDRlitSimple<0b01, 0b1, FPR64,
                               [(set (f64 FPR64:$Rt), (load constpool:$Imm19))]>;
 
-let mayLoad = 1 in
-{
+let mayLoad = 1 in {
   def LDRq_lit : A64I_LDRlitSimple<0b10, 0b1, FPR128>;
 
 
@@ -2548,16 +2435,14 @@
 
 // This operand parses a GPR64xsp register, followed by an optional immediate
 // #0.
-def GPR64xsp0_asmoperand : AsmOperandClass
-{
+def GPR64xsp0_asmoperand : AsmOperandClass {
   let Name = "GPR64xsp0";
   let PredicateMethod = "isWrappedReg";
   let RenderMethod = "addRegOperands";
   let ParserMethod = "ParseLSXAddressOperand";
 }
 
-def GPR64xsp0 : RegisterOperand<GPR64xsp>
-{
+def GPR64xsp0 : RegisterOperand<GPR64xsp> {
   let ParserMatchClass = GPR64xsp0_asmoperand;
 }
 
@@ -2568,7 +2453,7 @@
 class A64I_SRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
                         dag ins, list<dag> pat,
                         InstrItinClass itin> :
-	    A64I_LDSTex_stn <size,
+       A64I_LDSTex_stn <size,
                         opcode{2}, 0, opcode{1}, opcode{0},
                         outs, ins,
                         !strconcat(asm, "\t$Rs, $Rt, [$Rn]"),
@@ -2605,7 +2490,7 @@
 class A64I_LRexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
                         dag ins, list<dag> pat,
                         InstrItinClass itin> :
-	    A64I_LDSTex_tn <size,
+        A64I_LDSTex_tn <size,
                         opcode{2}, 1, opcode{1}, opcode{0},
                         outs, ins,
                         !strconcat(asm, "\t$Rt, [$Rn]"),
@@ -2658,7 +2543,7 @@
 class A64I_SLexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
                         dag ins, list<dag> pat,
                         InstrItinClass itin> :
-	    A64I_LDSTex_tn <size,
+        A64I_LDSTex_tn <size,
                         opcode{2}, 0, opcode{1}, opcode{0},
                         outs, ins,
                         !strconcat(asm, "\t$Rt, [$Rn]"),
@@ -2708,12 +2593,11 @@
 class A64I_SPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
                         dag ins, list<dag> pat,
                         InstrItinClass itin> :
-	    A64I_LDSTex_stt2n <size,
+     A64I_LDSTex_stt2n <size,
                         opcode{2}, 0, opcode{1}, opcode{0},
                         outs, ins,
                         !strconcat(asm, "\t$Rs, $Rt, $Rt2, [$Rn]"),
-                        pat, itin>
-{
+                        pat, itin> {
   let mayStore = 1;
 }
 
@@ -2740,7 +2624,7 @@
 class A64I_LPexs_impl<bits<2> size, bits<3> opcode, string asm, dag outs,
                         dag ins, list<dag> pat,
                         InstrItinClass itin> :
-	    A64I_LDSTex_tt2n <size,
+      A64I_LDSTex_tt2n <size,
                         opcode{2}, 1, opcode{1}, opcode{0},
                         outs, ins,
                         !strconcat(asm, "\t$Rt, $Rt2, [$Rn]"),
@@ -2828,10 +2712,8 @@
 // 1.1 Unsigned 12-bit immediate operands
 //===-------------------------------
 
-multiclass offsets_uimm12<int MemSize, string prefix>
-{
-  def uimm12_asmoperand : AsmOperandClass
-  {
+multiclass offsets_uimm12<int MemSize, string prefix> {
+  def uimm12_asmoperand : AsmOperandClass {
     let Name = "OffsetUImm12_" # MemSize;
     let PredicateMethod = "isOffsetUImm12<" # MemSize # ">";
     let RenderMethod = "addOffsetUImm12Operands<" # MemSize # ">";
@@ -2840,8 +2722,7 @@
   // Pattern is really no more than an ImmLeaf, but predicated on MemSize which
   // complicates things beyond TableGen's ken.
   def uimm12 : Operand<i64>,
-               ComplexPattern<i64, 1, "SelectOffsetUImm12<" # MemSize # ">">
-  {
+               ComplexPattern<i64, 1, "SelectOffsetUImm12<" # MemSize # ">"> {
     let ParserMatchClass
       = !cast<AsmOperandClass>(prefix # uimm12_asmoperand);
 
@@ -2866,8 +2747,7 @@
   return CurDAG->getTargetConstant(N->getZExtValue() & 0x1ff, MVT::i32);
 }]>;
 
-def simm9_asmoperand : AsmOperandClass
-{
+def simm9_asmoperand : AsmOperandClass {
   let Name = "SImm9";
   let PredicateMethod = "isSImm<9>";
   let RenderMethod = "addSImmOperands<9>";
@@ -2875,8 +2755,7 @@
 
 def simm9 : Operand<i64>,
             ImmLeaf<i64, [{ return Imm >= -0x100 && Imm <= 0xff; }],
-            SDXF_simm9>
-{
+            SDXF_simm9> {
   let PrintMethod = "printOffsetSImm9Operand";
   let ParserMatchClass = simm9_asmoperand;
 }
@@ -2899,17 +2778,14 @@
 // which will need separate instructions for LLVM type-consistency. We'll also
 // need separate operands, of course.
 multiclass regexts<int MemSize, int RmSize, RegisterClass GPR,
-                   string Rm, string prefix>
-{
-  def regext_asmoperand : AsmOperandClass
-  {
+                   string Rm, string prefix> {
+  def regext_asmoperand : AsmOperandClass {
     let Name = "AddrRegExtend_" # MemSize # "_" #  Rm;
     let PredicateMethod = "isAddrRegExtend<" # MemSize # "," # RmSize # ">";
     let RenderMethod = "addAddrRegExtendOperands<" # MemSize # ">";
   }
 
-  def regext : Operand<i64>
-  {
+  def regext : Operand<i64> {
     let PrintMethod
       = "printAddrRegExtendOperand<" # MemSize # ", " # RmSize # ">";
 
@@ -2919,8 +2795,7 @@
   }
 }
 
-multiclass regexts_wx<int MemSize, string prefix>
-{
+multiclass regexts_wx<int MemSize, string prefix> {
   // Rm is an X-register if LSL or SXTX are specified as the shift.
   defm Xm_ : regexts<MemSize, 64, GPR64, "Xm", prefix # "Xm_">;
 
@@ -2959,8 +2834,7 @@
 // This class covers the basic unsigned or irrelevantly-signed loads and stores,
 // to general-purpose and floating-point registers.
 
-class AddrParams<string prefix>
-{
+class AddrParams<string prefix> {
   Operand uimm12 = !cast<Operand>(prefix # "_uimm12");
 
   Operand regextWm = !cast<Operand>(prefix # "_Wm_regext");
@@ -2975,14 +2849,12 @@
 
 multiclass A64I_LDRSTR_unsigned<string prefix, bits<2> size, bit v,
                                 bit high_opc, string asmsuffix,
-                                RegisterClass GPR, AddrParams params>
-{
+                                RegisterClass GPR, AddrParams params> {
   // Unsigned immediate
   def _STR : A64I_LSunsigimm<size, v, {high_opc, 0b0},
                      (outs), (ins GPR:$Rt, GPR64xsp:$Rn, params.uimm12:$UImm12),
                      "str" # asmsuffix # "\t$Rt, [$Rn, $UImm12]",
-                     [], NoItinerary>
-  {
+                     [], NoItinerary> {
     let mayStore = 1;
   }
   def : InstAlias<"str" # asmsuffix # " $Rt, [$Rn]",
@@ -2991,16 +2863,14 @@
   def _LDR : A64I_LSunsigimm<size, v, {high_opc, 0b1},
                       (outs GPR:$Rt), (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
                       "ldr" #  asmsuffix # "\t$Rt, [$Rn, $UImm12]",
-                      [], NoItinerary>
-  {
+                      [], NoItinerary> {
     let mayLoad = 1;
   }
   def : InstAlias<"ldr" # asmsuffix # " $Rt, [$Rn]",
                 (!cast<Instruction>(prefix # "_LDR") GPR:$Rt, GPR64xsp:$Rn, 0)>;
 
   // Register offset (four of these: load/store and Wm/Xm).
-  let mayLoad = 1 in
-  {
+  let mayLoad = 1 in {
     def _Wm_RegOffset_LDR : A64I_LSregoff<size, v, {high_opc, 0b1}, 0b0,
                             (outs GPR:$Rt),
                             (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
@@ -3017,8 +2887,7 @@
         (!cast<Instruction>(prefix # "_Xm_RegOffset_LDR") GPR:$Rt, GPR64xsp:$Rn,
                                                           GPR64:$Rm, 2)>;
 
-  let mayStore = 1 in
-  {
+  let mayStore = 1 in {
     def _Wm_RegOffset_STR : A64I_LSregoff<size, v, {high_opc, 0b0}, 0b0,
                                   (outs), (ins GPR:$Rt, GPR64xsp:$Rn, GPR32:$Rm,
                                                params.regextWm:$Ext),
@@ -3039,8 +2908,7 @@
   def _STUR : A64I_LSunalimm<size, v, {high_opc, 0b0},
                              (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
                              "stur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
-                             [], NoItinerary>
-  {
+                             [], NoItinerary> {
     let mayStore = 1;
   }
   def : InstAlias<"stur" # asmsuffix # " $Rt, [$Rn]",
@@ -3049,8 +2917,7 @@
   def _LDUR : A64I_LSunalimm<size, v, {high_opc, 0b1},
                              (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
                              "ldur" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
-                             [], NoItinerary>
-  {
+                             [], NoItinerary> {
     let mayLoad = 1;
   }
   def : InstAlias<"ldur" # asmsuffix # " $Rt, [$Rn]",
@@ -3061,8 +2928,7 @@
                                (outs GPR64xsp:$Rn_wb),
                                (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
                                "str" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
-                               [], NoItinerary>
-  {
+                               [], NoItinerary> {
     let Constraints = "$Rn = $Rn_wb";
     let mayStore = 1;
 
@@ -3074,8 +2940,7 @@
                                     (outs GPR:$Rt, GPR64xsp:$Rn_wb),
                                     (ins GPR64xsp:$Rn, simm9:$SImm9),
                                     "ldr" # asmsuffix # "\t$Rt, [$Rn], $SImm9",
-                                    [], NoItinerary>
-  {
+                                    [], NoItinerary> {
     let mayLoad = 1;
     let Constraints = "$Rn = $Rn_wb";
     let DecoderMethod = "DecodeSingleIndexedInstruction";
@@ -3086,8 +2951,7 @@
                                (outs GPR64xsp:$Rn_wb),
                                (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
                                "str" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
-                               [], NoItinerary>
-  {
+                               [], NoItinerary> {
     let Constraints = "$Rn = $Rn_wb";
     let mayStore = 1;
 
@@ -3099,8 +2963,7 @@
                                     (outs GPR:$Rt, GPR64xsp:$Rn_wb),
                                     (ins GPR64xsp:$Rn, simm9:$SImm9),
                                     "ldr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]!",
-                                    [], NoItinerary>
-  {
+                                    [], NoItinerary> {
     let mayLoad = 1;
     let Constraints = "$Rn = $Rn_wb";
     let DecoderMethod = "DecodeSingleIndexedInstruction";
@@ -3141,7 +3004,8 @@
   : A64I_LDRSTR_unsigned<"LSFP64", 0b11, 0b1, 0b0, "", FPR64, dword_addrparams>;
 // STR/LDR to/from a Q register
 defm LSFP128
-  : A64I_LDRSTR_unsigned<"LSFP128", 0b00, 0b1, 0b1, "", FPR128, qword_addrparams>;
+  : A64I_LDRSTR_unsigned<"LSFP128", 0b00, 0b1, 0b1, "", FPR128,
+                         qword_addrparams>;
 
 //===------------------------------
 // 2.3 Signed loads
@@ -3151,15 +3015,13 @@
 // so it's worth factoring out. Signed word loads don't fit because there is no
 // W version.
 multiclass A64I_LDR_signed<bits<2> size, string asmopcode, AddrParams params,
-                           string prefix>
-{
+                           string prefix> {
   // Unsigned offset
   def w : A64I_LSunsigimm<size, 0b0, 0b11,
                           (outs GPR32:$Rt),
                           (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
                           "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
-                          [], NoItinerary>
-  {
+                          [], NoItinerary> {
     let mayLoad = 1;
   }
   def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
@@ -3169,16 +3031,14 @@
                           (outs GPR64:$Rt),
                           (ins GPR64xsp:$Rn, params.uimm12:$UImm12),
                           "ldrs" # asmopcode # "\t$Rt, [$Rn, $UImm12]",
-                          [], NoItinerary>
-  {
+                          [], NoItinerary> {
     let mayLoad = 1;
   }
   def : InstAlias<"ldrs" # asmopcode # " $Rt, [$Rn]",
                   (!cast<Instruction>(prefix # x) GPR64:$Rt, GPR64xsp:$Rn, 0)>;
 
   // Register offset
-  let mayLoad = 1 in
-  {
+  let mayLoad = 1 in {
     def w_Wm_RegOffset : A64I_LSregoff<size, 0b0, 0b11, 0b0,
                             (outs GPR32:$Rt),
                             (ins GPR64xsp:$Rn, GPR32:$Rm, params.regextWm:$Ext),
@@ -3212,8 +3072,7 @@
                                                        GPR64:$Rm, 2)>;
 
 
-  let mayLoad = 1 in
-  {
+  let mayLoad = 1 in {
     // Unaligned offset
     def w_U : A64I_LSunalimm<size, 0b0, 0b11,
                              (outs GPR32:$Rt),
@@ -3233,8 +3092,7 @@
                                  (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
                                  (ins GPR64xsp:$Rn, simm9:$SImm9),
                                  "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
-                                 [], NoItinerary>
-    {
+                                 [], NoItinerary> {
       let Constraints = "$Rn = $Rn_wb";
       let DecoderMethod = "DecodeSingleIndexedInstruction";
     }
@@ -3243,8 +3101,7 @@
                                    (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
                                    (ins GPR64xsp:$Rn, simm9:$SImm9),
                                    "ldrs" # asmopcode # "\t$Rt, [$Rn], $SImm9",
-                                   [], NoItinerary>
-    {
+                                   [], NoItinerary> {
       let Constraints = "$Rn = $Rn_wb";
       let DecoderMethod = "DecodeSingleIndexedInstruction";
     }
@@ -3254,8 +3111,7 @@
                                  (outs GPR32:$Rt, GPR64xsp:$Rn_wb),
                                  (ins GPR64xsp:$Rn, simm9:$SImm9),
                                  "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
-                                 [], NoItinerary>
-    {
+                                 [], NoItinerary> {
       let Constraints = "$Rn = $Rn_wb";
       let DecoderMethod = "DecodeSingleIndexedInstruction";
     }
@@ -3264,8 +3120,7 @@
                                  (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
                                  (ins GPR64xsp:$Rn, simm9:$SImm9),
                                  "ldrs" # asmopcode # "\t$Rt, [$Rn, $SImm9]!",
-                                 [], NoItinerary>
-    {
+                                 [], NoItinerary> {
       let Constraints = "$Rn = $Rn_wb";
       let DecoderMethod = "DecodeSingleIndexedInstruction";
     }
@@ -3283,14 +3138,12 @@
                     (outs GPR64:$Rt),
                     (ins GPR64xsp:$Rn, word_uimm12:$UImm12),
                     "ldrsw\t$Rt, [$Rn, $UImm12]",
-                    [], NoItinerary>
-{
+                    [], NoItinerary> {
   let mayLoad = 1;
 }
 def : InstAlias<"ldrsw $Rt, [$Rn]", (LDRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
 
-let mayLoad = 1 in
-{
+let mayLoad = 1 in {
   def LDRSWx_Wm_RegOffset : A64I_LSregoff<0b10, 0b0, 0b10, 0b0,
                              (outs GPR64:$Rt),
                              (ins GPR64xsp:$Rn, GPR32:$Rm, word_Wm_regext:$Ext),
@@ -3312,8 +3165,7 @@
                     (outs GPR64:$Rt),
                     (ins GPR64xsp:$Rn, simm9:$SImm9),
                     "ldursw\t$Rt, [$Rn, $SImm9]",
-                    [], NoItinerary>
-{
+                    [], NoItinerary> {
   let mayLoad = 1;
 }
 def : InstAlias<"ldursw $Rt, [$Rn]", (LDURSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
@@ -3323,8 +3175,7 @@
                     (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
                     (ins GPR64xsp:$Rn, simm9:$SImm9),
                     "ldrsw\t$Rt, [$Rn], $SImm9",
-                    [], NoItinerary>
-{
+                    [], NoItinerary> {
   let mayLoad = 1;
   let Constraints = "$Rn = $Rn_wb";
   let DecoderMethod = "DecodeSingleIndexedInstruction";
@@ -3334,8 +3185,7 @@
                                  (outs GPR64:$Rt, GPR64xsp:$Rn_wb),
                                  (ins GPR64xsp:$Rn, simm9:$SImm9),
                                  "ldrsw\t$Rt, [$Rn, $SImm9]!",
-                                 [], NoItinerary>
-{
+                                 [], NoItinerary> {
   let mayLoad = 1;
   let Constraints = "$Rn = $Rn_wb";
   let DecoderMethod = "DecodeSingleIndexedInstruction";
@@ -3348,15 +3198,13 @@
 def PRFM : A64I_LSunsigimm<0b11, 0b0, 0b10, (outs),
                  (ins prefetch_op:$Rt, GPR64xsp:$Rn, dword_uimm12:$UImm12),
                  "prfm\t$Rt, [$Rn, $UImm12]",
-                 [], NoItinerary>
-{
+                 [], NoItinerary> {
   let mayLoad = 1;
 }
 def : InstAlias<"prfm $Rt, [$Rn]",
                 (PRFM prefetch_op:$Rt, GPR64xsp:$Rn, 0)>;
 
-let mayLoad = 1 in
-{
+let mayLoad = 1 in {
   def PRFM_Wm_RegOffset : A64I_LSregoff<0b11, 0b0, 0b10, 0b0, (outs),
                                         (ins prefetch_op:$Rt, GPR64xsp:$Rn,
                                              GPR32:$Rm, dword_Wm_regext:$Ext),
@@ -3377,8 +3225,7 @@
 def PRFUM : A64I_LSunalimm<0b11, 0b0, 0b10, (outs),
                          (ins prefetch_op:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
                          "prfum\t$Rt, [$Rn, $SImm9]",
-                         [], NoItinerary>
-{
+                         [], NoItinerary> {
   let mayLoad = 1;
 }
 def : InstAlias<"prfum $Rt, [$Rn]",
@@ -3394,13 +3241,11 @@
 // section to avoid instantiation of "ldtr d0, [sp]" etc.
 
 multiclass A64I_LDTRSTTR<bits<2> size, string asmsuffix, RegisterClass GPR,
-                         string prefix>
-{
+                         string prefix> {
   def _UnPriv_STR : A64I_LSunpriv<size, 0b0, 0b00,
                               (outs), (ins GPR:$Rt, GPR64xsp:$Rn, simm9:$SImm9),
                               "sttr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
-                              [], NoItinerary>
-  {
+                              [], NoItinerary> {
     let mayStore = 1;
   }
 
@@ -3410,8 +3255,7 @@
   def _UnPriv_LDR : A64I_LSunpriv<size, 0b0, 0b01,
                                (outs GPR:$Rt), (ins GPR64xsp:$Rn, simm9:$SImm9),
                                "ldtr" # asmsuffix # "\t$Rt, [$Rn, $SImm9]",
-                               [], NoItinerary>
-  {
+                               [], NoItinerary> {
     let mayLoad = 1;
   }
 
@@ -3434,10 +3278,8 @@
 
 // Now a class for the signed instructions that can go to either 32 or 64
 // bits...
-multiclass A64I_LDTR_signed<bits<2> size, string asmopcode, string prefix>
-{
-  let mayLoad = 1 in
-  {
+multiclass A64I_LDTR_signed<bits<2> size, string asmopcode, string prefix> {
+  let mayLoad = 1 in {
     def w : A64I_LSunpriv<size, 0b0, 0b11,
                           (outs GPR32:$Rt),
                           (ins GPR64xsp:$Rn, simm9:$SImm9),
@@ -3469,8 +3311,7 @@
                             (outs GPR64:$Rt),
                             (ins GPR64xsp:$Rn, simm9:$SImm9),
                             "ldtrsw\t$Rt, [$Rn, $SImm9]",
-                            [], NoItinerary>
-{
+                            [], NoItinerary> {
   let mayLoad = 1;
 }
 def : InstAlias<"ldtrsw $Rt, [$Rn]", (LDTRSWx GPR64:$Rt, GPR64xsp:$Rn, 0)>;
@@ -3507,20 +3348,17 @@
 // Operands for each access size. This multiclass takes care of instantiating
 // the correct template functions in the rest of the backend.
 
-multiclass offsets_simm7<string MemSize, string prefix>
-{
+multiclass offsets_simm7<string MemSize, string prefix> {
   // The bare signed 7-bit immediate is used in post-indexed instructions, but
   // because of the scaling performed a generic "simm7" operand isn't
   // appropriate here either.
-  def simm7_asmoperand : AsmOperandClass
-  {
+  def simm7_asmoperand : AsmOperandClass {
     let Name = "SImm7_Scaled" # MemSize;
     let PredicateMethod = "isSImm7Scaled<" # MemSize # ">";
     let RenderMethod = "addSImm7ScaledOperands<" # MemSize # ">";
   }
 
-  def simm7 : Operand<i64>
-  {
+  def simm7 : Operand<i64> {
     let PrintMethod = "printSImm7ScaledOperand<" # MemSize # ">";
     let ParserMatchClass = !cast<AsmOperandClass>(prefix # "simm7_asmoperand");
   }
@@ -3531,12 +3369,10 @@
 defm qword_ : offsets_simm7<"16", "qword_">;
 
 multiclass A64I_LSPsimple<bits<2> opc, bit v, RegisterClass SomeReg,
-                          Operand simm7, string prefix>
-{
+                          Operand simm7, string prefix> {
   def _STR : A64I_LSPoffset<opc, v, 0b0, (outs),
                     (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
-                    "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>
-  {
+                    "stp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
     let mayStore = 1;
     let DecoderMethod = "DecodeLDSTPairInstruction";
   }
@@ -3547,8 +3383,7 @@
   def _LDR : A64I_LSPoffset<opc, v, 0b1,
                             (outs SomeReg:$Rt, SomeReg:$Rt2),
                             (ins GPR64xsp:$Rn, simm7:$SImm7),
-                            "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>
-  {
+                            "ldp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
     let mayLoad = 1;
     let DecoderMethod = "DecodeLDSTPairInstruction";
   }
@@ -3562,8 +3397,7 @@
                                     GPR64xsp:$Rn,
                                     simm7:$SImm7),
                                "stp\t$Rt, $Rt2, [$Rn], $SImm7",
-                               [], NoItinerary>
-  {
+                               [], NoItinerary> {
     let mayStore = 1;
     let Constraints = "$Rn = $Rn_wb";
 
@@ -3575,8 +3409,7 @@
                         (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
                         (ins GPR64xsp:$Rn, simm7:$SImm7),
                         "ldp\t$Rt, $Rt2, [$Rn], $SImm7",
-                        [], NoItinerary>
-  {
+                        [], NoItinerary> {
     let mayLoad = 1;
     let Constraints = "$Rn = $Rn_wb";
     let DecoderMethod = "DecodeLDSTPairInstruction";
@@ -3585,8 +3418,7 @@
   def _PreInd_STR : A64I_LSPpreind<opc, v, 0b0, (outs GPR64xsp:$Rn_wb),
                     (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
                     "stp\t$Rt, $Rt2, [$Rn, $SImm7]!",
-                    [], NoItinerary>
-  {
+                    [], NoItinerary> {
     let mayStore = 1;
     let Constraints = "$Rn = $Rn_wb";
     let DecoderMethod = "DecodeLDSTPairInstruction";
@@ -3596,8 +3428,7 @@
                               (outs SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn_wb),
                               (ins GPR64xsp:$Rn, simm7:$SImm7),
                               "ldp\t$Rt, $Rt2, [$Rn, $SImm7]!",
-                              [], NoItinerary>
-  {
+                              [], NoItinerary> {
     let mayLoad = 1;
     let Constraints = "$Rn = $Rn_wb";
     let DecoderMethod = "DecodeLDSTPairInstruction";
@@ -3605,8 +3436,7 @@
 
   def _NonTemp_STR : A64I_LSPnontemp<opc, v, 0b0, (outs),
                     (ins SomeReg:$Rt, SomeReg:$Rt2, GPR64xsp:$Rn, simm7:$SImm7),
-                    "stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>
-  {
+                    "stnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
     let mayStore = 1;
     let DecoderMethod = "DecodeLDSTPairInstruction";
   }
@@ -3617,8 +3447,7 @@
   def _NonTemp_LDR : A64I_LSPnontemp<opc, v, 0b1,
                             (outs SomeReg:$Rt, SomeReg:$Rt2),
                             (ins GPR64xsp:$Rn, simm7:$SImm7),
-                            "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>
-  {
+                            "ldnp\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
     let mayLoad = 1;
     let DecoderMethod = "DecodeLDSTPairInstruction";
   }
@@ -3633,14 +3462,14 @@
 defm LSPair64 : A64I_LSPsimple<0b10, 0b0, GPR64, dword_simm7, "LSPair64">;
 defm LSFPPair32 : A64I_LSPsimple<0b00, 0b1, FPR32, word_simm7, "LSFPPair32">;
 defm LSFPPair64 : A64I_LSPsimple<0b01, 0b1, FPR64,  dword_simm7, "LSFPPair64">;
-defm LSFPPair128 : A64I_LSPsimple<0b10, 0b1, FPR128, qword_simm7, "LSFPPair128">;
+defm LSFPPair128 : A64I_LSPsimple<0b10, 0b1, FPR128, qword_simm7,
+                                  "LSFPPair128">;
 
 
 def LDPSWx : A64I_LSPoffset<0b01, 0b0, 0b1,
                            (outs GPR64:$Rt, GPR64:$Rt2),
                            (ins GPR64xsp:$Rn, word_simm7:$SImm7),
-                           "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary>
-{
+                           "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]", [], NoItinerary> {
   let mayLoad = 1;
   let DecoderMethod = "DecodeLDSTPairInstruction";
 }
@@ -3651,8 +3480,7 @@
                                   (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
                                   (ins GPR64xsp:$Rn, word_simm7:$SImm7),
                                   "ldpsw\t$Rt, $Rt2, [$Rn], $SImm7",
-                                  [], NoItinerary>
-{
+                                  [], NoItinerary> {
   let mayLoad = 1;
   let Constraints = "$Rn = $Rn_wb";
   let DecoderMethod = "DecodeLDSTPairInstruction";
@@ -3662,8 +3490,7 @@
                                    (outs GPR64:$Rt, GPR64:$Rt2, GPR64:$Rn_wb),
                                    (ins GPR64xsp:$Rn, word_simm7:$SImm7),
                                    "ldpsw\t$Rt, $Rt2, [$Rn, $SImm7]!",
-                                   [], NoItinerary>
-{
+                                   [], NoItinerary> {
   let mayLoad = 1;
   let Constraints = "$Rn = $Rn_wb";
   let DecoderMethod = "DecodeLDSTPairInstruction";
@@ -3675,18 +3502,15 @@
 // Contains: AND, ORR, EOR, ANDS, + aliases TST, MOV
 
 multiclass logical_imm_operands<string prefix, string note,
-                                int size, ValueType VT>
-{
-  def _asmoperand : AsmOperandClass
-  {
+                                int size, ValueType VT> {
+  def _asmoperand : AsmOperandClass {
     let Name = "LogicalImm" # note # size;
     let PredicateMethod = "isLogicalImm" # note # "<" # size # ">";
     let RenderMethod = "addLogicalImmOperands<" # size # ">";
   }
 
   def _operand
-        : Operand<VT>, ComplexPattern<VT, 1, "SelectLogicalImm", [imm]>
-  {
+        : Operand<VT>, ComplexPattern<VT, 1, "SelectLogicalImm", [imm]> {
     let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
     let PrintMethod = "printLogicalImmOperand<" # size # ">";
     let DecoderMethod = "DecodeLogicalImmOperand<" # size # ">";
@@ -3704,8 +3528,7 @@
   : logical_imm_operands<"logical_imm64_mov", "MOV", 64, i64>;
 
 
-multiclass A64I_logimmSizes<bits<2> opc, string asmop, SDNode opnode>
-{
+multiclass A64I_logimmSizes<bits<2> opc, string asmop, SDNode opnode> {
   def wwi : A64I_logicalimm<0b0, opc, (outs GPR32wsp:$Rd),
                          (ins GPR32:$Rn, logical_imm32_operand:$Imm),
                          !strconcat(asmop, "\t$Rd, $Rn, $Imm"),
@@ -3725,8 +3548,7 @@
 defm ORR : A64I_logimmSizes<0b01, "orr", or>;
 defm EOR : A64I_logimmSizes<0b10, "eor", xor>;
 
-let Defs = [NZCV] in
-{
+let Defs = [NZCV] in {
   def ANDSwwi : A64I_logicalimm<0b0, 0b11, (outs GPR32:$Rd),
                                 (ins GPR32:$Rn, logical_imm32_operand:$Imm),
                                 "ands\t$Rd, $Rn, $Imm",
@@ -3770,8 +3592,7 @@
 multiclass logical_shifts<string prefix, bit sf, bits<2> opc,
                           bit N, bit commutable,
                           string asmop, SDPatternOperator opfrag, string sty,
-                          RegisterClass GPR, list<Register> defs>
-{
+                          RegisterClass GPR, list<Register> defs> {
   let isCommutable = commutable, Defs = defs in {
   def _lsl : A64I_logicalshift<sf, opc, 0b00, N,
                        (outs GPR:$Rd),
@@ -3825,8 +3646,7 @@
 
 multiclass logical_sizes<string prefix, bits<2> opc, bit N, bit commutable,
                          string asmop, SDPatternOperator opfrag,
-                         list<Register> defs>
-{
+                         list<Register> defs> {
   defm xxx : logical_shifts<prefix # "xxx", 0b1, opc, N,
                             commutable, asmop, opfrag, "i64", GPR64, defs>;
   defm www : logical_shifts<prefix # "www", 0b0, opc, N,
@@ -3857,8 +3677,7 @@
                                   [{ (void)N; return false; }]>,
                           [NZCV]>;
 
-multiclass tst_shifts<string prefix, bit sf, string sty, RegisterClass GPR>
-{
+multiclass tst_shifts<string prefix, bit sf, string sty, RegisterClass GPR> {
   let isCommutable = 1, Rd = 0b11111, Defs = [NZCV] in {
   def _lsl : A64I_logicalshift<sf, 0b11, 0b00, 0b0,
                        (outs),
@@ -3913,8 +3732,7 @@
 defm TSTww : tst_shifts<"TSTww", 0b0, "i32", GPR32>;
 
 
-multiclass mvn_shifts<string prefix, bit sf, string sty, RegisterClass GPR>
-{
+multiclass mvn_shifts<string prefix, bit sf, string sty, RegisterClass GPR> {
   let isCommutable = 0, Rn = 0b11111 in {
   def _lsl : A64I_logicalshift<sf, 0b01, 0b00, 0b1,
                        (outs GPR:$Rd),
@@ -3975,10 +3793,8 @@
 // A wide variety of different relocations are needed for variants of these
 // instructions, so it turns out that we need a different operand for all of
 // them.
-multiclass movw_operands<string prefix, string instname, int width>
-{
-  def _imm_asmoperand : AsmOperandClass
-  {
+multiclass movw_operands<string prefix, string instname, int width> {
+  def _imm_asmoperand : AsmOperandClass {
     let Name = instname # width # "Shifted" # shift;
     let PredicateMethod = "is" # instname # width # "Imm";
     let RenderMethod = "addMoveWideImmOperands";
@@ -3986,8 +3802,7 @@
     let ParserMethod = "ParseImmWithLSLOperand";
   }
 
-  def _imm : Operand<i32>
-  {
+  def _imm : Operand<i32> {
     let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_imm_asmoperand");
     let PrintMethod = "printMoveWideImmOperand";
     let EncoderMethod = "getMoveWideImmOpValue";
@@ -4004,13 +3819,12 @@
 defm movk32 : movw_operands<"movk32", "MOVK", 32>;
 defm movk64 : movw_operands<"movk64", "MOVK", 64>;
 
-multiclass A64I_movwSizes<bits<2> opc, string asmop, dag ins32bit, dag ins64bit>
-{
+multiclass A64I_movwSizes<bits<2> opc, string asmop, dag ins32bit,
+                          dag ins64bit> {
 
   def wii : A64I_movw<0b0, opc, (outs GPR32:$Rd), ins32bit,
                       !strconcat(asmop, "\t$Rd, $FullImm"),
-                      [], NoItinerary>
-  {
+                      [], NoItinerary> {
     bits<18> FullImm;
     let UImm16 = FullImm{15-0};
     let Shift = FullImm{17-16};
@@ -4018,8 +3832,7 @@
 
   def xii : A64I_movw<0b1, opc, (outs GPR64:$Rd), ins64bit,
                       !strconcat(asmop, "\t$Rd, $FullImm"),
-                      [], NoItinerary>
-  {
+                      [], NoItinerary> {
     bits<18> FullImm;
     let UImm16 = FullImm{15-0};
     let Shift = FullImm{17-16};
@@ -4027,8 +3840,7 @@
 }
 
 let isMoveImm = 1, isReMaterializable = 1,
-    isAsCheapAsAMove = 1, neverHasSideEffects = 1 in
-{
+    isAsCheapAsAMove = 1, neverHasSideEffects = 1 in {
   defm MOVN : A64I_movwSizes<0b00, "movn",
                              (ins movn32_imm:$FullImm),
                              (ins movn64_imm:$FullImm)>;
@@ -4051,10 +3863,8 @@
 // And now the "MOV" aliases. These also need their own operands because what
 // they accept is completely different to what the base instructions accept.
 multiclass movalias_operand<string prefix, string basename,
-                            string immpredicate, int width>
-{
-  def _asmoperand : AsmOperandClass
-  {
+                            string immpredicate, int width> {
+  def _asmoperand : AsmOperandClass {
     let Name = basename # width # "MovAlias";
     let PredicateMethod
           = "isMoveWideMovAlias<" # width # ", A64Imms::" # immpredicate # ">";
@@ -4063,8 +3873,7 @@
                                        # "A64Imms::" # immpredicate # ">";
   }
 
-  def _movimm : Operand<i32>
-  {
+  def _movimm : Operand<i32> {
     let ParserMatchClass = !cast<AsmOperandClass>(prefix # "_asmoperand");
 
     let MIOperandInfo = (ops uimm16:$UImm16, imm:$Shift);
@@ -4102,14 +3911,12 @@
   let OperandType = "OPERAND_PCREL";
 }
 
-def adrp_label_asmoperand : AsmOperandClass
-{
+def adrp_label_asmoperand : AsmOperandClass {
   let Name = "AdrpLabel";
   let RenderMethod = "addLabelOperands<21, 4096>";
 }
 
-def adrp_label : Operand<i64>
-{
+def adrp_label : Operand<i64> {
   let EncoderMethod = "getAdrpLabelOpValue";
 
   // This label is a 21-bit offset from PC, scaled by the page-size: 4096.
@@ -4118,8 +3925,7 @@
   let OperandType = "OPERAND_PCREL";
 }
 
-let neverHasSideEffects = 1 in
-{
+let neverHasSideEffects = 1 in {
   def ADRxi : A64I_PCADR<0b0, (outs GPR64:$Rd), (ins adr_label:$Label),
                          "adr\t$Rd, $Label", [], NoItinerary>;
 
@@ -4134,28 +3940,24 @@
 //    + aliases IC, DC, AT, TLBI, NOP, YIELD, WFE, WFI, SEV, SEVL
 
 // Op1 and Op2 fields are sometimes simple 3-bit unsigned immediate values.
-def uimm3_asmoperand : AsmOperandClass
-{
+def uimm3_asmoperand : AsmOperandClass {
   let Name = "UImm3";
   let PredicateMethod = "isUImm<3>";
   let RenderMethod = "addImmOperands";
 }
 
-def uimm3 : Operand<i32>
-{
+def uimm3 : Operand<i32> {
   let ParserMatchClass = uimm3_asmoperand;
 }
 
 // The HINT alias can accept a simple unsigned 7-bit immediate.
-def uimm7_asmoperand : AsmOperandClass
-{
+def uimm7_asmoperand : AsmOperandClass {
   let Name = "UImm7";
   let PredicateMethod = "isUImm<7>";
   let RenderMethod = "addImmOperands";
 }
 
-def uimm7 : Operand<i32>
-{
+def uimm7 : Operand<i32> {
   let ParserMatchClass = uimm7_asmoperand;
 }
 
@@ -4174,8 +3976,8 @@
 //   * There are ~1000 generic names S3_<op1>_<CRn>_<CRm>_<Op2> which have an
 //     implementation-defined effect
 //   * Most registers are shared, but some are read-only or write-only.
-//   * There is a variant of MSR which accepts the same register name (SPSel), but
-//     which would have a different encoding.
+//   * There is a variant of MSR which accepts the same register name (SPSel),
+//     but which would have a different encoding.
 
 // In principle these could be resolved in with more complicated subclasses of
 // NamedImmMapper, however that imposes an overhead on other "named
@@ -4185,21 +3987,18 @@
 // The solution adopted here is to take the MRS/MSR Mappers out of the usual
 // hierarchy (they're not derived from NamedImmMapper) and to add logic for
 // their special situation.
-def mrs_asmoperand : AsmOperandClass
-{
+def mrs_asmoperand : AsmOperandClass {
   let Name = "MRS";
   let ParserMethod = "ParseSysRegOperand";
 }
 
-def mrs_op : Operand<i32>
-{
+def mrs_op : Operand<i32> {
   let ParserMatchClass = mrs_asmoperand;
   let PrintMethod = "printMRSOperand";
   let DecoderMethod = "DecodeMRSOperand";
 }
 
-def msr_asmoperand : AsmOperandClass
-{
+def msr_asmoperand : AsmOperandClass {
   let Name = "MSRWithReg";
 
   // Note that SPSel is valid for both this and the pstate operands, but with
@@ -4209,22 +4008,19 @@
   let ParserMethod = "ParseSysRegOperand";
 }
 
-def msr_op : Operand<i32>
-{
+def msr_op : Operand<i32> {
   let ParserMatchClass = msr_asmoperand;
   let PrintMethod = "printMSROperand";
   let DecoderMethod = "DecodeMSROperand";
 }
 
-def pstate_asmoperand : AsmOperandClass
-{
+def pstate_asmoperand : AsmOperandClass {
   let Name = "MSRPState";
   // See comment above about parser.
   let ParserMethod = "ParseSysRegOperand";
 }
 
-def pstate_op : Operand<i32>
-{
+def pstate_op : Operand<i32> {
   let ParserMatchClass = pstate_asmoperand;
   let PrintMethod = "printNamedImmOperand<A64PState::PStateMapper>";
   let DecoderMethod = "DecodeNamedImmOperand<A64PState::PStateMapper>";
@@ -4232,16 +4028,14 @@
 
 // When <CRn> is specified, an assembler should accept something like "C4", not
 // the usual "#4" immediate.
-def CRx_asmoperand : AsmOperandClass
-{
+def CRx_asmoperand : AsmOperandClass {
   let Name = "CRx";
   let PredicateMethod = "isUImm<4>";
   let RenderMethod = "addImmOperands";
   let ParserMethod = "ParseCRxOperand";
 }
 
-def CRx : Operand<i32>
-{
+def CRx : Operand<i32> {
   let ParserMatchClass = CRx_asmoperand;
   let PrintMethod = "printCRxOperand";
 }
@@ -4251,8 +4045,7 @@
 
 // HINT is straightforward, with a few aliases.
 def HINTi : A64I_system<0b0, (outs), (ins uimm7:$UImm7), "hint\t$UImm7",
-                        [], NoItinerary>
-{
+                        [], NoItinerary> {
   bits<7> UImm7;
   let CRm = UImm7{6-3};
   let Op2 = UImm7{2-0};
@@ -4275,8 +4068,7 @@
 class simple_sys<bits<2> op0, bits<3> op1, bits<4> crn, bits<3> op2,
                  Operand operand, string asmop>
   : A64I_system<0b0, (outs), (ins operand:$CRm), !strconcat(asmop, "\t$CRm"),
-                [], NoItinerary>
-{
+                [], NoItinerary> {
   let Op0 = op0;
   let Op1 = op1;
   let CRn = crn;
@@ -4303,8 +4095,7 @@
                            (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm,
                                 uimm3:$Op2, GPR64:$Rt),
                            "sys\t$Op1, $CRn, $CRm, $Op2, $Rt",
-                           [], NoItinerary>
-{
+                           [], NoItinerary> {
   let Op0 = 0b01;
 }
 
@@ -4316,8 +4107,7 @@
 
 // But many have aliases, which obviously don't fit into
 class SYSalias<dag ins, string asmstring>
-  : A64I_system<0b0, (outs), ins, asmstring, [], NoItinerary>
-{
+  : A64I_system<0b0, (outs), ins, asmstring, [], NoItinerary> {
   let isAsmParserOnly = 1;
 
   bits<14> SysOp;
@@ -4330,8 +4120,7 @@
 
 def ICix : SYSalias<(ins ic_op:$SysOp, GPR64:$Rt), "ic\t$SysOp, $Rt">;
 
-def ICi : SYSalias<(ins ic_op:$SysOp), "ic\t$SysOp">
-{
+def ICi : SYSalias<(ins ic_op:$SysOp), "ic\t$SysOp"> {
   let Rt = 0b11111;
 }
 
@@ -4340,8 +4129,7 @@
 
 def TLBIix : SYSalias<(ins tlbi_op:$SysOp, GPR64:$Rt), "tlbi\t$SysOp, $Rt">;
 
-def TLBIi : SYSalias<(ins tlbi_op:$SysOp), "tlbi\t$SysOp">
-{
+def TLBIi : SYSalias<(ins tlbi_op:$SysOp), "tlbi\t$SysOp"> {
   let Rt = 0b11111;
 }
 
@@ -4349,15 +4137,13 @@
 def SYSLxicci : A64I_system<0b1, (outs GPR64:$Rt),
                             (ins uimm3:$Op1, CRx:$CRn, CRx:$CRm, uimm3:$Op2),
                             "sysl\t$Rt, $Op1, $CRn, $CRm, $Op2",
-                            [], NoItinerary>
-{
+                            [], NoItinerary> {
   let Op0 = 0b01;
 }
 
 // The instructions themselves are rather simple for MSR and MRS.
 def MSRix : A64I_system<0b0, (outs), (ins msr_op:$SysReg, GPR64:$Rt),
-                        "msr\t$SysReg, $Rt", [], NoItinerary>
-{
+                        "msr\t$SysReg, $Rt", [], NoItinerary> {
   bits<16> SysReg;
   let Op0 = SysReg{15-14};
   let Op1 = SysReg{13-11};
@@ -4367,8 +4153,7 @@
 }
 
 def MRSxi : A64I_system<0b1, (outs GPR64:$Rt), (ins mrs_op:$SysReg),
-                        "mrs\t$Rt, $SysReg", [], NoItinerary>
-{
+                        "mrs\t$Rt, $SysReg", [], NoItinerary> {
   bits<16> SysReg;
   let Op0 = SysReg{15-14};
   let Op1 = SysReg{13-11};
@@ -4378,8 +4163,7 @@
 }
 
 def MSRii : A64I_system<0b0, (outs), (ins pstate_op:$PState, uimm4:$CRm),
-                        "msr\t$PState, $CRm", [], NoItinerary>
-{
+                        "msr\t$PState, $CRm", [], NoItinerary> {
   bits<6> PState;
 
   let Op0 = 0b00;
@@ -4396,15 +4180,13 @@
 
 // The bit to test is a simple unsigned 6-bit immediate in the X-register
 // versions.
-def uimm6 : Operand<i64>
-{
+def uimm6 : Operand<i64> {
   let ParserMatchClass = uimm6_asmoperand;
 }
 
 def label_wid14_scal4_asmoperand : label_asmoperand<14, 4>;
 
-def tbimm_target : Operand<OtherVT>
-{
+def tbimm_target : Operand<OtherVT> {
   let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_tstbr>";
 
   // This label is a 14-bit offset from PC, scaled by the instruction-width: 4.
@@ -4422,8 +4204,7 @@
 def tstb64_pat : ComplexPattern<i64, 1, "SelectTSTBOperand<64>">;
 def tstb32_pat : ComplexPattern<i32, 1, "SelectTSTBOperand<32>">;
 
-let isBranch = 1, isTerminator = 1 in
-{
+let isBranch = 1, isTerminator = 1 in {
   def TBZxii : A64I_TBimm<0b0, (outs),
                         (ins GPR64:$Rt, uimm6:$Imm, tbimm_target:$Label),
                         "tbz\t$Rt, $Imm, $Label",
@@ -4448,8 +4229,7 @@
                         "tbz\t$Rt, $Imm, $Label",
                         [(A64br_cc (A64cmp (and GPR32:$Rt, tstb32_pat:$Imm), 0),
                                    A64eq, bb:$Label)],
-                        NoItinerary>
-  {
+                        NoItinerary> {
     let Imm{5} = 0b0;
   }
 
@@ -4458,8 +4238,7 @@
                         "tbnz\t$Rt, $Imm, $Label",
                         [(A64br_cc (A64cmp (and GPR32:$Rt, tstb32_pat:$Imm), 0),
                                    A64ne, bb:$Label)],
-                        NoItinerary>
-  {
+                        NoItinerary> {
     let Imm{5} = 0b0;
   }
 }
@@ -4471,8 +4250,7 @@
 
 def label_wid26_scal4_asmoperand : label_asmoperand<26, 4>;
 
-def bimm_target : Operand<OtherVT>
-{
+def bimm_target : Operand<OtherVT> {
   let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_uncondbr>";
 
   // This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
@@ -4482,8 +4260,7 @@
   let OperandType = "OPERAND_PCREL";
 }
 
-def blimm_target : Operand<i64>
-{
+def blimm_target : Operand<i64> {
   let EncoderMethod = "getLabelOpValue<AArch64::fixup_a64_call>";
 
   // This label is a 26-bit offset from PC, scaled by the instruction-width: 4.
@@ -4499,15 +4276,13 @@
               NoItinerary>;
 
 let isBranch = 1 in {
-  def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target>
-  {
+  def Bimm : A64I_BimmImpl<0b0, "b", [(br bb:$Label)], bimm_target> {
     let isTerminator = 1;
     let isBarrier = 1;
   }
 
   def BLimm : A64I_BimmImpl<0b1, "bl",
-                            [(AArch64Call tglobaladdr:$Label)], blimm_target>
-  {
+                            [(AArch64Call tglobaladdr:$Label)], blimm_target> {
     let isCall = 1;
     let Defs = [X30];
   }
@@ -4526,8 +4301,7 @@
                     dag outs, dag ins, string asmstr, list<dag> patterns,
                     InstrItinClass itin = NoItinerary>
   : A64I_Breg<opc, 0b11111, 0b000000, 0b00000,
-              outs, ins, asmstr, patterns, itin>
-{
+              outs, ins, asmstr, patterns, itin> {
   let isBranch         = 1;
   let isIndirectBranch = 1;
 }
@@ -4538,23 +4312,20 @@
 
 let isBranch = 1 in {
   def BRx : A64I_BregImpl<0b0000,(outs), (ins GPR64:$Rn),
-                          "br\t$Rn", [(brind GPR64:$Rn)]>
-  {
+                          "br\t$Rn", [(brind GPR64:$Rn)]> {
     let isBarrier = 1;
     let isTerminator = 1;
   }
 
   def BLRx : A64I_BregImpl<0b0001, (outs), (ins GPR64:$Rn),
-                           "blr\t$Rn", [(AArch64Call GPR64:$Rn)]>
-  {
+                           "blr\t$Rn", [(AArch64Call GPR64:$Rn)]> {
     let isBarrier = 0;
     let isCall = 1;
     let Defs = [X30];
   }
 
   def RETx : A64I_BregImpl<0b0010, (outs), (ins GPR64:$Rn),
-                           "ret\t$Rn", []>
-  {
+                           "ret\t$Rn", []> {
     let isBarrier = 1;
     let isTerminator = 1;
     let isReturn = 1;
@@ -4563,23 +4334,20 @@
   // Create a separate pseudo-instruction for codegen to use so that we don't
   // flag x30 as used in every function. It'll be restored before the RET by the
   // epilogue if it's legitimately used.
-  def RET : A64PseudoExpand<(outs), (ins), [(A64ret)], (RETx (ops X30))>
-  {
+  def RET : A64PseudoExpand<(outs), (ins), [(A64ret)], (RETx (ops X30))> {
     let isTerminator = 1;
     let isBarrier = 1;
     let isReturn = 1;
   }
 
-  def ERET : A64I_BregImpl<0b0100, (outs), (ins), "eret", []>
-  {
+  def ERET : A64I_BregImpl<0b0100, (outs), (ins), "eret", []> {
     let Rn = 0b11111;
     let isBarrier = 1;
     let isTerminator = 1;
     let isReturn = 1;
   }
 
-  def DRPS : A64I_BregImpl<0b0101, (outs), (ins), "drps", []>
-  {
+  def DRPS : A64I_BregImpl<0b0101, (outs), (ins), "drps", []> {
     let Rn = 0b11111;
     let isBarrier = 1;
   }
@@ -4632,8 +4400,7 @@
 // Tail call handling
 //===----------------------------------------------------------------------===//
 
-let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [XSP] in
-{
+let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, Uses = [XSP] in {
   def TC_RETURNdi
     : PseudoInst<(outs), (ins i64imm:$dst, i32imm:$FPDiff),
                  [(AArch64tcret tglobaladdr:$dst, (i32 timm:$FPDiff))]>;
@@ -4644,8 +4411,7 @@
 }
 
 let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1,
-    Uses = [XSP] in
-{
+    Uses = [XSP] in {
   def TAIL_Bimm : A64PseudoExpand<(outs), (ins bimm_target:$Label), [],
                                   (Bimm bimm_target:$Label)>;
 
@@ -4668,14 +4434,12 @@
 
 def : Pat<(A64threadpointer), (MRSxi 0xde82)>;
 
-def TLSDESCCALL : PseudoInst<(outs), (ins i64imm:$Lbl), []>
-{
+def TLSDESCCALL : PseudoInst<(outs), (ins i64imm:$Lbl), []> {
   let hasSideEffects = 1;
 }
 
 def TLSDESC_BLRx : PseudoInst<(outs), (ins GPR64:$Rn, i64imm:$Var),
-                              [(A64tlsdesc_blr GPR64:$Rn, tglobaltlsaddr:$Var)]>
-{
+                            [(A64tlsdesc_blr GPR64:$Rn, tglobaltlsaddr:$Var)]> {
   let isCall = 1;
   let Defs = [X30];
 }
@@ -4737,8 +4501,7 @@
 
 def CONSTPOOL_ENTRY : PseudoInst<(outs), (ins cpinst_operand:$instid,
                                               cpinst_operand:$cpidx,
-                                              i32imm:$size), []>
-{
+                                              i32imm:$size), []> {
   let neverHasSideEffects = 1;
   let isNotDuplicable = 1;
 }
@@ -4761,8 +4524,7 @@
 def F128CSEL : PseudoInst<(outs FPR128:$Rd),
                           (ins FPR128:$Rn, FPR128:$Rm, cond_code_op:$Cond),
                           [(set FPR128:$Rd, (simple_select (f128 FPR128:$Rn),
-                                                           FPR128:$Rm))]>
-{
+                                                           FPR128:$Rm))]> {
   let Uses = [NZCV];
   let usesCustomInserter = 1;
 }
@@ -4798,8 +4560,7 @@
 //===------------------------------
 
 // First, some simple classes for !foreach and !subst to use:
-class Decls
-{
+class Decls {
   dag pattern;
 }
 
@@ -4876,8 +4637,7 @@
 // quick multiclass here allows reuse.
 multiclass ls_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
                           dag Offset, dag address, RegisterClass TPR,
-                          ValueType sty>
-{
+                          ValueType sty> {
   def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
             (LOAD Base, Offset)>;
 
@@ -4894,8 +4654,7 @@
 multiclass ls_small_pats<Instruction LOAD, Instruction STORE,
                          dag Base, dag Offset,
                          dag address, ValueType sty>
-  : ls_atomic_pats<LOAD, STORE, Base, Offset, address, GPR32, sty>
-{
+  : ls_atomic_pats<LOAD, STORE, Base, Offset, address, GPR32, sty> {
   def : Pat<(!cast<SDNode>(zextload # sty) address), (LOAD Base, Offset)>;
 
   def : Pat<(!cast<SDNode>(extload # sty) address), (LOAD Base, Offset)>;
@@ -4919,8 +4678,7 @@
 
 // Next come patterns for sign-extending loads.
 multiclass load_signed_pats<string T, string U, dag Base, dag Offset,
-                            dag address, ValueType sty>
-{
+                            dag address, ValueType sty> {
   def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
             (!cast<Instruction>("LDRS" # T # "w" # U) Base, Offset)>;
 
@@ -4932,8 +4690,7 @@
 // and finally "natural-width" loads and stores come next.
 multiclass ls_neutral_pats<Instruction LOAD, Instruction STORE, dag Base,
                            dag Offset, dag address, RegisterClass TPR,
-                           ValueType sty>
-{
+                           ValueType sty> {
   def : Pat<(sty (load address)), (LOAD Base, Offset)>;
   def : Pat<(store (sty TPR:$Rt), address), (STORE TPR:$Rt, Base, Offset)>;
 }
@@ -4949,8 +4706,7 @@
 // 2.2. Addressing-mode instantiations
 //===------------------------------
 
-multiclass uimm12_pats<dag address, dag Base, dag Offset>
-{
+multiclass uimm12_pats<dag address, dag Base, dag Offset> {
   defm : ls_small_pats<LS8_LDR, LS8_STR, Base,
                        !foreach(decls.pattern, Offset,
                                 !subst(OFFSET, byte_uimm12, decls.pattern)),
@@ -5041,7 +4797,7 @@
                                   !subst(OFFSET, word_uimm12,
                                   !subst(ALIGN, min_align4, decls.pattern)))),
             (LDRSWx Base, !foreach(decls.pattern, Offset,
-                                   !subst(OFFSET, word_uimm12, decls.pattern)))>;
+                                  !subst(OFFSET, word_uimm12, decls.pattern)))>;
 }
 
 // Straightforward patterns of last resort: a pointer with or without an
@@ -5059,11 +4815,13 @@
 defm : uimm12_pats<(A64WrapperSmall tglobaladdr:$Hi, tglobaladdr:$Lo12, ALIGN),
                    (ADRPxi tglobaladdr:$Hi), (i64 tglobaladdr:$Lo12)>;
 
-defm : uimm12_pats<(A64WrapperSmall tglobaltlsaddr:$Hi, tglobaltlsaddr:$Lo12, ALIGN),
+defm : uimm12_pats<(A64WrapperSmall tglobaltlsaddr:$Hi, tglobaltlsaddr:$Lo12,
+                                    ALIGN),
                    (ADRPxi tglobaltlsaddr:$Hi), (i64 tglobaltlsaddr:$Lo12)>;
 
 // External symbols that make it this far should also get standard relocations.
-defm : uimm12_pats<(A64WrapperSmall texternalsym:$Hi, texternalsym:$Lo12, ALIGN),
+defm : uimm12_pats<(A64WrapperSmall texternalsym:$Hi, texternalsym:$Lo12,
+                                    ALIGN),
                    (ADRPxi texternalsym:$Hi), (i64 texternalsym:$Lo12)>;
 
 
@@ -5078,8 +4836,7 @@
 
 // These can be much simpler than uimm12 because we don't to change the operand
 // type (e.g. LDURB and LDURH take the same operands).
-multiclass simm9_pats<dag address, dag Base, dag Offset>
-{
+multiclass simm9_pats<dag address, dag Base, dag Offset> {
   defm : ls_small_pats<LS8_LDUR, LS8_STUR, Base, Offset, address, i8>;
   defm : ls_small_pats<LS16_LDUR, LS16_STUR, Base, Offset, address, i16>;
 
@@ -5123,8 +4880,7 @@
 // quick multiclass here allows reuse.
 multiclass ro_atomic_pats<Instruction LOAD, Instruction STORE, dag Base,
                           dag Offset, dag Extend, dag address,
-                          RegisterClass TPR, ValueType sty>
-{
+                          RegisterClass TPR, ValueType sty> {
   def : Pat<(!cast<PatFrag>("atomic_load_simple_" # sty) address),
             (LOAD Base, Offset, Extend)>;
 
@@ -5140,8 +4896,7 @@
 multiclass ro_small_pats<Instruction LOAD, Instruction STORE,
                          dag Base, dag Offset, dag Extend,
                          dag address, ValueType sty>
-  : ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, GPR32, sty>
-{
+  : ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, GPR32, sty> {
   def : Pat<(!cast<SDNode>(zextload # sty) address),
             (LOAD Base, Offset, Extend)>;
 
@@ -5168,8 +4923,7 @@
 
 // Next come patterns for sign-extending loads.
 multiclass ro_signed_pats<string T, string Rm, dag Base, dag Offset, dag Extend,
-                          dag address, ValueType sty>
-{
+                          dag address, ValueType sty> {
   def : Pat<(i32 (!cast<SDNode>("sextload" # sty) address)),
             (!cast<Instruction>("LDRS" # T # "w_" # Rm # "_RegOffset")
               Base, Offset, Extend)>;
@@ -5182,21 +4936,20 @@
 // and finally "natural-width" loads and stores come next.
 multiclass ro_neutral_pats<Instruction LOAD, Instruction STORE,
                            dag Base, dag Offset, dag Extend, dag address,
-                           RegisterClass TPR, ValueType sty>
-{
+                           RegisterClass TPR, ValueType sty> {
   def : Pat<(sty (load address)), (LOAD Base, Offset, Extend)>;
   def : Pat<(store (sty TPR:$Rt), address),
             (STORE TPR:$Rt, Base, Offset, Extend)>;
 }
 
 multiclass ro_int_neutral_pats<Instruction LOAD, Instruction STORE,
-                           dag Base, dag Offset, dag Extend, dag address,
-                           RegisterClass TPR, ValueType sty>
+                               dag Base, dag Offset, dag Extend, dag address,
+                               RegisterClass TPR, ValueType sty>
   : ro_neutral_pats<LOAD, STORE, Base, Offset, Extend, address, TPR, sty>,
     ro_atomic_pats<LOAD, STORE, Base, Offset, Extend, address, TPR, sty>;
 
-multiclass regoff_pats<string Rm, dag address, dag Base, dag Offset, dag Extend>
-{
+multiclass regoff_pats<string Rm, dag address, dag Base, dag Offset,
+                       dag Extend> {
   defm : ro_small_pats<!cast<Instruction>("LS8_" # Rm # "_RegOffset_LDR"),
                        !cast<Instruction>("LS8_" # Rm # "_RegOffset_STR"),
                        Base, Offset, Extend,
@@ -5216,19 +4969,21 @@
                                 !subst(SHIFT, imm_eq2, decls.pattern)),
                        i32>;
 
-  defm : ro_int_neutral_pats<!cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
-                         !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
-                         Base, Offset, Extend,
-                         !foreach(decls.pattern, address,
-                                  !subst(SHIFT, imm_eq2, decls.pattern)),
-                         GPR32, i32>;
+  defm : ro_int_neutral_pats<
+                            !cast<Instruction>("LS32_" # Rm # "_RegOffset_LDR"),
+                            !cast<Instruction>("LS32_" # Rm # "_RegOffset_STR"),
+                            Base, Offset, Extend,
+                            !foreach(decls.pattern, address,
+                                     !subst(SHIFT, imm_eq2, decls.pattern)),
+                            GPR32, i32>;
 
-  defm : ro_int_neutral_pats<!cast<Instruction>("LS64_" # Rm # "_RegOffset_LDR"),
-                         !cast<Instruction>("LS64_" # Rm # "_RegOffset_STR"),
-                         Base, Offset, Extend,
-                         !foreach(decls.pattern, address,
-                                  !subst(SHIFT, imm_eq3, decls.pattern)),
-                         GPR64, i64>;
+  defm : ro_int_neutral_pats<
+                            !cast<Instruction>("LS64_" # Rm # "_RegOffset_LDR"),
+                            !cast<Instruction>("LS64_" # Rm # "_RegOffset_STR"),
+                            Base, Offset, Extend,
+                            !foreach(decls.pattern, address,
+                                     !subst(SHIFT, imm_eq3, decls.pattern)),
+                            GPR64, i64>;
 
   defm : ro_neutral_pats<!cast<Instruction>("LSFP16_" # Rm # "_RegOffset_LDR"),
                          !cast<Instruction>("LSFP16_" # Rm # "_RegOffset_STR"),
diff --git a/lib/Target/AArch64/AArch64MachineFunctionInfo.h b/lib/Target/AArch64/AArch64MachineFunctionInfo.h
index bf5cadf..37c1cc5 100644
--- a/lib/Target/AArch64/AArch64MachineFunctionInfo.h
+++ b/lib/Target/AArch64/AArch64MachineFunctionInfo.h
@@ -121,7 +121,9 @@
   void setBytesInStackArgArea (unsigned bytes) { BytesInStackArgArea = bytes;}
 
   unsigned getArgumentStackToRestore() const { return ArgumentStackToRestore; }
-  void setArgumentStackToRestore(unsigned bytes) { ArgumentStackToRestore = bytes; }
+  void setArgumentStackToRestore(unsigned bytes) {
+    ArgumentStackToRestore = bytes;
+  }
 
   unsigned getInitialStackAdjust() const { return InitialStackAdjust; }
   void setInitialStackAdjust(unsigned bytes) { InitialStackAdjust = bytes; }
diff --git a/lib/Target/AArch64/AArch64RegisterInfo.cpp b/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 2481176..da45685 100644
--- a/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -7,7 +7,8 @@
 //
 //===----------------------------------------------------------------------===//
 //
-// This file contains the AArch64 implementation of the TargetRegisterInfo class.
+// This file contains the AArch64 implementation of the TargetRegisterInfo
+// class.
 //
 //===----------------------------------------------------------------------===//
 
@@ -87,7 +88,7 @@
   MachineFunction &MF = *MBB.getParent();
   MachineFrameInfo *MFI = MF.getFrameInfo();
   const AArch64FrameLowering *TFI =
-    static_cast<const AArch64FrameLowering *>(MF.getTarget().getFrameLowering());
+   static_cast<const AArch64FrameLowering *>(MF.getTarget().getFrameLowering());
 
   // In order to work out the base and offset for addressing, the FrameLowering
   // code needs to know (sometimes) whether the instruction is storing/loading a
@@ -202,6 +203,7 @@
 bool
 AArch64RegisterInfo::useFPForScavengingIndex(const MachineFunction &MF) const {
   const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
-  const AArch64FrameLowering *AFI = static_cast<const AArch64FrameLowering*>(TFI);
+  const AArch64FrameLowering *AFI
+    = static_cast<const AArch64FrameLowering*>(TFI);
   return AFI->useFPForAddressing(MF);
 }
diff --git a/lib/Target/AArch64/AArch64RegisterInfo.td b/lib/Target/AArch64/AArch64RegisterInfo.td
index f1f7fd1..3cbbf14 100644
--- a/lib/Target/AArch64/AArch64RegisterInfo.td
+++ b/lib/Target/AArch64/AArch64RegisterInfo.td
@@ -193,13 +193,11 @@
                            (sequence "V%u", 0, 31)>;
 
 // Flags register
-def NZCV : Register<"nzcv">
-{
+def NZCV : Register<"nzcv"> {
   let Namespace = "AArch64";
 }
 
-def FlagClass : RegisterClass<"AArch64", [i32], 32, (add NZCV)>
-{
+def FlagClass : RegisterClass<"AArch64", [i32], 32, (add NZCV)> {
   let CopyCost = -1;
   let isAllocatable = 0;
 }
diff --git a/lib/Target/AArch64/AArch64SelectionDAGInfo.h b/lib/Target/AArch64/AArch64SelectionDAGInfo.h
index 8d3889e..d412ed2 100644
--- a/lib/Target/AArch64/AArch64SelectionDAGInfo.h
+++ b/lib/Target/AArch64/AArch64SelectionDAGInfo.h
@@ -1,4 +1,4 @@
-//===-- AArch64SelectionDAGInfo.h - AArch64 SelectionDAG Info -----*- C++ -*-===//
+//===-- AArch64SelectionDAGInfo.h - AArch64 SelectionDAG Info ---*- C++ -*-===//
 //
 //                     The LLVM Compiler Infrastructure
 //
diff --git a/lib/Target/AArch64/AArch64TargetObjectFile.cpp b/lib/Target/AArch64/AArch64TargetObjectFile.cpp
index 3bb961a..d5c3e89 100644
--- a/lib/Target/AArch64/AArch64TargetObjectFile.cpp
+++ b/lib/Target/AArch64/AArch64TargetObjectFile.cpp
@@ -1,4 +1,4 @@
-//===-- AArch64TargetObjectFile.cpp - AArch64 Object Info ------------------===//
+//===-- AArch64TargetObjectFile.cpp - AArch64 Object Info -----------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
diff --git a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
index bc0f396..e15d135 100644
--- a/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
+++ b/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
@@ -53,7 +53,7 @@
 
   // These are the public interface of the MCTargetAsmParser
   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
-  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 
+  bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc,
                         SmallVectorImpl<MCParsedAsmOperand*> &Operands);
 
@@ -116,7 +116,7 @@
   ParseSysRegOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
 
   bool validateInstruction(MCInst &Inst,
-                           const SmallVectorImpl<MCParsedAsmOperand*> &Operands);
+                          const SmallVectorImpl<MCParsedAsmOperand*> &Operands);
 
   /// Scan the next token (which had better be an identifier) and determine
   /// whether it represents a general-purpose or vector register. It returns
@@ -1674,7 +1674,8 @@
     if (Parser.getTok().is(AsmToken::Comma) ||
         Parser.getTok().is(AsmToken::EndOfStatement) ||
         Parser.getTok().is(AsmToken::RBrac)) {
-      Operands.push_back(AArch64Operand::CreateShiftExtend(Spec, 0, true, S, E));
+      Operands.push_back(AArch64Operand::CreateShiftExtend(Spec, 0, true,
+                                                           S, E));
       return MatchOperand_Success;
     }
   }
@@ -1697,7 +1698,8 @@
   Parser.Lex();
   E = Parser.getTok().getLoc();
 
-  Operands.push_back(AArch64Operand::CreateShiftExtend(Spec, Amount, false, S, E));
+  Operands.push_back(AArch64Operand::CreateShiftExtend(Spec, Amount, false,
+                                                       S, E));
 
   return MatchOperand_Success;
 }
@@ -1942,7 +1944,7 @@
                                  bool MatchingInlineAsm) {
   MCInst Inst;
   unsigned MatchResult;
-  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo, 
+  MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
                                      MatchingInlineAsm);
   switch (MatchResult) {
   default: break;
diff --git a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
index 017b509..38d0e8e 100644
--- a/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
+++ b/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp
@@ -77,10 +77,12 @@
                                          uint64_t Address, const void *Decoder);
 static DecodeStatus DecodeFPR64RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
                                          uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
-                                         uint64_t Address, const void *Decoder);
-static DecodeStatus DecodeVPR128RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
-                                              uint64_t Address, const void *Decoder);
+static DecodeStatus DecodeFPR128RegisterClass(llvm::MCInst &Inst,
+                                              unsigned RegNo, uint64_t Address,
+                                              const void *Decoder);
+static DecodeStatus DecodeVPR128RegisterClass(llvm::MCInst &Inst,
+                                              unsigned RegNo, uint64_t Address,
+                                              const void *Decoder);
 
 static DecodeStatus DecodeAddrRegExtendOperand(llvm::MCInst &Inst,
                                                unsigned OptionHiS,
@@ -143,11 +145,10 @@
                                           uint64_t Address,
                                           const void *Decoder);
 
-static DecodeStatus DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper,
-                                        llvm::MCInst &Inst,
-                                        unsigned Val,
-                                        uint64_t Address,
-                                        const void *Decoder);
+static DecodeStatus
+DecodeSysRegOperand(const A64SysReg::SysRegMapper &InstMapper,
+                    llvm::MCInst &Inst, unsigned Val,
+                    uint64_t Address, const void *Decoder);
 
 static DecodeStatus DecodeMRSOperand(llvm::MCInst &Inst,
                                      unsigned Val,
@@ -247,7 +248,8 @@
 }
 
 static DecodeStatus DecodeGPR32RegisterClass(llvm::MCInst &Inst, unsigned RegNo,
-                                             uint64_t Address, const void *Decoder) {
+                                             uint64_t Address,
+                                             const void *Decoder) {
   if (RegNo > 31)
     return MCDisassembler::Fail;
 
@@ -460,8 +462,10 @@
   }
 
   // ASR and LSR have more specific patterns so they won't get here:
-  assert(!(ImmS == 31 && !SF && Opc != BFM) && "shift should have used auto decode");
-  assert(!(ImmS == 63 && SF && Opc != BFM) && "shift should have used auto decode");
+  assert(!(ImmS == 31 && !SF && Opc != BFM)
+         && "shift should have used auto decode");
+  assert(!(ImmS == 63 && SF && Opc != BFM)
+         && "shift should have used auto decode");
 
   // Extension instructions similarly:
   if (Opc == SBFM && ImmR == 0) {
diff --git a/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h b/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
index ec14595..639fa86 100644
--- a/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
+++ b/lib/Target/AArch64/InstPrinter/AArch64InstPrinter.h
@@ -114,7 +114,7 @@
   }
 
   void printShiftOperand(const char *name, const MCInst *MI,
-                         unsigned OpIdx, raw_ostream &O);  
+                         unsigned OpIdx, raw_ostream &O);
 
   void printLSLOperand(const MCInst *MI, unsigned OpNum, raw_ostream &O);
 
diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
index a206fd1..5d5e38e 100644
--- a/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
+++ b/lib/Target/AArch64/MCTargetDesc/AArch64AsmBackend.cpp
@@ -94,73 +94,73 @@
 // This table *must* be in the order that the fixup_* kinds are defined in
 // AArch64FixupKinds.h.
 //
-// Name                         Offset (bits)    Size (bits)      Flags
-      { "fixup_a64_ld_prel",               0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_adr_prel",              0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_adr_prel_page",         0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_add_lo12",              0,    32,             0 },
-      { "fixup_a64_ldst8_lo12",            0,    32,             0 },
-      { "fixup_a64_ldst16_lo12",           0,    32,             0 },
-      { "fixup_a64_ldst32_lo12",           0,    32,             0 },
-      { "fixup_a64_ldst64_lo12",           0,    32,             0 },
-      { "fixup_a64_ldst128_lo12",          0,    32,             0 },
-      { "fixup_a64_tstbr",                 0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_condbr",                0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_uncondbr",              0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_call",                  0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_movw_uabs_g0",          0,    32,             0 },
-      { "fixup_a64_movw_uabs_g0_nc",       0,    32,             0 },
-      { "fixup_a64_movw_uabs_g1",          0,    32,             0 },
-      { "fixup_a64_movw_uabs_g1_nc",       0,    32,             0 },
-      { "fixup_a64_movw_uabs_g2",          0,    32,             0 },
-      { "fixup_a64_movw_uabs_g2_nc",       0,    32,             0 },
-      { "fixup_a64_movw_uabs_g3",          0,    32,             0 },
-      { "fixup_a64_movw_sabs_g0",          0,    32,             0 },
-      { "fixup_a64_movw_sabs_g1",          0,    32,             0 },
-      { "fixup_a64_movw_sabs_g2",          0,    32,             0 },
-      { "fixup_a64_adr_prel_got_page",     0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_ld64_got_lo12_nc",      0,    32,             0 },
-      { "fixup_a64_movw_dtprel_g2",        0,    32,             0 },
-      { "fixup_a64_movw_dtprel_g1",        0,    32,             0 },
-      { "fixup_a64_movw_dtprel_g1_nc",     0,    32,             0 },
-      { "fixup_a64_movw_dtprel_g0",        0,    32,             0 },
-      { "fixup_a64_movw_dtprel_g0_nc",     0,    32,             0 },
-      { "fixup_a64_add_dtprel_hi12",       0,    32,             0 },
-      { "fixup_a64_add_dtprel_lo12",       0,    32,             0 },
-      { "fixup_a64_add_dtprel_lo12_nc",    0,    32,             0 },
-      { "fixup_a64_ldst8_dtprel_lo12",     0,    32,             0 },
-      { "fixup_a64_ldst8_dtprel_lo12_nc",  0,    32,             0 },
-      { "fixup_a64_ldst16_dtprel_lo12",    0,    32,             0 },
-      { "fixup_a64_ldst16_dtprel_lo12_nc", 0,    32,             0 },
-      { "fixup_a64_ldst32_dtprel_lo12",    0,    32,             0 },
-      { "fixup_a64_ldst32_dtprel_lo12_nc", 0,    32,             0 },
-      { "fixup_a64_ldst64_dtprel_lo12",    0,    32,             0 },
-      { "fixup_a64_ldst64_dtprel_lo12_nc", 0,    32,             0 },
-      { "fixup_a64_movw_gottprel_g1",      0,    32,             0 },
-      { "fixup_a64_movw_gottprel_g0_nc",   0,    32,             0 },
-      { "fixup_a64_adr_gottprel_page",     0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_ld64_gottprel_lo12_nc", 0,    32,             0 },
-      { "fixup_a64_ld_gottprel_prel19",    0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_movw_tprel_g2",         0,    32,             0 },
-      { "fixup_a64_movw_tprel_g1",         0,    32,             0 },
-      { "fixup_a64_movw_tprel_g1_nc",      0,    32,             0 },
-      { "fixup_a64_movw_tprel_g0",         0,    32,             0 },
-      { "fixup_a64_movw_tprel_g0_nc",      0,    32,             0 },
-      { "fixup_a64_add_tprel_hi12",        0,    32,             0 },
-      { "fixup_a64_add_tprel_lo12",        0,    32,             0 },
-      { "fixup_a64_add_tprel_lo12_nc",     0,    32,             0 },
-      { "fixup_a64_ldst8_tprel_lo12",      0,    32,             0 },
-      { "fixup_a64_ldst8_tprel_lo12_nc",   0,    32,             0 },
-      { "fixup_a64_ldst16_tprel_lo12",     0,    32,             0 },
-      { "fixup_a64_ldst16_tprel_lo12_nc",  0,    32,             0 },
-      { "fixup_a64_ldst32_tprel_lo12",     0,    32,             0 },
-      { "fixup_a64_ldst32_tprel_lo12_nc",  0,    32,             0 },
-      { "fixup_a64_ldst64_tprel_lo12",     0,    32,             0 },
-      { "fixup_a64_ldst64_tprel_lo12_nc",  0,    32,             0 },
-      { "fixup_a64_tlsdesc_adr_page",      0,    32, MCFixupKindInfo::FKF_IsPCRel },
-      { "fixup_a64_tlsdesc_ld64_lo12_nc",  0,    32,             0 },
-      { "fixup_a64_tlsdesc_add_lo12_nc",   0,    32,             0 },
-      { "fixup_a64_tlsdesc_call",          0,     0,             0 }
+// Name                   Offset (bits)    Size (bits)    Flags
+{ "fixup_a64_ld_prel",               0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_adr_prel",              0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_adr_prel_page",         0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_add_lo12",              0,    32,             0 },
+{ "fixup_a64_ldst8_lo12",            0,    32,             0 },
+{ "fixup_a64_ldst16_lo12",           0,    32,             0 },
+{ "fixup_a64_ldst32_lo12",           0,    32,             0 },
+{ "fixup_a64_ldst64_lo12",           0,    32,             0 },
+{ "fixup_a64_ldst128_lo12",          0,    32,             0 },
+{ "fixup_a64_tstbr",                 0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_condbr",                0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_uncondbr",              0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_call",                  0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_movw_uabs_g0",          0,    32,             0 },
+{ "fixup_a64_movw_uabs_g0_nc",       0,    32,             0 },
+{ "fixup_a64_movw_uabs_g1",          0,    32,             0 },
+{ "fixup_a64_movw_uabs_g1_nc",       0,    32,             0 },
+{ "fixup_a64_movw_uabs_g2",          0,    32,             0 },
+{ "fixup_a64_movw_uabs_g2_nc",       0,    32,             0 },
+{ "fixup_a64_movw_uabs_g3",          0,    32,             0 },
+{ "fixup_a64_movw_sabs_g0",          0,    32,             0 },
+{ "fixup_a64_movw_sabs_g1",          0,    32,             0 },
+{ "fixup_a64_movw_sabs_g2",          0,    32,             0 },
+{ "fixup_a64_adr_prel_got_page",     0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_ld64_got_lo12_nc",      0,    32,             0 },
+{ "fixup_a64_movw_dtprel_g2",        0,    32,             0 },
+{ "fixup_a64_movw_dtprel_g1",        0,    32,             0 },
+{ "fixup_a64_movw_dtprel_g1_nc",     0,    32,             0 },
+{ "fixup_a64_movw_dtprel_g0",        0,    32,             0 },
+{ "fixup_a64_movw_dtprel_g0_nc",     0,    32,             0 },
+{ "fixup_a64_add_dtprel_hi12",       0,    32,             0 },
+{ "fixup_a64_add_dtprel_lo12",       0,    32,             0 },
+{ "fixup_a64_add_dtprel_lo12_nc",    0,    32,             0 },
+{ "fixup_a64_ldst8_dtprel_lo12",     0,    32,             0 },
+{ "fixup_a64_ldst8_dtprel_lo12_nc",  0,    32,             0 },
+{ "fixup_a64_ldst16_dtprel_lo12",    0,    32,             0 },
+{ "fixup_a64_ldst16_dtprel_lo12_nc", 0,    32,             0 },
+{ "fixup_a64_ldst32_dtprel_lo12",    0,    32,             0 },
+{ "fixup_a64_ldst32_dtprel_lo12_nc", 0,    32,             0 },
+{ "fixup_a64_ldst64_dtprel_lo12",    0,    32,             0 },
+{ "fixup_a64_ldst64_dtprel_lo12_nc", 0,    32,             0 },
+{ "fixup_a64_movw_gottprel_g1",      0,    32,             0 },
+{ "fixup_a64_movw_gottprel_g0_nc",   0,    32,             0 },
+{ "fixup_a64_adr_gottprel_page",     0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_ld64_gottprel_lo12_nc", 0,    32,             0 },
+{ "fixup_a64_ld_gottprel_prel19",    0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_movw_tprel_g2",         0,    32,             0 },
+{ "fixup_a64_movw_tprel_g1",         0,    32,             0 },
+{ "fixup_a64_movw_tprel_g1_nc",      0,    32,             0 },
+{ "fixup_a64_movw_tprel_g0",         0,    32,             0 },
+{ "fixup_a64_movw_tprel_g0_nc",      0,    32,             0 },
+{ "fixup_a64_add_tprel_hi12",        0,    32,             0 },
+{ "fixup_a64_add_tprel_lo12",        0,    32,             0 },
+{ "fixup_a64_add_tprel_lo12_nc",     0,    32,             0 },
+{ "fixup_a64_ldst8_tprel_lo12",      0,    32,             0 },
+{ "fixup_a64_ldst8_tprel_lo12_nc",   0,    32,             0 },
+{ "fixup_a64_ldst16_tprel_lo12",     0,    32,             0 },
+{ "fixup_a64_ldst16_tprel_lo12_nc",  0,    32,             0 },
+{ "fixup_a64_ldst32_tprel_lo12",     0,    32,             0 },
+{ "fixup_a64_ldst32_tprel_lo12_nc",  0,    32,             0 },
+{ "fixup_a64_ldst64_tprel_lo12",     0,    32,             0 },
+{ "fixup_a64_ldst64_tprel_lo12_nc",  0,    32,             0 },
+{ "fixup_a64_tlsdesc_adr_page",      0,    32, MCFixupKindInfo::FKF_IsPCRel },
+{ "fixup_a64_tlsdesc_ld64_lo12_nc",  0,    32,             0 },
+{ "fixup_a64_tlsdesc_add_lo12_nc",   0,    32,             0 },
+{ "fixup_a64_tlsdesc_call",          0,     0,             0 }
     };
     if (Kind < FirstTargetFixupKind)
       return MCAsmBackend::getFixupKindInfo(Kind);
diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp b/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
index ee77da2..8d45198 100644
--- a/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
+++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp
@@ -364,7 +364,7 @@
 
 unsigned
 AArch64MCCodeEmitter::getMoveWideImmOpValue(const MCInst &MI, unsigned OpIdx,
-                                            SmallVectorImpl<MCFixup> &Fixups) const {
+                                       SmallVectorImpl<MCFixup> &Fixups) const {
   const MCOperand &UImm16MO = MI.getOperand(OpIdx);
   const MCOperand &ShiftMO = MI.getOperand(OpIdx + 1);
 
diff --git a/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h b/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h
index 20adc0c..f2af204 100644
--- a/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h
+++ b/lib/Target/AArch64/MCTargetDesc/AArch64MCExpr.h
@@ -83,7 +83,8 @@
     return Create(VK_AARCH64_GOT, Expr, Ctx);
   }
 
-  static const AArch64MCExpr *CreateGOTLo12(const MCExpr *Expr, MCContext &Ctx) {
+  static const AArch64MCExpr *CreateGOTLo12(const MCExpr *Expr,
+                                            MCContext &Ctx) {
     return Create(VK_AARCH64_GOT_LO12, Expr, Ctx);
   }
 
diff --git a/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp b/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
index fa07d49..5dbdc57 100644
--- a/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
+++ b/lib/Target/AArch64/TargetInfo/AArch64TargetInfo.cpp
@@ -1,4 +1,4 @@
-//===-- AArch64TargetInfo.cpp - AArch64 Target Implementation ---------------===//
+//===-- AArch64TargetInfo.cpp - AArch64 Target Implementation -------------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
diff --git a/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp b/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
index cf9a638..5f09074 100644
--- a/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
+++ b/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp
@@ -725,7 +725,8 @@
 }
 
 
-bool A64Imms::isLogicalImmBits(unsigned RegWidth, uint32_t Bits, uint64_t &Imm) {
+bool A64Imms::isLogicalImmBits(unsigned RegWidth, uint32_t Bits,
+                               uint64_t &Imm) {
   uint32_t N = Bits >> 12;
   uint32_t ImmR = (Bits >> 6) & 0x3f;
   uint32_t ImmS = Bits & 0x3f;