CellSPU:
- Fix (brcond (setq ...)) bug, where BRNZ should have been used vice BRZ.
- Kill unused/unnecessary nodes in SPUNodes.td
- Beef out the i64operations.c test harness to use a lot of unaligned
loads, test loops and LLVM loop/basic block optimizations; run the
test harness successfully on real Cell hardware.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@61664 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/CellSPU/icmp64.ll b/test/CodeGen/CellSPU/icmp64.ll
index d2b4fc0..0b5eaaf 100644
--- a/test/CodeGen/CellSPU/icmp64.ll
+++ b/test/CodeGen/CellSPU/icmp64.ll
@@ -1,10 +1,11 @@
; RUN: llvm-as -o - %s | llc -march=cellspu > %t1.s
-; RUN: grep ceq %t1.s | count 4
+; RUN: grep ceq %t1.s | count 6
; RUN: grep cgti %t1.s | count 4
+; RUN: grep clgt %t1.s | count 2
; RUN: grep gb %t1.s | count 4
-; RUN: grep fsm %t1.s | count 2
+; RUN: grep fsm %t1.s | count 3
; RUN: grep xori %t1.s | count 1
-; RUN: grep selb %t1.s | count 2
+; RUN: grep selb %t1.s | count 5
target datalayout = "E-p:32:32:128-f64:64:128-f32:32:128-i64:32:128-i32:32:128-i16:16:128-i8:8:128-i1:8:128-a0:0:128-v128:128:128-s0:128:128"
target triple = "spu"
@@ -39,19 +40,19 @@
ret i1 %A
}
-;; define i64 @icmp_ugt_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
-;; entry:
-;; %A = icmp ugt i64 %arg1, %arg2
-;; %B = select i1 %A, i64 %val1, i64 %val2
-;; ret i64 %B
-;; }
-;;
-;; define i1 @icmp_ugt_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
-;; entry:
-;; %A = icmp ugt i64 %arg1, %arg2
-;; ret i1 %A
-;; }
-;;
+define i64 @icmp_ugt_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp ugt i64 %arg1, %arg2
+ %B = select i1 %A, i64 %val1, i64 %val2
+ ret i64 %B
+}
+
+define i1 @icmp_ugt_setcc_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
+entry:
+ %A = icmp ugt i64 %arg1, %arg2
+ ret i1 %A
+}
+
;; define i64 @icmp_uge_select_i64(i64 %arg1, i64 %arg2, i64 %val1, i64 %val2) nounwind {
;; entry:
;; %A = icmp uge i64 %arg1, %arg2