commit e0187e51a17f2081d6a72a57e0fbba8ce38d9410
author Daniel Sanders <daniel.sanders@imgtec.com> Mon Sep 23 14:29:55 2013 +0000
committer Daniel Sanders <daniel.sanders@imgtec.com> Mon Sep 23 14:29:55 2013 +0000
tree 53c1a00d7d3ee2183eec49395d367e07950e6265
parent 0f22c134be40a337b30e30bdafb9e8b6880dea1e

[mips][msa] Added support for matching addvi, and subvi from normal IR (i.e. not intrinsics)



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191203 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Mips/MipsSEISelLowering.cpp

diff --git a/lib/Target/Mips/MipsSEISelLowering.cpp b/lib/Target/Mips/MipsSEISelLowering.cpp
index 732b68b..60960d6 100644
--- a/lib/Target/Mips/MipsSEISelLowering.cpp
+++ b/lib/Target/Mips/MipsSEISelLowering.cpp
@@ -980,6 +980,14 @@
   return Result;
 }
 
+static SDValue lowerMSABinaryImmIntr(SDValue Op, SelectionDAG &DAG,
+                                     unsigned Opc, SDValue RHS) {
+  SDValue LHS = Op->getOperand(1);
+  EVT ResTy = Op->getValueType(0);
+
+  return DAG.getNode(Opc, SDLoc(Op), ResTy, LHS, RHS);
+}
+
 static SDValue lowerMSABranchIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
   SDLoc DL(Op);
   SDValue Value = Op->getOperand(1);
@@ -1017,6 +1025,16 @@
   return Result;
 }
 
+static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) {
+  EVT ResTy = Op->getValueType(0);
+
+  unsigned SplatOp = MipsISD::VSPLAT;
+  if (ResTy == MVT::v2i64)
+    SplatOp = MipsISD::VSPLATD;
+
+  return DAG.getNode(SplatOp, SDLoc(Op), ResTy, Op->getOperand(ImmOp));
+}
+
 static SDValue lowerMSAUnaryIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) {
   SDLoc DL(Op);
   SDValue Value = Op->getOperand(1);
@@ -1069,6 +1087,12 @@
   case Intrinsic::mips_addv_w:
   case Intrinsic::mips_addv_d:
     return lowerMSABinaryIntr(Op, DAG, ISD::ADD);
+  case Intrinsic::mips_addvi_b:
+  case Intrinsic::mips_addvi_h:
+  case Intrinsic::mips_addvi_w:
+  case Intrinsic::mips_addvi_d:
+    return lowerMSABinaryImmIntr(Op, DAG, ISD::ADD,
+                                 lowerMSASplatImm(Op, 2, DAG));
   case Intrinsic::mips_and_v:
     return lowerMSABinaryIntr(Op, DAG, ISD::AND);
   case Intrinsic::mips_bnz_b:
@@ -1178,6 +1202,12 @@
   case Intrinsic::mips_subv_w:
   case Intrinsic::mips_subv_d:
     return lowerMSABinaryIntr(Op, DAG, ISD::SUB);
+  case Intrinsic::mips_subvi_b:
+  case Intrinsic::mips_subvi_h:
+  case Intrinsic::mips_subvi_w:
+  case Intrinsic::mips_subvi_d:
+    return lowerMSABinaryImmIntr(Op, DAG, ISD::SUB,
+                                 lowerMSASplatImm(Op, 2, DAG));
   case Intrinsic::mips_xor_v:
     return lowerMSABinaryIntr(Op, DAG, ISD::XOR);
   }