commit e11a8f565c6a019ddc54667227be9c4d8f117473
author Jim Grosbach <grosbach@apple.com> Fri Sep 11 19:49:06 2009 +0000
committer Jim Grosbach <grosbach@apple.com> Fri Sep 11 19:49:06 2009 +0000
tree 39bf91100550a6a078f5ac04931dabd1d25071ad
parent d00025a6c85522a43348e4473b8eb58f7a0129c9

Update register class references to use the global constant ARM::*RegisterClass names.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81556 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMBaseRegisterInfo.cpp

diff --git a/lib/Target/ARM/ARMBaseRegisterInfo.cpp b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
index 1c41073..908819c 100644
--- a/lib/Target/ARM/ARMBaseRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMBaseRegisterInfo.cpp
@@ -164,42 +164,46 @@
 const TargetRegisterClass* const *
 ARMBaseRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
   static const TargetRegisterClass * const CalleeSavedRegClasses[] = {
-    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
-    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
-    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
+    ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
+    ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
+    ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
 
-    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
-    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
+    ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
+    ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
+    ARM::DPRRegisterClass, ARM::DPRRegisterClass,
     0
   };
 
   static const TargetRegisterClass * const ThumbCalleeSavedRegClasses[] = {
-    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
-    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::tGPRRegClass,
-    &ARM::tGPRRegClass,&ARM::tGPRRegClass,&ARM::tGPRRegClass,
+    ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
+    ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::tGPRRegisterClass,
+    ARM::tGPRRegisterClass,ARM::tGPRRegisterClass,ARM::tGPRRegisterClass,
 
-    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
-    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
+    ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
+    ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
+    ARM::DPRRegisterClass, ARM::DPRRegisterClass,
     0
   };
 
   static const TargetRegisterClass * const DarwinCalleeSavedRegClasses[] = {
-    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
-    &ARM::GPRRegClass, &ARM::GPRRegClass, &ARM::GPRRegClass,
-    &ARM::GPRRegClass, &ARM::GPRRegClass,
+    ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
+    ARM::GPRRegisterClass, ARM::GPRRegisterClass, ARM::GPRRegisterClass,
+    ARM::GPRRegisterClass, ARM::GPRRegisterClass,
 
-    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
-    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
+    ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
+    ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
+    ARM::DPRRegisterClass, ARM::DPRRegisterClass,
     0
   };
 
   static const TargetRegisterClass * const DarwinThumbCalleeSavedRegClasses[] ={
-    &ARM::GPRRegClass,  &ARM::tGPRRegClass, &ARM::tGPRRegClass,
-    &ARM::tGPRRegClass, &ARM::tGPRRegClass, &ARM::GPRRegClass,
-    &ARM::GPRRegClass,  &ARM::GPRRegClass,
+    ARM::GPRRegisterClass,  ARM::tGPRRegisterClass, ARM::tGPRRegisterClass,
+    ARM::tGPRRegisterClass, ARM::tGPRRegisterClass, ARM::GPRRegisterClass,
+    ARM::GPRRegisterClass,  ARM::GPRRegisterClass,
 
-    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
-    &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass, &ARM::DPRRegClass,
+    ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
+    ARM::DPRRegisterClass, ARM::DPRRegisterClass, ARM::DPRRegisterClass,
+    ARM::DPRRegisterClass, ARM::DPRRegisterClass,
     0
   };
 
@@ -245,7 +249,7 @@
 
 const TargetRegisterClass *
 ARMBaseRegisterInfo::getPointerRegClass(unsigned Kind) const {
-  return &ARM::GPRRegClass;
+  return ARM::GPRRegisterClass;
 }
 
 /// getAllocationOrder - Returns the register allocation order for a specified
@@ -536,7 +540,7 @@
       }
     }
 
-    if (CSRegClasses[i] == &ARM::GPRRegClass) {
+    if (CSRegClasses[i] == ARM::GPRRegisterClass) {
       if (Spilled) {
         NumGPRSpills++;
 
@@ -680,7 +684,7 @@
           }
         } else {
           // Reserve a slot closest to SP or frame pointer.
-          const TargetRegisterClass *RC = &ARM::GPRRegClass;
+          const TargetRegisterClass *RC = ARM::GPRRegisterClass;
           RS->setScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
                                                            RC->getAlignment()));
         }
@@ -1068,10 +1072,10 @@
   // If the offset we have is too large to fit into the instruction, we need
   // to form it with a series of ADDri's.  Do this by taking 8-bit chunks
   // out of 'Offset'.
-  unsigned ScratchReg = findScratchRegister(RS, &ARM::GPRRegClass, AFI);
+  unsigned ScratchReg = findScratchRegister(RS, ARM::GPRRegisterClass, AFI);
   if (ScratchReg == 0)
     // No register is "free". Scavenge a register.
-    ScratchReg = RS->scavengeRegister(&ARM::GPRRegClass, II, SPAdj);
+    ScratchReg = RS->scavengeRegister(ARM::GPRRegisterClass, II, SPAdj);
   int PIdx = MI.findFirstPredOperandIdx();
   ARMCC::CondCodes Pred = (PIdx == -1)
     ? ARMCC::AL : (ARMCC::CondCodes)MI.getOperand(PIdx).getImm();