commit e1b53287179b4b9b5c3c549586f688d3fa2ae8ef
author Andrew Trick <atrick@apple.com> Mon Sep 17 23:00:42 2012 +0000
committer Andrew Trick <atrick@apple.com> Mon Sep 17 23:00:42 2012 +0000
tree 3d76841b29da81f048e4a8da6149d48575efb2d8
parent 419e5b9d4f8bd0e0724b7b2c2d8df0f534bc8d8d

Revert r164061-r164067. Most of the new subtarget emitter.

I have to work out the Target/CodeGen header dependencies
before putting this back.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@164072 91177308-0d34-0410-b5e6-96231b3b80d8

lib/MC/MCSubtargetInfo.cpp

diff --git a/lib/MC/MCSubtargetInfo.cpp b/lib/MC/MCSubtargetInfo.cpp
index 3eae8ce..47735a4 100644
--- a/lib/MC/MCSubtargetInfo.cpp
+++ b/lib/MC/MCSubtargetInfo.cpp
@@ -19,28 +19,11 @@
 
 MCSchedModel MCSchedModel::DefaultSchedModel; // For unknown processors.
 
-/// ReInitMCSubtargetInfo - Set or chaing the CPU (optionally supplemented
-/// with feature string). Recompute feature bits and scheduling model.
-void
-MCSubtargetInfo::InitMCProcessorInfo(StringRef CPU, StringRef FS) {
-  SubtargetFeatures Features(FS);
-  FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
-                                        ProcFeatures, NumFeatures);
-
-  if (!CPU.empty())
-    CPUSchedModel = getSchedModelForCPU(CPU);
-  else
-    CPUSchedModel = &MCSchedModel::DefaultSchedModel;
-}
-
 void
 MCSubtargetInfo::InitMCSubtargetInfo(StringRef TT, StringRef CPU, StringRef FS,
                                      const SubtargetFeatureKV *PF,
                                      const SubtargetFeatureKV *PD,
                                      const SubtargetInfoKV *ProcSched,
-                                     const MCWriteProcResEntry *WPR,
-                                     const MCWriteLatencyEntry *WL,
-                                     const MCReadAdvanceEntry *RA,
                                      const InstrStage *IS,
                                      const unsigned *OC,
                                      const unsigned *FP,
@@ -49,17 +32,25 @@
   ProcFeatures = PF;
   ProcDesc = PD;
   ProcSchedModels = ProcSched;
-  WriteProcResTable = WPR;
-  WriteLatencyTable = WL;
-  ReadAdvanceTable = RA;
-
   Stages = IS;
   OperandCycles = OC;
   ForwardingPaths = FP;
   NumFeatures = NF;
   NumProcs = NP;
 
-  InitMCProcessorInfo(CPU, FS);
+  SubtargetFeatures Features(FS);
+  FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
+                                        ProcFeatures, NumFeatures);
+}
+
+
+/// ReInitMCSubtargetInfo - Change CPU (and optionally supplemented with
+/// feature string) and recompute feature bits.
+uint64_t MCSubtargetInfo::ReInitMCSubtargetInfo(StringRef CPU, StringRef FS) {
+  SubtargetFeatures Features(FS);
+  FeatureBits = Features.getFeatureBits(CPU, ProcDesc, NumProcs,
+                                        ProcFeatures, NumFeatures);
+  return FeatureBits;
 }
 
 /// ToggleFeature - Toggle a feature and returns the re-computed feature
@@ -114,5 +105,5 @@
 /// Initialize an InstrItineraryData instance.
 void MCSubtargetInfo::initInstrItins(InstrItineraryData &InstrItins) const {
   InstrItins =
-    InstrItineraryData(CPUSchedModel, Stages, OperandCycles, ForwardingPaths);
+    InstrItineraryData(0, Stages, OperandCycles, ForwardingPaths);
 }