Simplify extract element based on comments from Duncan Sands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62459 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 230079b..67a419a 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -4880,14 +4880,9 @@
SDValue DAGCombiner::visitEXTRACT_VECTOR_ELT(SDNode *N) {
// (vextract (scalar_to_vector val, 0) -> val
SDValue InVec = N->getOperand(0);
- SDValue EltNo = N->getOperand(1);
- if (isa<ConstantSDNode>(EltNo)) {
- unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
- if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR && Elt == 0) {
- return InVec.getOperand(0);
- }
- }
+ if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR)
+ return InVec.getOperand(0);
// Perform only after legalization to ensure build_vector / vector_shuffle
// optimizations have already been done.
@@ -4896,6 +4891,7 @@
// (vextract (v4f32 load $addr), c) -> (f32 load $addr+c*size)
// (vextract (v4f32 s2v (f32 load $addr)), c) -> (f32 load $addr+c*size)
// (vextract (v4f32 shuffle (load $addr), <1,u,u,u>), 0) -> (f32 load $addr)
+ SDValue EltNo = N->getOperand(1);
if (isa<ConstantSDNode>(EltNo)) {
unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();