Great renaming: Sparc --> SparcV9
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11826 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/SparcV9/SparcV9TargetMachine.cpp b/lib/Target/SparcV9/SparcV9TargetMachine.cpp
index 2b4c3cb..76e7707 100644
--- a/lib/Target/SparcV9/SparcV9TargetMachine.cpp
+++ b/lib/Target/SparcV9/SparcV9TargetMachine.cpp
@@ -1,4 +1,4 @@
-//===-- Sparc.cpp - General implementation file for the Sparc Target ------===//
+//===-- SparcV9.cpp - General implementation file for the SparcV9 Target ------===//
//
// The LLVM Compiler Infrastructure
//
@@ -26,21 +26,21 @@
#include "llvm/Target/TargetMachineImpls.h"
#include "llvm/Transforms/Scalar.h"
#include "MappingInfo.h"
-#include "SparcInternals.h"
-#include "SparcTargetMachine.h"
+#include "SparcV9Internals.h"
+#include "SparcV9TargetMachine.h"
#include "Support/CommandLine.h"
using namespace llvm;
static const unsigned ImplicitRegUseList[] = { 0 }; /* not used yet */
// Build the MachineInstruction Description Array...
-const TargetInstrDescriptor llvm::SparcMachineInstrDesc[] = {
+const TargetInstrDescriptor llvm::SparcV9MachineInstrDesc[] = {
#define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
{ OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS, 0, \
ImplicitRegUseList, ImplicitRegUseList },
-#include "SparcInstr.def"
+#include "SparcV9Instr.def"
};
//---------------------------------------------------------------------------
@@ -106,13 +106,13 @@
}
}
-FunctionPass *llvm::createSparcMachineCodeDestructionPass() {
+FunctionPass *llvm::createSparcV9MachineCodeDestructionPass() {
return new DestroyMachineFunction();
}
-SparcTargetMachine::SparcTargetMachine(IntrinsicLowering *il)
- : TargetMachine("UltraSparc-Native", il, false),
+SparcV9TargetMachine::SparcV9TargetMachine(IntrinsicLowering *il)
+ : TargetMachine("UltraSparcV9-Native", il, false),
schedInfo(*this),
regInfo(*this),
frameInfo(*this),
@@ -124,7 +124,7 @@
/// process for the ultra sparc.
///
bool
-SparcTargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
+SparcV9TargetMachine::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out)
{
// The following 3 passes used to be inserted specially by llc.
// Replace malloc and free instructions with library calls.
@@ -177,7 +177,7 @@
// allowing machine code representations for functions to be free'd after the
// function has been emitted.
PM.add(createAsmPrinterPass(Out, *this));
- PM.add(createSparcMachineCodeDestructionPass()); // Free mem no longer needed
+ PM.add(createSparcV9MachineCodeDestructionPass()); // Free mem no longer needed
// Emit bytecode to the assembly file into its special section next
if (EmitMappingInfo)
@@ -187,9 +187,9 @@
}
/// addPassesToJITCompile - This method controls the JIT method of code
-/// generation for the UltraSparc.
+/// generation for the UltraSparcV9.
///
-void SparcJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
+void SparcV9JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
const TargetData &TD = TM.getTargetData();
PM.add(new TargetData("lli", TD.isLittleEndian(), TD.getPointerSize(),
@@ -229,10 +229,10 @@
PM.add(createPeepholeOptsPass(TM));
}
-/// allocateSparcTargetMachine - Allocate and return a subclass of TargetMachine
-/// that implements the Sparc backend. (the llvm/CodeGen/Sparc.h interface)
+/// allocateSparcV9TargetMachine - Allocate and return a subclass of TargetMachine
+/// that implements the SparcV9 backend. (the llvm/CodeGen/SparcV9.h interface)
///
-TargetMachine *llvm::allocateSparcTargetMachine(const Module &M,
+TargetMachine *llvm::allocateSparcV9TargetMachine(const Module &M,
IntrinsicLowering *IL) {
- return new SparcTargetMachine(IL);
+ return new SparcV9TargetMachine(IL);
}