diff --git a/lib/Target/ARM/ARMAsmBackend.cpp b/lib/Target/ARM/ARMAsmBackend.cpp
index 54cd1ae..d5a2759 100644
--- a/lib/Target/ARM/ARMAsmBackend.cpp
+++ b/lib/Target/ARM/ARMAsmBackend.cpp
@@ -56,10 +56,14 @@
 }
 
 bool ARMAsmBackend::WriteNopData(uint64_t Count, MCObjectWriter *OW) const {
-  if ((Count % 4) != 0) {
-    // Fixme: % 2 for Thumb?
-    return false;
-  }
+//  if ((Count % 4) != 0) {
+//    // Fixme: % 2 for Thumb?
+//    return false;
+//  }
+  // FIXME: Zero fill for now. That's not right, but at least will get the
+  // section size right.
+  for (uint64_t i = 0; i != Count; ++i)
+    OW->Write8(0);
   return true;
 }
 } // end anonymous namespace
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp
index ebd0d9b..96da945 100644
--- a/lib/Target/ARM/ARMMCCodeEmitter.cpp
+++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp
@@ -608,10 +608,17 @@
                   SmallVectorImpl<MCFixup> &Fixups) const {
   // Pseudo instructions don't get encoded.
   const TargetInstrDesc &Desc = TII.get(MI.getOpcode());
-  if ((Desc.TSFlags & ARMII::FormMask) == ARMII::Pseudo)
+  uint64_t TSFlags = Desc.TSFlags;
+  if ((TSFlags & ARMII::FormMask) == ARMII::Pseudo)
     return;
-
-  EmitConstant(getBinaryCodeForInstr(MI, Fixups), 4, OS);
+  int Size;
+  // Basic size info comes from the TSFlags field.
+  switch ((TSFlags & ARMII::SizeMask) >> ARMII::SizeShift) {
+  default: llvm_unreachable("Unexpected instruction size!");
+  case ARMII::Size2Bytes: Size = 2; break;
+  case ARMII::Size4Bytes: Size = 4; break;
+  }
+  EmitConstant(getBinaryCodeForInstr(MI, Fixups), Size, OS);
   ++MCNumEmitted;  // Keep track of the # of mi's emitted.
 }