Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78610 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
index d6137a5..7a1eeb2 100644
--- a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
+++ b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
@@ -33,8 +33,8 @@
// HandleByVal - Allocate a stack slot large enough to pass an argument by
// value. The size and alignment information of the argument is encoded in its
// parameter attribute.
-void CCState::HandleByVal(unsigned ValNo, MVT ValVT,
- MVT LocVT, CCValAssign::LocInfo LocInfo,
+void CCState::HandleByVal(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
int MinSize, int MinAlign,
ISD::ArgFlagsTy ArgFlags) {
unsigned Align = ArgFlags.getByValAlign();
@@ -65,12 +65,12 @@
unsigned NumArgs = Ins.size();
for (unsigned i = 0; i != NumArgs; ++i) {
- MVT ArgVT = Ins[i].VT;
+ EVT ArgVT = Ins[i].VT;
ISD::ArgFlagsTy ArgFlags = Ins[i].Flags;
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
#ifndef NDEBUG
cerr << "Formal argument #" << i << " has unhandled type "
- << ArgVT.getMVTString();
+ << ArgVT.getEVTString();
#endif
llvm_unreachable(0);
}
@@ -83,12 +83,12 @@
CCAssignFn Fn) {
// Determine which register each value should be copied into.
for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
- MVT VT = Outs[i].Val.getValueType();
+ EVT VT = Outs[i].Val.getValueType();
ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this)) {
#ifndef NDEBUG
cerr << "Return operand #" << i << " has unhandled type "
- << VT.getMVTString();
+ << VT.getEVTString();
#endif
llvm_unreachable(0);
}
@@ -102,12 +102,12 @@
CCAssignFn Fn) {
unsigned NumOps = Outs.size();
for (unsigned i = 0; i != NumOps; ++i) {
- MVT ArgVT = Outs[i].Val.getValueType();
+ EVT ArgVT = Outs[i].Val.getValueType();
ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
#ifndef NDEBUG
cerr << "Call operand #" << i << " has unhandled type "
- << ArgVT.getMVTString();
+ << ArgVT.getEVTString();
#endif
llvm_unreachable(0);
}
@@ -116,17 +116,17 @@
/// AnalyzeCallOperands - Same as above except it takes vectors of types
/// and argument flags.
-void CCState::AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
+void CCState::AnalyzeCallOperands(SmallVectorImpl<EVT> &ArgVTs,
SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
CCAssignFn Fn) {
unsigned NumOps = ArgVTs.size();
for (unsigned i = 0; i != NumOps; ++i) {
- MVT ArgVT = ArgVTs[i];
+ EVT ArgVT = ArgVTs[i];
ISD::ArgFlagsTy ArgFlags = Flags[i];
if (Fn(i, ArgVT, ArgVT, CCValAssign::Full, ArgFlags, *this)) {
#ifndef NDEBUG
cerr << "Call operand #" << i << " has unhandled type "
- << ArgVT.getMVTString();
+ << ArgVT.getEVTString();
#endif
llvm_unreachable(0);
}
@@ -138,12 +138,12 @@
void CCState::AnalyzeCallResult(const SmallVectorImpl<ISD::InputArg> &Ins,
CCAssignFn Fn) {
for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
- MVT VT = Ins[i].VT;
+ EVT VT = Ins[i].VT;
ISD::ArgFlagsTy Flags = Ins[i].Flags;
if (Fn(i, VT, VT, CCValAssign::Full, Flags, *this)) {
#ifndef NDEBUG
cerr << "Call result #" << i << " has unhandled type "
- << VT.getMVTString();
+ << VT.getEVTString();
#endif
llvm_unreachable(0);
}
@@ -152,11 +152,11 @@
/// AnalyzeCallResult - Same as above except it's specialized for calls which
/// produce a single value.
-void CCState::AnalyzeCallResult(MVT VT, CCAssignFn Fn) {
+void CCState::AnalyzeCallResult(EVT VT, CCAssignFn Fn) {
if (Fn(0, VT, VT, CCValAssign::Full, ISD::ArgFlagsTy(), *this)) {
#ifndef NDEBUG
cerr << "Call result has unhandled type "
- << VT.getMVTString();
+ << VT.getEVTString();
#endif
llvm_unreachable(0);
}
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 6446ed9..6119411 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -215,12 +215,12 @@
SDValue SimplifySelectCC(DebugLoc DL, SDValue N0, SDValue N1, SDValue N2,
SDValue N3, ISD::CondCode CC,
bool NotExtCompare = false);
- SDValue SimplifySetCC(MVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
+ SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
DebugLoc DL, bool foldBooleans = true);
SDValue SimplifyNodeWithTwoResults(SDNode *N, unsigned LoOp,
unsigned HiOp);
- SDValue CombineConsecutiveLoads(SDNode *N, MVT VT);
- SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, MVT);
+ SDValue CombineConsecutiveLoads(SDNode *N, EVT VT);
+ SDValue ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *, EVT);
SDValue BuildSDIV(SDNode *N);
SDValue BuildUDIV(SDNode *N);
SDNode *MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL);
@@ -253,7 +253,7 @@
/// getShiftAmountTy - Returns a type large enough to hold any valid
/// shift amount - before type legalization these can be huge.
- MVT getShiftAmountTy() {
+ EVT getShiftAmountTy() {
return LegalTypes ? TLI.getShiftAmountTy() : TLI.getPointerTy();
}
@@ -331,7 +331,7 @@
static char isNegatibleForFree(SDValue Op, bool LegalOperations,
unsigned Depth = 0) {
// No compile time optimizations on this type.
- if (Op.getValueType() == MVT::ppcf128)
+ if (Op.getValueType() == EVT::ppcf128)
return 0;
// fneg is removable even if it has multiple uses.
@@ -497,7 +497,7 @@
SDValue DAGCombiner::ReassociateOps(unsigned Opc, DebugLoc DL,
SDValue N0, SDValue N1) {
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
if (N0.getOpcode() == Opc && isa<ConstantSDNode>(N0.getOperand(1))) {
if (isa<ConstantSDNode>(N1)) {
// reassoc. (op (op x, c1), c2) -> (op x, (op c1, c2))
@@ -833,12 +833,12 @@
/// otherwise return a null sd operand.
static SDValue getInputChainForNode(SDNode *N) {
if (unsigned NumOps = N->getNumOperands()) {
- if (N->getOperand(0).getValueType() == MVT::Other)
+ if (N->getOperand(0).getValueType() == EVT::Other)
return N->getOperand(0);
- else if (N->getOperand(NumOps-1).getValueType() == MVT::Other)
+ else if (N->getOperand(NumOps-1).getValueType() == EVT::Other)
return N->getOperand(NumOps-1);
for (unsigned i = 1; i < NumOps-1; ++i)
- if (N->getOperand(i).getValueType() == MVT::Other)
+ if (N->getOperand(i).getValueType() == EVT::Other)
return N->getOperand(i);
}
return SDValue();
@@ -911,7 +911,7 @@
} else {
// New and improved token factor.
Result = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
- MVT::Other, &Ops[0], Ops.size());
+ EVT::Other, &Ops[0], Ops.size());
}
// Don't add users to work list.
@@ -935,7 +935,7 @@
static
SDValue combineShlAddConstant(DebugLoc DL, SDValue N0, SDValue N1,
SelectionDAG &DAG) {
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
SDValue N00 = N0.getOperand(0);
SDValue N01 = N0.getOperand(1);
ConstantSDNode *N01C = dyn_cast<ConstantSDNode>(N01);
@@ -959,7 +959,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
// fold vector ops
if (VT.isVector()) {
@@ -1082,13 +1082,13 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
// If the flag result is dead, turn this into an ADD.
if (N->hasNUsesOfValue(0, 1))
return CombineTo(N, DAG.getNode(ISD::ADD, N->getDebugLoc(), VT, N1, N0),
DAG.getNode(ISD::CARRY_FALSE,
- N->getDebugLoc(), MVT::Flag));
+ N->getDebugLoc(), EVT::Flag));
// canonicalize constant to RHS.
if (N0C && !N1C)
@@ -1097,7 +1097,7 @@
// fold (addc x, 0) -> x + no carry out
if (N1C && N1C->isNullValue())
return CombineTo(N, N0, DAG.getNode(ISD::CARRY_FALSE,
- N->getDebugLoc(), MVT::Flag));
+ N->getDebugLoc(), EVT::Flag));
// fold (addc a, b) -> (or a, b), CARRY_FALSE iff a and b share no bits.
APInt LHSZero, LHSOne;
@@ -1114,7 +1114,7 @@
(LHSZero & (~RHSZero & Mask)) == (~RHSZero & Mask))
return CombineTo(N, DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N1),
DAG.getNode(ISD::CARRY_FALSE,
- N->getDebugLoc(), MVT::Flag));
+ N->getDebugLoc(), EVT::Flag));
}
return SDValue();
@@ -1144,7 +1144,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
// fold vector ops
if (VT.isVector()) {
@@ -1217,7 +1217,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
// fold vector ops
if (VT.isVector()) {
@@ -1310,7 +1310,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold vector ops
if (VT.isVector()) {
@@ -1397,7 +1397,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0.getNode());
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold vector ops
if (VT.isVector()) {
@@ -1417,7 +1417,7 @@
if (N1.getOpcode() == ISD::SHL) {
if (ConstantSDNode *SHC = dyn_cast<ConstantSDNode>(N1.getOperand(0))) {
if (SHC->getAPIntValue().isPowerOf2()) {
- MVT ADDVT = N1.getOperand(1).getValueType();
+ EVT ADDVT = N1.getOperand(1).getValueType();
SDValue Add = DAG.getNode(ISD::ADD, N->getDebugLoc(), ADDVT,
N1.getOperand(1),
DAG.getConstant(SHC->getAPIntValue()
@@ -1449,7 +1449,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (srem c1, c2) -> c1%c2
if (N0C && N1C && !N1C->isNullValue())
@@ -1491,7 +1491,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (urem c1, c2) -> c1%c2
if (N0C && N1C && !N1C->isNullValue())
@@ -1543,7 +1543,7 @@
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (mulhs x, 0) -> 0
if (N1C && N1C->isNullValue())
@@ -1564,7 +1564,7 @@
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (mulhu x, 0) -> 0
if (N1C && N1C->isNullValue())
@@ -1667,7 +1667,7 @@
/// two operands of the same opcode, try to simplify it.
SDValue DAGCombiner::SimplifyBinOpWithSameOpcodeHands(SDNode *N) {
SDValue N0 = N->getOperand(0), N1 = N->getOperand(1);
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
assert(N0.getOpcode() == N1.getOpcode() && "Bad input!");
// For each of OP in AND/OR/XOR:
@@ -1713,7 +1713,7 @@
SDValue LL, LR, RL, RR, CC0, CC1;
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N1.getValueType();
+ EVT VT = N1.getValueType();
unsigned BitWidth = VT.getSizeInBits();
// fold vector ops
@@ -1824,7 +1824,7 @@
// fold (zext_inreg (extload x)) -> (zextload x)
if (ISD::isEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode())) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT EVT = LN0->getMemoryVT();
+ EVT EVT = LN0->getMemoryVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
unsigned BitWidth = N1.getValueSizeInBits();
@@ -1846,7 +1846,7 @@
if (ISD::isSEXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT EVT = LN0->getMemoryVT();
+ EVT EVT = LN0->getMemoryVT();
// If we zero all the possible extended bits, then we can turn this into
// a zextload if we are running before legalize or the operation is legal.
unsigned BitWidth = N1.getValueSizeInBits();
@@ -1873,24 +1873,24 @@
LN0->isUnindexed() && N0.hasOneUse() &&
// Do not change the width of a volatile load.
!LN0->isVolatile()) {
- MVT EVT = MVT::Other;
+ EVT ExtVT = EVT::Other;
uint32_t ActiveBits = N1C->getAPIntValue().getActiveBits();
if (ActiveBits > 0 && APIntOps::isMask(ActiveBits, N1C->getAPIntValue()))
- EVT = MVT::getIntegerVT(ActiveBits);
+ ExtVT = EVT::getIntegerVT(ActiveBits);
- MVT LoadedVT = LN0->getMemoryVT();
+ EVT LoadedVT = LN0->getMemoryVT();
// Do not generate loads of non-round integer types since these can
// be expensive (and would be wrong if the type is not byte sized).
- if (EVT != MVT::Other && LoadedVT.bitsGT(EVT) && EVT.isRound() &&
- (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT))) {
- MVT PtrType = N0.getOperand(1).getValueType();
+ if (ExtVT != EVT::Other && LoadedVT.bitsGT(ExtVT) && ExtVT.isRound() &&
+ (!LegalOperations || TLI.isLoadExtLegal(ISD::ZEXTLOAD, ExtVT))) {
+ EVT PtrType = N0.getOperand(1).getValueType();
// For big endian targets, we need to add an offset to the pointer to
// load the correct bytes. For little endian systems, we merely need to
// read fewer bytes from the same pointer.
unsigned LVTStoreBytes = LoadedVT.getStoreSizeInBits()/8;
- unsigned EVTStoreBytes = EVT.getStoreSizeInBits()/8;
+ unsigned EVTStoreBytes = ExtVT.getStoreSizeInBits()/8;
unsigned PtrOff = LVTStoreBytes - EVTStoreBytes;
unsigned Alignment = LN0->getAlignment();
SDValue NewPtr = LN0->getBasePtr();
@@ -1905,7 +1905,7 @@
SDValue Load =
DAG.getExtLoad(ISD::ZEXTLOAD, LN0->getDebugLoc(), VT, LN0->getChain(),
NewPtr, LN0->getSrcValue(), LN0->getSrcValueOffset(),
- EVT, LN0->isVolatile(), Alignment);
+ ExtVT, LN0->isVolatile(), Alignment);
AddToWorkList(N);
CombineTo(N0.getNode(), Load, Load.getValue(1));
return SDValue(N, 0); // Return N so it doesn't get rechecked!
@@ -1922,7 +1922,7 @@
SDValue LL, LR, RL, RR, CC0, CC1;
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N1.getValueType();
+ EVT VT = N1.getValueType();
// fold vector ops
if (VT.isVector()) {
@@ -2062,7 +2062,7 @@
// a rot[lr].
SDNode *DAGCombiner::MatchRotate(SDValue LHS, SDValue RHS, DebugLoc DL) {
// Must be a legal type. Expanded 'n promoted things won't work with rotates.
- MVT VT = LHS.getValueType();
+ EVT VT = LHS.getValueType();
if (!TLI.isTypeLegal(VT)) return 0;
// The target must have at least one rotate flavor.
@@ -2223,7 +2223,7 @@
SDValue LHS, RHS, CC;
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
// fold vector ops
if (VT.isVector()) {
@@ -2284,7 +2284,7 @@
}
// fold (not (or x, y)) -> (and (not x), (not y)) iff x or y are setcc
- if (N1C && N1C->getAPIntValue() == 1 && VT == MVT::i1 &&
+ if (N1C && N1C->getAPIntValue() == 1 && VT == EVT::i1 &&
(N0.getOpcode() == ISD::OR || N0.getOpcode() == ISD::AND)) {
SDValue LHS = N0.getOperand(0), RHS = N0.getOperand(1);
if (isOneUseSetCC(RHS) || isOneUseSetCC(LHS)) {
@@ -2391,7 +2391,7 @@
!isa<ConstantSDNode>(BinOpLHSVal->getOperand(1)))
return SDValue();
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// If this is a signed shift right, and the high bit is modified by the
// logical operation, do not perform the transformation. The highBitSet
@@ -2421,7 +2421,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
unsigned OpSizeInBits = VT.getSizeInBits();
// fold (shl c1, c2) -> c1<<c2
@@ -2446,7 +2446,7 @@
N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
SDValue N101 = N1.getOperand(0).getOperand(1);
if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
- MVT TruncVT = N1.getValueType();
+ EVT TruncVT = N1.getValueType();
SDValue N100 = N1.getOperand(0).getOperand(0);
APInt TruncC = N101C->getAPIntValue();
TruncC.trunc(TruncVT.getSizeInBits());
@@ -2513,7 +2513,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
// fold (sra c1, c2) -> (sra c1, c2)
if (N0C && N1C)
@@ -2534,7 +2534,7 @@
// sext_inreg.
if (N1C && N0.getOpcode() == ISD::SHL && N1 == N0.getOperand(1)) {
unsigned LowBits = VT.getSizeInBits() - (unsigned)N1C->getZExtValue();
- MVT EVT = MVT::getIntegerVT(LowBits);
+ EVT EVT = EVT::getIntegerVT(LowBits);
if ((!LegalOperations || TLI.isOperationLegal(ISD::SIGN_EXTEND_INREG, EVT)))
return DAG.getNode(ISD::SIGN_EXTEND_INREG, N->getDebugLoc(), VT,
N0.getOperand(0), DAG.getValueType(EVT));
@@ -2561,8 +2561,8 @@
if (N01C && N1C) {
// Determine what the truncate's result bitsize and type would be.
unsigned VTValSize = VT.getSizeInBits();
- MVT TruncVT =
- MVT::getIntegerVT(VTValSize - N1C->getZExtValue());
+ EVT TruncVT =
+ EVT::getIntegerVT(VTValSize - N1C->getZExtValue());
// Determine the residual right-shift amount.
signed ShiftAmt = N1C->getZExtValue() - N01C->getZExtValue();
@@ -2592,7 +2592,7 @@
N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
SDValue N101 = N1.getOperand(0).getOperand(1);
if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
- MVT TruncVT = N1.getValueType();
+ EVT TruncVT = N1.getValueType();
SDValue N100 = N1.getOperand(0).getOperand(0);
APInt TruncC = N101C->getAPIntValue();
TruncC.trunc(TruncVT.getSizeInBits());
@@ -2623,7 +2623,7 @@
SDValue N1 = N->getOperand(1);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
- MVT VT = N0.getValueType();
+ EVT VT = N0.getValueType();
unsigned OpSizeInBits = VT.getSizeInBits();
// fold (srl c1, c2) -> c1 >>u c2
@@ -2657,7 +2657,7 @@
// fold (srl (anyextend x), c) -> (anyextend (srl x, c))
if (N1C && N0.getOpcode() == ISD::ANY_EXTEND) {
// Shifting in all undef bits?
- MVT SmallVT = N0.getOperand(0).getValueType();
+ EVT SmallVT = N0.getOperand(0).getValueType();
if (N1C->getZExtValue() >= SmallVT.getSizeInBits())
return DAG.getUNDEF(VT);
@@ -2716,7 +2716,7 @@
N1.hasOneUse() && N1.getOperand(0).hasOneUse()) {
SDValue N101 = N1.getOperand(0).getOperand(1);
if (ConstantSDNode *N101C = dyn_cast<ConstantSDNode>(N101)) {
- MVT TruncVT = N1.getValueType();
+ EVT TruncVT = N1.getValueType();
SDValue N100 = N1.getOperand(0).getOperand(0);
APInt TruncC = N101C->getAPIntValue();
TruncC.trunc(TruncVT.getSizeInBits());
@@ -2740,7 +2740,7 @@
SDValue DAGCombiner::visitCTLZ(SDNode *N) {
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (ctlz c1) -> c2
if (isa<ConstantSDNode>(N0))
@@ -2750,7 +2750,7 @@
SDValue DAGCombiner::visitCTTZ(SDNode *N) {
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (cttz c1) -> c2
if (isa<ConstantSDNode>(N0))
@@ -2760,7 +2760,7 @@
SDValue DAGCombiner::visitCTPOP(SDNode *N) {
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (ctpop c1) -> c2
if (isa<ConstantSDNode>(N0))
@@ -2775,8 +2775,8 @@
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1);
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2);
- MVT VT = N->getValueType(0);
- MVT VT0 = N0.getValueType();
+ EVT VT = N->getValueType(0);
+ EVT VT0 = N0.getValueType();
// fold (select C, X, X) -> X
if (N1 == N2)
@@ -2788,11 +2788,11 @@
if (N0C && N0C->isNullValue())
return N2;
// fold (select C, 1, X) -> (or C, X)
- if (VT == MVT::i1 && N1C && N1C->getAPIntValue() == 1)
+ if (VT == EVT::i1 && N1C && N1C->getAPIntValue() == 1)
return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
// fold (select C, 0, 1) -> (xor C, 1)
if (VT.isInteger() &&
- (VT0 == MVT::i1 ||
+ (VT0 == EVT::i1 ||
(VT0.isInteger() &&
TLI.getBooleanContents() == TargetLowering::ZeroOrOneBooleanContent)) &&
N1C && N2C && N1C->isNullValue() && N2C->getAPIntValue() == 1) {
@@ -2808,27 +2808,27 @@
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), VT, XORNode);
}
// fold (select C, 0, X) -> (and (not C), X)
- if (VT == VT0 && VT == MVT::i1 && N1C && N1C->isNullValue()) {
+ if (VT == VT0 && VT == EVT::i1 && N1C && N1C->isNullValue()) {
SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
AddToWorkList(NOTNode.getNode());
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, NOTNode, N2);
}
// fold (select C, X, 1) -> (or (not C), X)
- if (VT == VT0 && VT == MVT::i1 && N2C && N2C->getAPIntValue() == 1) {
+ if (VT == VT0 && VT == EVT::i1 && N2C && N2C->getAPIntValue() == 1) {
SDValue NOTNode = DAG.getNOT(N0.getDebugLoc(), N0, VT);
AddToWorkList(NOTNode.getNode());
return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, NOTNode, N1);
}
// fold (select C, X, 0) -> (and C, X)
- if (VT == MVT::i1 && N2C && N2C->isNullValue())
+ if (VT == EVT::i1 && N2C && N2C->isNullValue())
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
// fold (select X, X, Y) -> (or X, Y)
// fold (select X, 1, Y) -> (or X, Y)
- if (VT == MVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
+ if (VT == EVT::i1 && (N0 == N1 || (N1C && N1C->getAPIntValue() == 1)))
return DAG.getNode(ISD::OR, N->getDebugLoc(), VT, N0, N2);
// fold (select X, Y, X) -> (and X, Y)
// fold (select X, Y, 0) -> (and X, Y)
- if (VT == MVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
+ if (VT == EVT::i1 && (N0 == N2 || (N2C && N2C->getAPIntValue() == 0)))
return DAG.getNode(ISD::AND, N->getDebugLoc(), VT, N0, N1);
// If we can fold this based on the true/false value, do so.
@@ -2838,10 +2838,10 @@
// fold selects based on a setcc into other things, such as min/max/abs
if (N0.getOpcode() == ISD::SETCC) {
// FIXME:
- // Check against MVT::Other for SELECT_CC, which is a workaround for targets
+ // Check against EVT::Other for SELECT_CC, which is a workaround for targets
// having to say they don't support SELECT_CC on every type the DAG knows
// about, since there is no way to mark an opcode illegal at all value types
- if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, MVT::Other) &&
+ if (TLI.isOperationLegalOrCustom(ISD::SELECT_CC, EVT::Other) &&
TLI.isOperationLegalOrCustom(ISD::SELECT_CC, VT))
return DAG.getNode(ISD::SELECT_CC, N->getDebugLoc(), VT,
N0.getOperand(0), N0.getOperand(1),
@@ -2962,7 +2962,7 @@
SDValue DAGCombiner::visitSIGN_EXTEND(SDNode *N) {
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (sext c1) -> c1
if (isa<ConstantSDNode>(N0))
@@ -3071,7 +3071,7 @@
if ((ISD::isSEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT EVT = LN0->getMemoryVT();
+ EVT EVT = LN0->getMemoryVT();
if ((!LegalOperations && !LN0->isVolatile()) ||
TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT)) {
SDValue ExtLoad = DAG.getExtLoad(ISD::SEXTLOAD, N->getDebugLoc(), VT,
@@ -3127,7 +3127,7 @@
SDValue DAGCombiner::visitZERO_EXTEND(SDNode *N) {
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (zext c1) -> c1
if (isa<ConstantSDNode>(N0))
@@ -3231,7 +3231,7 @@
if ((ISD::isZEXTLoad(N0.getNode()) || ISD::isEXTLoad(N0.getNode())) &&
ISD::isUNINDEXEDLoad(N0.getNode()) && N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT EVT = LN0->getMemoryVT();
+ EVT EVT = LN0->getMemoryVT();
if ((!LegalOperations && !LN0->isVolatile()) ||
TLI.isLoadExtLegal(ISD::ZEXTLOAD, EVT)) {
SDValue ExtLoad = DAG.getExtLoad(ISD::ZEXTLOAD, N->getDebugLoc(), VT,
@@ -3262,7 +3262,7 @@
SDValue DAGCombiner::visitANY_EXTEND(SDNode *N) {
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (aext c1) -> c1
if (isa<ConstantSDNode>(N0))
@@ -3367,7 +3367,7 @@
!ISD::isNON_EXTLoad(N0.getNode()) && ISD::isUNINDEXEDLoad(N0.getNode()) &&
N0.hasOneUse()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT EVT = LN0->getMemoryVT();
+ EVT EVT = LN0->getMemoryVT();
SDValue ExtLoad = DAG.getExtLoad(LN0->getExtensionType(), N->getDebugLoc(),
VT, LN0->getChain(), LN0->getBasePtr(),
LN0->getSrcValue(),
@@ -3437,8 +3437,8 @@
unsigned Opc = N->getOpcode();
ISD::LoadExtType ExtType = ISD::NON_EXTLOAD;
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
- MVT EVT = VT;
+ EVT VT = N->getValueType(0);
+ EVT ExtVT = VT;
// This transformation isn't valid for vector loads.
if (VT.isVector())
@@ -3448,12 +3448,12 @@
// extended to VT.
if (Opc == ISD::SIGN_EXTEND_INREG) {
ExtType = ISD::SEXTLOAD;
- EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
- if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, EVT))
+ ExtVT = cast<VTSDNode>(N->getOperand(1))->getVT();
+ if (LegalOperations && !TLI.isLoadExtLegal(ISD::SEXTLOAD, ExtVT))
return SDValue();
}
- unsigned EVTBits = EVT.getSizeInBits();
+ unsigned EVTBits = ExtVT.getSizeInBits();
unsigned ShAmt = 0;
if (N0.getOpcode() == ISD::SRL && N0.hasOneUse()) {
if (ConstantSDNode *N01 = dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
@@ -3469,18 +3469,18 @@
// Do not generate loads of non-round integer types since these can
// be expensive (and would be wrong if the type is not byte sized).
- if (isa<LoadSDNode>(N0) && N0.hasOneUse() && EVT.isRound() &&
+ if (isa<LoadSDNode>(N0) && N0.hasOneUse() && ExtVT.isRound() &&
cast<LoadSDNode>(N0)->getMemoryVT().getSizeInBits() > EVTBits &&
// Do not change the width of a volatile load.
!cast<LoadSDNode>(N0)->isVolatile()) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
- MVT PtrType = N0.getOperand(1).getValueType();
+ EVT PtrType = N0.getOperand(1).getValueType();
// For big endian targets, we need to adjust the offset to the pointer to
// load the correct bytes.
if (TLI.isBigEndian()) {
unsigned LVTStoreBits = LN0->getMemoryVT().getStoreSizeInBits();
- unsigned EVTStoreBits = EVT.getStoreSizeInBits();
+ unsigned EVTStoreBits = ExtVT.getStoreSizeInBits();
ShAmt = LVTStoreBits - EVTStoreBits - ShAmt;
}
@@ -3497,7 +3497,7 @@
LN0->isVolatile(), NewAlign)
: DAG.getExtLoad(ExtType, N0.getDebugLoc(), VT, LN0->getChain(), NewPtr,
LN0->getSrcValue(), LN0->getSrcValueOffset() + PtrOff,
- EVT, LN0->isVolatile(), NewAlign);
+ ExtVT, LN0->isVolatile(), NewAlign);
// Replace the old load's chain with the new load's chain.
WorkListRemover DeadNodes(*this);
@@ -3514,8 +3514,8 @@
SDValue DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
- MVT VT = N->getValueType(0);
- MVT EVT = cast<VTSDNode>(N1)->getVT();
+ EVT VT = N->getValueType(0);
+ EVT EVT = cast<VTSDNode>(N1)->getVT();
unsigned VTBits = VT.getSizeInBits();
unsigned EVTBits = EVT.getSizeInBits();
@@ -3610,7 +3610,7 @@
SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// noop truncate
if (N0.getValueType() == N->getValueType(0))
@@ -3660,14 +3660,14 @@
/// CombineConsecutiveLoads - build_pair (load, load) -> load
/// if load locations are consecutive.
-SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, MVT VT) {
+SDValue DAGCombiner::CombineConsecutiveLoads(SDNode *N, EVT VT) {
assert(N->getOpcode() == ISD::BUILD_PAIR);
LoadSDNode *LD1 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 0));
LoadSDNode *LD2 = dyn_cast<LoadSDNode>(getBuildPairElt(N, 1));
if (!LD1 || !LD2 || !ISD::isNON_EXTLoad(LD1) || !LD1->hasOneUse())
return SDValue();
- MVT LD1VT = LD1->getValueType(0);
+ EVT LD1VT = LD1->getValueType(0);
const MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
if (ISD::isNON_EXTLoad(LD2) &&
@@ -3679,7 +3679,7 @@
TLI.isConsecutiveLoad(LD2, LD1, LD1VT.getSizeInBits()/8, 1, MFI)) {
unsigned Align = LD1->getAlignment();
unsigned NewAlign = TLI.getTargetData()->
- getABITypeAlignment(VT.getTypeForMVT());
+ getABITypeAlignment(VT.getTypeForEVT());
if (NewAlign <= Align &&
(!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT)))
@@ -3693,7 +3693,7 @@
SDValue DAGCombiner::visitBIT_CONVERT(SDNode *N) {
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// If the input is a BUILD_VECTOR with all constant elements, fold this now.
// Only do this before legalize, since afterward the target may be depending
@@ -3711,7 +3711,7 @@
break;
}
- MVT DestEltVT = N->getValueType(0).getVectorElementType();
+ EVT DestEltVT = N->getValueType(0).getVectorElementType();
assert(!DestEltVT.isVector() &&
"Element type of vector ValueType must not be vector!");
if (isSimple)
@@ -3737,7 +3737,7 @@
(!LegalOperations || TLI.isOperationLegal(ISD::LOAD, VT))) {
LoadSDNode *LN0 = cast<LoadSDNode>(N0);
unsigned Align = TLI.getTargetData()->
- getABITypeAlignment(VT.getTypeForMVT());
+ getABITypeAlignment(VT.getTypeForEVT());
unsigned OrigAlign = LN0->getAlignment();
if (Align <= OrigAlign) {
@@ -3780,7 +3780,7 @@
isa<ConstantFPSDNode>(N0.getOperand(0)) &&
VT.isInteger() && !VT.isVector()) {
unsigned OrigXWidth = N0.getOperand(1).getValueType().getSizeInBits();
- MVT IntXVT = MVT::getIntegerVT(OrigXWidth);
+ EVT IntXVT = EVT::getIntegerVT(OrigXWidth);
if (TLI.isTypeLegal(IntXVT) || !LegalTypes) {
SDValue X = DAG.getNode(ISD::BIT_CONVERT, N0.getDebugLoc(),
IntXVT, N0.getOperand(1));
@@ -3828,7 +3828,7 @@
}
SDValue DAGCombiner::visitBUILD_PAIR(SDNode *N) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
return CombineConsecutiveLoads(N, VT);
}
@@ -3836,8 +3836,8 @@
/// node with Constant, ConstantFP or Undef operands. DstEltVT indicates the
/// destination element value type.
SDValue DAGCombiner::
-ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, MVT DstEltVT) {
- MVT SrcEltVT = BV->getValueType(0).getVectorElementType();
+ConstantFoldBIT_CONVERTofBUILD_VECTOR(SDNode *BV, EVT DstEltVT) {
+ EVT SrcEltVT = BV->getValueType(0).getVectorElementType();
// If this is already the right type, we're done.
if (SrcEltVT == DstEltVT) return SDValue(BV, 0);
@@ -3859,7 +3859,7 @@
DstEltVT, Op));
AddToWorkList(Ops.back().getNode());
}
- MVT VT = MVT::getVectorVT(DstEltVT,
+ EVT VT = EVT::getVectorVT(DstEltVT,
BV->getValueType(0).getVectorNumElements());
return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
&Ops[0], Ops.size());
@@ -3871,8 +3871,8 @@
if (SrcEltVT.isFloatingPoint()) {
// Convert the input float vector to a int vector where the elements are the
// same sizes.
- assert((SrcEltVT == MVT::f32 || SrcEltVT == MVT::f64) && "Unknown FP VT!");
- MVT IntVT = MVT::getIntegerVT(SrcEltVT.getSizeInBits());
+ assert((SrcEltVT == EVT::f32 || SrcEltVT == EVT::f64) && "Unknown FP VT!");
+ EVT IntVT = EVT::getIntegerVT(SrcEltVT.getSizeInBits());
BV = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, IntVT).getNode();
SrcEltVT = IntVT;
}
@@ -3880,8 +3880,8 @@
// Now we know the input is an integer vector. If the output is a FP type,
// convert to integer first, then to FP of the right size.
if (DstEltVT.isFloatingPoint()) {
- assert((DstEltVT == MVT::f32 || DstEltVT == MVT::f64) && "Unknown FP VT!");
- MVT TmpVT = MVT::getIntegerVT(DstEltVT.getSizeInBits());
+ assert((DstEltVT == EVT::f32 || DstEltVT == EVT::f64) && "Unknown FP VT!");
+ EVT TmpVT = EVT::getIntegerVT(DstEltVT.getSizeInBits());
SDNode *Tmp = ConstantFoldBIT_CONVERTofBUILD_VECTOR(BV, TmpVT).getNode();
// Next, convert to FP elements of the same size.
@@ -3917,7 +3917,7 @@
Ops.push_back(DAG.getConstant(NewBits, DstEltVT));
}
- MVT VT = MVT::getVectorVT(DstEltVT, Ops.size());
+ EVT VT = EVT::getVectorVT(DstEltVT, Ops.size());
return DAG.getNode(ISD::BUILD_VECTOR, BV->getDebugLoc(), VT,
&Ops[0], Ops.size());
}
@@ -3926,7 +3926,7 @@
// turns into multiple outputs.
bool isS2V = ISD::isScalarToVector(BV);
unsigned NumOutputsPerInput = SrcBitSize/DstBitSize;
- MVT VT = MVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands());
+ EVT VT = EVT::getVectorVT(DstEltVT, NumOutputsPerInput*BV->getNumOperands());
SmallVector<SDValue, 8> Ops;
for (unsigned i = 0, e = BV->getNumOperands(); i != e; ++i) {
@@ -3963,7 +3963,7 @@
SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold vector ops
if (VT.isVector()) {
@@ -3972,7 +3972,7 @@
}
// fold (fadd c1, c2) -> (fadd c1, c2)
- if (N0CFP && N1CFP && VT != MVT::ppcf128)
+ if (N0CFP && N1CFP && VT != EVT::ppcf128)
return DAG.getNode(ISD::FADD, N->getDebugLoc(), VT, N0, N1);
// canonicalize constant to RHS
if (N0CFP && !N1CFP)
@@ -4004,7 +4004,7 @@
SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold vector ops
if (VT.isVector()) {
@@ -4013,7 +4013,7 @@
}
// fold (fsub c1, c2) -> c1-c2
- if (N0CFP && N1CFP && VT != MVT::ppcf128)
+ if (N0CFP && N1CFP && VT != EVT::ppcf128)
return DAG.getNode(ISD::FSUB, N->getDebugLoc(), VT, N0, N1);
// fold (fsub A, 0) -> A
if (UnsafeFPMath && N1CFP && N1CFP->getValueAPF().isZero())
@@ -4038,7 +4038,7 @@
SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold vector ops
if (VT.isVector()) {
@@ -4047,7 +4047,7 @@
}
// fold (fmul c1, c2) -> c1*c2
- if (N0CFP && N1CFP && VT != MVT::ppcf128)
+ if (N0CFP && N1CFP && VT != EVT::ppcf128)
return DAG.getNode(ISD::FMUL, N->getDebugLoc(), VT, N0, N1);
// canonicalize constant to RHS
if (N0CFP && !N1CFP)
@@ -4093,7 +4093,7 @@
SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold vector ops
if (VT.isVector()) {
@@ -4102,7 +4102,7 @@
}
// fold (fdiv c1, c2) -> c1/c2
- if (N0CFP && N1CFP && VT != MVT::ppcf128)
+ if (N0CFP && N1CFP && VT != EVT::ppcf128)
return DAG.getNode(ISD::FDIV, N->getDebugLoc(), VT, N0, N1);
@@ -4126,10 +4126,10 @@
SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (frem c1, c2) -> fmod(c1,c2)
- if (N0CFP && N1CFP && VT != MVT::ppcf128)
+ if (N0CFP && N1CFP && VT != EVT::ppcf128)
return DAG.getNode(ISD::FREM, N->getDebugLoc(), VT, N0, N1);
return SDValue();
@@ -4140,9 +4140,9 @@
SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
ConstantFPSDNode *N1CFP = dyn_cast<ConstantFPSDNode>(N1);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
- if (N0CFP && N1CFP && VT != MVT::ppcf128) // Constant fold
+ if (N0CFP && N1CFP && VT != EVT::ppcf128) // Constant fold
return DAG.getNode(ISD::FCOPYSIGN, N->getDebugLoc(), VT, N0, N1);
if (N1CFP) {
@@ -4188,11 +4188,11 @@
SDValue DAGCombiner::visitSINT_TO_FP(SDNode *N) {
SDValue N0 = N->getOperand(0);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
- MVT VT = N->getValueType(0);
- MVT OpVT = N0.getValueType();
+ EVT VT = N->getValueType(0);
+ EVT OpVT = N0.getValueType();
// fold (sint_to_fp c1) -> c1fp
- if (N0C && OpVT != MVT::ppcf128)
+ if (N0C && OpVT != EVT::ppcf128)
return DAG.getNode(ISD::SINT_TO_FP, N->getDebugLoc(), VT, N0);
// If the input is a legal type, and SINT_TO_FP is not legal on this target,
@@ -4210,11 +4210,11 @@
SDValue DAGCombiner::visitUINT_TO_FP(SDNode *N) {
SDValue N0 = N->getOperand(0);
ConstantSDNode *N0C = dyn_cast<ConstantSDNode>(N0);
- MVT VT = N->getValueType(0);
- MVT OpVT = N0.getValueType();
+ EVT VT = N->getValueType(0);
+ EVT OpVT = N0.getValueType();
// fold (uint_to_fp c1) -> c1fp
- if (N0C && OpVT != MVT::ppcf128)
+ if (N0C && OpVT != EVT::ppcf128)
return DAG.getNode(ISD::UINT_TO_FP, N->getDebugLoc(), VT, N0);
// If the input is a legal type, and UINT_TO_FP is not legal on this target,
@@ -4232,7 +4232,7 @@
SDValue DAGCombiner::visitFP_TO_SINT(SDNode *N) {
SDValue N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (fp_to_sint c1fp) -> c1
if (N0CFP)
@@ -4244,10 +4244,10 @@
SDValue DAGCombiner::visitFP_TO_UINT(SDNode *N) {
SDValue N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (fp_to_uint c1fp) -> c1
- if (N0CFP && VT != MVT::ppcf128)
+ if (N0CFP && VT != EVT::ppcf128)
return DAG.getNode(ISD::FP_TO_UINT, N->getDebugLoc(), VT, N0);
return SDValue();
@@ -4257,10 +4257,10 @@
SDValue N0 = N->getOperand(0);
SDValue N1 = N->getOperand(1);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (fp_round c1fp) -> c1fp
- if (N0CFP && N0.getValueType() != MVT::ppcf128)
+ if (N0CFP && N0.getValueType() != EVT::ppcf128)
return DAG.getNode(ISD::FP_ROUND, N->getDebugLoc(), VT, N0, N1);
// fold (fp_round (fp_extend x)) -> x
@@ -4290,8 +4290,8 @@
SDValue DAGCombiner::visitFP_ROUND_INREG(SDNode *N) {
SDValue N0 = N->getOperand(0);
- MVT VT = N->getValueType(0);
- MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
+ EVT VT = N->getValueType(0);
+ EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
// fold (fp_round_inreg c1fp) -> c1fp
@@ -4306,7 +4306,7 @@
SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
SDValue N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
if (N->hasOneUse() &&
@@ -4314,7 +4314,7 @@
return SDValue();
// fold (fp_extend c1fp) -> c1fp
- if (N0CFP && VT != MVT::ppcf128)
+ if (N0CFP && VT != EVT::ppcf128)
return DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), VT, N0);
// Turn fp_extend(fp_round(X, 1)) -> x since the fp_round doesn't affect the
@@ -4363,7 +4363,7 @@
N0.getOperand(0).getValueType().isInteger() &&
!N0.getOperand(0).getValueType().isVector()) {
SDValue Int = N0.getOperand(0);
- MVT IntVT = Int.getValueType();
+ EVT IntVT = Int.getValueType();
if (IntVT.isInteger() && !IntVT.isVector()) {
Int = DAG.getNode(ISD::XOR, N0.getDebugLoc(), IntVT, Int,
DAG.getConstant(APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
@@ -4379,10 +4379,10 @@
SDValue DAGCombiner::visitFABS(SDNode *N) {
SDValue N0 = N->getOperand(0);
ConstantFPSDNode *N0CFP = dyn_cast<ConstantFPSDNode>(N0);
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// fold (fabs c1) -> fabs(c1)
- if (N0CFP && VT != MVT::ppcf128)
+ if (N0CFP && VT != EVT::ppcf128)
return DAG.getNode(ISD::FABS, N->getDebugLoc(), VT, N0);
// fold (fabs (fabs x)) -> (fabs x)
if (N0.getOpcode() == ISD::FABS)
@@ -4398,7 +4398,7 @@
N0.getOperand(0).getValueType().isInteger() &&
!N0.getOperand(0).getValueType().isVector()) {
SDValue Int = N0.getOperand(0);
- MVT IntVT = Int.getValueType();
+ EVT IntVT = Int.getValueType();
if (IntVT.isInteger() && !IntVT.isVector()) {
Int = DAG.getNode(ISD::AND, N0.getDebugLoc(), IntVT, Int,
DAG.getConstant(~APInt::getSignBit(IntVT.getSizeInBits()), IntVT));
@@ -4422,12 +4422,12 @@
return Chain;
// unconditional branch
if (N1C && N1C->getAPIntValue() == 1)
- return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other, Chain, N2);
+ return DAG.getNode(ISD::BR, N->getDebugLoc(), EVT::Other, Chain, N2);
// fold a brcond with a setcc condition into a BR_CC node if BR_CC is legal
// on the target.
if (N1.getOpcode() == ISD::SETCC &&
- TLI.isOperationLegalOrCustom(ISD::BR_CC, MVT::Other)) {
- return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
+ TLI.isOperationLegalOrCustom(ISD::BR_CC, EVT::Other)) {
+ return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), EVT::Other,
Chain, N1.getOperand(2),
N1.getOperand(0), N1.getOperand(1), N2);
}
@@ -4475,7 +4475,7 @@
removeFromWorkList(N1.getNode());
DAG.DeleteNode(N1.getNode());
return DAG.getNode(ISD::BRCOND, N->getDebugLoc(),
- MVT::Other, Chain, SetCC, N2);
+ EVT::Other, Chain, SetCC, N2);
}
}
}
@@ -4500,7 +4500,7 @@
// fold br_cc true, dest -> br dest (unconditional branch)
if (SCCC && !SCCC->isNullValue())
- return DAG.getNode(ISD::BR, N->getDebugLoc(), MVT::Other,
+ return DAG.getNode(ISD::BR, N->getDebugLoc(), EVT::Other,
N->getOperand(0), N->getOperand(4));
// fold br_cc false, dest -> unconditional fall through
if (SCCC && SCCC->isNullValue())
@@ -4508,7 +4508,7 @@
// fold to a simpler setcc
if (Simp.getNode() && Simp.getOpcode() == ISD::SETCC)
- return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), MVT::Other,
+ return DAG.getNode(ISD::BR_CC, N->getDebugLoc(), EVT::Other,
N->getOperand(0), Simp.getOperand(2),
Simp.getOperand(0), Simp.getOperand(1),
N->getOperand(4));
@@ -4528,7 +4528,7 @@
bool isLoad = true;
SDValue Ptr;
- MVT VT;
+ EVT VT;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
if (LD->isIndexed())
return false;
@@ -4653,7 +4653,7 @@
bool isLoad = true;
SDValue Ptr;
- MVT VT;
+ EVT VT;
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
if (LD->isIndexed())
return false;
@@ -4843,7 +4843,7 @@
// the updated indexed value in case of indexed loads), change uses of the
// chain value into uses of the chain input (i.e. delete the dead load).
if (!LD->isVolatile()) {
- if (N->getValueType(1) == MVT::Other) {
+ if (N->getValueType(1) == EVT::Other) {
// Unindexed loads.
if (N->hasNUsesOfValue(0, 0)) {
// It's not safe to use the two value CombineTo variant here. e.g.
@@ -4867,7 +4867,7 @@
}
} else {
// Indexed loads.
- assert(N->getValueType(2) == MVT::Other && "Malformed indexed loads?");
+ assert(N->getValueType(2) == EVT::Other && "Malformed indexed loads?");
if (N->hasNUsesOfValue(0, 0) && N->hasNUsesOfValue(0, 1)) {
SDValue Undef = DAG.getUNDEF(N->getValueType(0));
DOUT << "\nReplacing.6 "; DEBUG(N->dump(&DAG));
@@ -4926,7 +4926,7 @@
// Create token factor to keep old chain connected.
SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
- MVT::Other, Chain, ReplLoad.getValue(1));
+ EVT::Other, Chain, ReplLoad.getValue(1));
// Replace uses with load result and token factor. Don't add users
// to work list.
@@ -4954,7 +4954,7 @@
SDValue Chain = ST->getChain();
SDValue Value = ST->getValue();
SDValue Ptr = ST->getBasePtr();
- MVT VT = Value.getValueType();
+ EVT VT = Value.getValueType();
if (ST->isTruncatingStore() || VT.isVector() || !Value.hasOneUse())
return SDValue();
@@ -4981,12 +4981,12 @@
unsigned ShAmt = Imm.countTrailingZeros();
unsigned MSB = BitWidth - Imm.countLeadingZeros() - 1;
unsigned NewBW = NextPowerOf2(MSB - ShAmt);
- MVT NewVT = MVT::getIntegerVT(NewBW);
+ EVT NewVT = EVT::getIntegerVT(NewBW);
while (NewBW < BitWidth &&
!(TLI.isOperationLegalOrCustom(Opc, NewVT) &&
TLI.isNarrowingProfitable(VT, NewVT))) {
NewBW = NextPowerOf2(NewBW);
- NewVT = MVT::getIntegerVT(NewBW);
+ NewVT = EVT::getIntegerVT(NewBW);
}
if (NewBW >= BitWidth)
return SDValue();
@@ -5008,7 +5008,7 @@
unsigned NewAlign = MinAlign(LD->getAlignment(), PtrOff);
if (NewAlign <
- TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForMVT()))
+ TLI.getTargetData()->getABITypeAlignment(NewVT.getTypeForEVT()))
return SDValue();
SDValue NewPtr = DAG.getNode(ISD::ADD, LD->getDebugLoc(),
@@ -5061,9 +5061,9 @@
if (Value.getOpcode() == ISD::BIT_CONVERT && !ST->isTruncatingStore() &&
ST->isUnindexed()) {
unsigned OrigAlign = ST->getAlignment();
- MVT SVT = Value.getOperand(0).getValueType();
+ EVT SVT = Value.getOperand(0).getValueType();
unsigned Align = TLI.getTargetData()->
- getABITypeAlignment(SVT.getTypeForMVT());
+ getABITypeAlignment(SVT.getTypeForEVT());
if (Align <= OrigAlign &&
((!LegalOperations && !ST->isVolatile()) ||
TLI.isOperationLegalOrCustom(ISD::STORE, SVT)))
@@ -5082,40 +5082,40 @@
SDValue Tmp;
switch (CFP->getValueType(0).getSimpleVT()) {
default: llvm_unreachable("Unknown FP type");
- case MVT::f80: // We don't do this for these yet.
- case MVT::f128:
- case MVT::ppcf128:
+ case EVT::f80: // We don't do this for these yet.
+ case EVT::f128:
+ case EVT::ppcf128:
break;
- case MVT::f32:
- if (((TLI.isTypeLegal(MVT::i32) || !LegalTypes) && !LegalOperations &&
+ case EVT::f32:
+ if (((TLI.isTypeLegal(EVT::i32) || !LegalTypes) && !LegalOperations &&
!ST->isVolatile()) ||
- TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
+ TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i32)) {
Tmp = DAG.getConstant((uint32_t)CFP->getValueAPF().
- bitcastToAPInt().getZExtValue(), MVT::i32);
+ bitcastToAPInt().getZExtValue(), EVT::i32);
return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
Ptr, ST->getSrcValue(),
ST->getSrcValueOffset(), ST->isVolatile(),
ST->getAlignment());
}
break;
- case MVT::f64:
- if (((TLI.isTypeLegal(MVT::i64) || !LegalTypes) && !LegalOperations &&
+ case EVT::f64:
+ if (((TLI.isTypeLegal(EVT::i64) || !LegalTypes) && !LegalOperations &&
!ST->isVolatile()) ||
- TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i64)) {
+ TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i64)) {
Tmp = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
- getZExtValue(), MVT::i64);
+ getZExtValue(), EVT::i64);
return DAG.getStore(Chain, N->getDebugLoc(), Tmp,
Ptr, ST->getSrcValue(),
ST->getSrcValueOffset(), ST->isVolatile(),
ST->getAlignment());
} else if (!ST->isVolatile() &&
- TLI.isOperationLegalOrCustom(ISD::STORE, MVT::i32)) {
+ TLI.isOperationLegalOrCustom(ISD::STORE, EVT::i32)) {
// Many FP stores are not made apparent until after legalize, e.g. for
// argument passing. Since this is so common, custom legalize the
// 64-bit integer store into two 32-bit stores.
uint64_t Val = CFP->getValueAPF().bitcastToAPInt().getZExtValue();
- SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, MVT::i32);
- SDValue Hi = DAG.getConstant(Val >> 32, MVT::i32);
+ SDValue Lo = DAG.getConstant(Val & 0xFFFFFFFF, EVT::i32);
+ SDValue Hi = DAG.getConstant(Val >> 32, EVT::i32);
if (TLI.isBigEndian()) std::swap(Lo, Hi);
int SVOffset = ST->getSrcValueOffset();
@@ -5133,7 +5133,7 @@
SDValue St1 = DAG.getStore(Chain, ST->getDebugLoc(), Hi,
Ptr, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
- return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
+ return DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), EVT::Other,
St0, St1);
}
@@ -5163,7 +5163,7 @@
// Create token to keep both nodes around.
SDValue Token = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(),
- MVT::Other, Chain, ReplStore);
+ EVT::Other, Chain, ReplStore);
// Don't add users to work list.
return CombineTo(N, Token, false);
@@ -5248,8 +5248,8 @@
// BUILD_VECTOR with undef elements and the inserted element.
if (!LegalOperations && InVec.getOpcode() == ISD::UNDEF &&
isa<ConstantSDNode>(EltNo)) {
- MVT VT = InVec.getValueType();
- MVT EVT = VT.getVectorElementType();
+ EVT VT = InVec.getValueType();
+ EVT EVT = VT.getVectorElementType();
unsigned NElts = VT.getVectorNumElements();
SmallVector<SDValue, 8> Ops(NElts, DAG.getUNDEF(EVT));
@@ -5269,7 +5269,7 @@
if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR) {
// If the operand is wider than the vector element type then it is implicitly
// truncated. Make that explicit here.
- MVT EltVT = InVec.getValueType().getVectorElementType();
+ EVT EltVT = InVec.getValueType().getVectorElementType();
SDValue InOp = InVec.getOperand(0);
if (InOp.getValueType() != EltVT)
return DAG.getNode(ISD::TRUNCATE, InVec.getDebugLoc(), EltVT, InOp);
@@ -5289,18 +5289,18 @@
unsigned Elt = cast<ConstantSDNode>(EltNo)->getZExtValue();
bool NewLoad = false;
bool BCNumEltsChanged = false;
- MVT VT = InVec.getValueType();
- MVT EVT = VT.getVectorElementType();
- MVT LVT = EVT;
+ EVT VT = InVec.getValueType();
+ EVT ExtVT = VT.getVectorElementType();
+ EVT LVT = ExtVT;
if (InVec.getOpcode() == ISD::BIT_CONVERT) {
- MVT BCVT = InVec.getOperand(0).getValueType();
- if (!BCVT.isVector() || EVT.bitsGT(BCVT.getVectorElementType()))
+ EVT BCVT = InVec.getOperand(0).getValueType();
+ if (!BCVT.isVector() || ExtVT.bitsGT(BCVT.getVectorElementType()))
return SDValue();
if (VT.getVectorNumElements() != BCVT.getVectorNumElements())
BCNumEltsChanged = true;
InVec = InVec.getOperand(0);
- EVT = BCVT.getVectorElementType();
+ ExtVT = BCVT.getVectorElementType();
NewLoad = true;
}
@@ -5309,7 +5309,7 @@
if (ISD::isNormalLoad(InVec.getNode())) {
LN0 = cast<LoadSDNode>(InVec);
} else if (InVec.getOpcode() == ISD::SCALAR_TO_VECTOR &&
- InVec.getOperand(0).getValueType() == EVT &&
+ InVec.getOperand(0).getValueType() == ExtVT &&
ISD::isNormalLoad(InVec.getOperand(0).getNode())) {
LN0 = cast<LoadSDNode>(InVec.getOperand(0));
} else if ((SVN = dyn_cast<ShuffleVectorSDNode>(InVec))) {
@@ -5343,7 +5343,7 @@
// Check the resultant load doesn't need a higher alignment than the
// original load.
unsigned NewAlign =
- TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForMVT());
+ TLI.getTargetData()->getABITypeAlignment(LVT.getTypeForEVT());
if (NewAlign > Align || !TLI.isOperationLegalOrCustom(ISD::LOAD, LVT))
return SDValue();
@@ -5354,7 +5354,7 @@
SDValue NewPtr = LN0->getBasePtr();
if (Elt) {
unsigned PtrOff = LVT.getSizeInBits() * Elt / 8;
- MVT PtrType = NewPtr.getValueType();
+ EVT PtrType = NewPtr.getValueType();
if (TLI.isBigEndian())
PtrOff = VT.getSizeInBits() / 8 - PtrOff;
NewPtr = DAG.getNode(ISD::ADD, N->getDebugLoc(), PtrType, NewPtr,
@@ -5371,8 +5371,8 @@
SDValue DAGCombiner::visitBUILD_VECTOR(SDNode *N) {
unsigned NumInScalars = N->getNumOperands();
- MVT VT = N->getValueType(0);
- MVT EltType = VT.getVectorElementType();
+ EVT VT = N->getValueType(0);
+ EVT EltType = VT.getVectorElementType();
// Check to see if this is a BUILD_VECTOR of a bunch of EXTRACT_VECTOR_ELT
// operations. If so, and if the EXTRACT_VECTOR_ELT vector inputs come from
@@ -5469,7 +5469,7 @@
SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
return SDValue();
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
unsigned NumElts = VT.getVectorNumElements();
SDValue N0 = N->getOperand(0);
@@ -5531,7 +5531,7 @@
/// e.g. AND V, <0xffffffff, 0, 0xffffffff, 0>. ==>
/// vector_shuffle V, Zero, <0, 4, 2, 4>
SDValue DAGCombiner::XformToShuffleWithZero(SDNode *N) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
@@ -5554,12 +5554,12 @@
}
// Let's see if the target supports this vector_shuffle.
- MVT RVT = RHS.getValueType();
+ EVT RVT = RHS.getValueType();
if (!TLI.isVectorClearMaskLegal(Indices, RVT))
return SDValue();
// Return the new VECTOR_SHUFFLE node.
- MVT EVT = RVT.getVectorElementType();
+ EVT EVT = RVT.getVectorElementType();
SmallVector<SDValue,8> ZeroOps(RVT.getVectorNumElements(),
DAG.getConstant(0, EVT));
SDValue Zero = DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(),
@@ -5580,10 +5580,10 @@
// things. Simplifying them may result in a loss of legality.
if (LegalOperations) return SDValue();
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
assert(VT.isVector() && "SimplifyVBinOp only works on vectors!");
- MVT EltType = VT.getVectorElementType();
+ EVT EltType = VT.getVectorElementType();
SDValue LHS = N->getOperand(0);
SDValue RHS = N->getOperand(1);
SDValue Shuffle = XformToShuffleWithZero(N);
@@ -5626,7 +5626,7 @@
}
if (Ops.size() == LHS.getNumOperands()) {
- MVT VT = LHS.getValueType();
+ EVT VT = LHS.getValueType();
return DAG.getNode(ISD::BUILD_VECTOR, N->getDebugLoc(), VT,
&Ops[0], Ops.size());
}
@@ -5765,7 +5765,7 @@
// (x ? y : y) -> y.
if (N2 == N3) return N2;
- MVT VT = N2.getValueType();
+ EVT VT = N2.getValueType();
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
ConstantSDNode *N3C = dyn_cast<ConstantSDNode>(N3.getNode());
@@ -5857,8 +5857,8 @@
N2.getValueType().isInteger() &&
(N1C->isNullValue() || // (a < 0) ? b : 0
(N1C->getAPIntValue() == 1 && N0 == N2))) { // (a < 1) ? a : 0
- MVT XType = N0.getValueType();
- MVT AType = N2.getValueType();
+ EVT XType = N0.getValueType();
+ EVT AType = N2.getValueType();
if (XType.bitsGE(AType)) {
// and (sra X, size(X)-1, A) -> "and (srl X, C2), A" iff A is a
// single-bit constant.
@@ -5916,7 +5916,7 @@
Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
N2.getValueType(), SCC);
} else {
- SCC = DAG.getSetCC(N0.getDebugLoc(), MVT::i1, N0, N1, CC);
+ SCC = DAG.getSetCC(N0.getDebugLoc(), EVT::i1, N0, N1, CC);
Temp = DAG.getNode(ISD::ZERO_EXTEND, N2.getDebugLoc(),
N2.getValueType(), SCC);
}
@@ -5937,7 +5937,7 @@
// FIXME: Turn all of these into setcc if setcc if setcc is legal
// otherwise, go ahead with the folds.
if (0 && N3C && N3C->isNullValue() && N2C && (N2C->getAPIntValue() == 1ULL)) {
- MVT XType = N0.getValueType();
+ EVT XType = N0.getValueType();
if (!LegalOperations ||
TLI.isOperationLegal(ISD::SETCC, TLI.getSetCCResultType(XType))) {
SDValue Res = DAG.getSetCC(DL, TLI.getSetCCResultType(XType), N0, N1, CC);
@@ -5979,7 +5979,7 @@
if (N1C && N1C->isNullValue() && (CC == ISD::SETLT || CC == ISD::SETLE) &&
N0 == N3 && N2.getOpcode() == ISD::SUB && N0 == N2.getOperand(1) &&
N2.getOperand(0) == N1 && N0.getValueType().isInteger()) {
- MVT XType = N0.getValueType();
+ EVT XType = N0.getValueType();
SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType, N0,
DAG.getConstant(XType.getSizeInBits()-1,
getShiftAmountTy()));
@@ -5994,7 +5994,7 @@
if (N1C && N1C->isAllOnesValue() && CC == ISD::SETGT &&
N0 == N2 && N3.getOpcode() == ISD::SUB && N0 == N3.getOperand(1)) {
if (ConstantSDNode *SubC = dyn_cast<ConstantSDNode>(N3.getOperand(0))) {
- MVT XType = N0.getValueType();
+ EVT XType = N0.getValueType();
if (SubC->isNullValue() && XType.isInteger()) {
SDValue Shift = DAG.getNode(ISD::SRA, N0.getDebugLoc(), XType,
N0,
@@ -6013,7 +6013,7 @@
}
/// SimplifySetCC - This is a stub for TargetLowering::SimplifySetCC.
-SDValue DAGCombiner::SimplifySetCC(MVT VT, SDValue N0,
+SDValue DAGCombiner::SimplifySetCC(EVT VT, SDValue N0,
SDValue N1, ISD::CondCode Cond,
DebugLoc DL, bool foldBooleans) {
TargetLowering::DAGCombinerInfo
@@ -6223,7 +6223,7 @@
}
// Construct a custom tailored token factor.
- SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), MVT::Other,
+ SDValue NewChain = DAG.getNode(ISD::TokenFactor, N->getDebugLoc(), EVT::Other,
&Aliases[0], Aliases.size());
// Make sure the old chain gets cleaned up.
diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index e3eed28..f4edc1a 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -57,7 +57,7 @@
using namespace llvm;
unsigned FastISel::getRegForValue(Value *V) {
- MVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
+ EVT RealVT = TLI.getValueType(V->getType(), /*AllowUnknown=*/true);
// Don't handle non-simple values in FastISel.
if (!RealVT.isSimple())
return 0;
@@ -65,10 +65,10 @@
// Ignore illegal types. We must do this before looking up the value
// in ValueMap because Arguments are given virtual registers regardless
// of whether FastISel can handle them.
- MVT::SimpleValueType VT = RealVT.getSimpleVT();
+ EVT::SimpleValueType VT = RealVT.getSimpleVT();
if (!TLI.isTypeLegal(VT)) {
- // Promote MVT::i1 to a legal type though, because it's common and easy.
- if (VT == MVT::i1)
+ // Promote EVT::i1 to a legal type though, because it's common and easy.
+ if (VT == EVT::i1)
VT = TLI.getTypeToTransformTo(VT).getSimpleVT();
else
return 0;
@@ -98,7 +98,7 @@
if (!Reg) {
const APFloat &Flt = CF->getValueAPF();
- MVT IntVT = TLI.getPointerTy();
+ EVT IntVT = TLI.getPointerTy();
uint64_t x[2];
uint32_t IntBitWidth = IntVT.getSizeInBits();
@@ -174,8 +174,8 @@
return 0;
// If the index is smaller or larger than intptr_t, truncate or extend it.
- MVT PtrVT = TLI.getPointerTy();
- MVT IdxVT = MVT::getMVT(Idx->getType(), /*HandleUnknown=*/false);
+ EVT PtrVT = TLI.getPointerTy();
+ EVT IdxVT = EVT::getEVT(Idx->getType(), /*HandleUnknown=*/false);
if (IdxVT.bitsLT(PtrVT))
IdxN = FastEmit_r(IdxVT.getSimpleVT(), PtrVT.getSimpleVT(),
ISD::SIGN_EXTEND, IdxN);
@@ -189,8 +189,8 @@
/// which has an opcode which directly corresponds to the given ISD opcode.
///
bool FastISel::SelectBinaryOp(User *I, ISD::NodeType ISDOpcode) {
- MVT VT = MVT::getMVT(I->getType(), /*HandleUnknown=*/true);
- if (VT == MVT::Other || !VT.isSimple())
+ EVT VT = EVT::getEVT(I->getType(), /*HandleUnknown=*/true);
+ if (VT == EVT::Other || !VT.isSimple())
// Unhandled type. Halt "fast" selection and bail.
return false;
@@ -199,9 +199,9 @@
// under the assumption that i64 won't be used if the target doesn't
// support it.
if (!TLI.isTypeLegal(VT)) {
- // MVT::i1 is special. Allow AND, OR, or XOR because they
+ // EVT::i1 is special. Allow AND, OR, or XOR because they
// don't require additional zeroing, which makes them easy.
- if (VT == MVT::i1 &&
+ if (VT == EVT::i1 &&
(ISDOpcode == ISD::AND || ISDOpcode == ISD::OR ||
ISDOpcode == ISD::XOR))
VT = TLI.getTypeToTransformTo(VT);
@@ -261,7 +261,7 @@
return false;
const Type *Ty = I->getOperand(0)->getType();
- MVT::SimpleValueType VT = TLI.getPointerTy();
+ EVT::SimpleValueType VT = TLI.getPointerTy();
for (GetElementPtrInst::op_iterator OI = I->op_begin()+1, E = I->op_end();
OI != E; ++OI) {
Value *Idx = *OI;
@@ -432,7 +432,7 @@
return true;
}
case Intrinsic::eh_exception: {
- MVT VT = TLI.getValueType(I->getType());
+ EVT VT = TLI.getValueType(I->getType());
switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
default: break;
case TargetLowering::Expand: {
@@ -452,12 +452,12 @@
}
case Intrinsic::eh_selector_i32:
case Intrinsic::eh_selector_i64: {
- MVT VT = TLI.getValueType(I->getType());
+ EVT VT = TLI.getValueType(I->getType());
switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
default: break;
case TargetLowering::Expand: {
- MVT VT = (IID == Intrinsic::eh_selector_i32 ?
- MVT::i32 : MVT::i64);
+ EVT VT = (IID == Intrinsic::eh_selector_i32 ?
+ EVT::i32 : EVT::i64);
if (MMI) {
if (MBB->isLandingPad())
@@ -494,11 +494,11 @@
}
bool FastISel::SelectCast(User *I, ISD::NodeType Opcode) {
- MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
- MVT DstVT = TLI.getValueType(I->getType());
+ EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
+ EVT DstVT = TLI.getValueType(I->getType());
- if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
- DstVT == MVT::Other || !DstVT.isSimple())
+ if (SrcVT == EVT::Other || !SrcVT.isSimple() ||
+ DstVT == EVT::Other || !DstVT.isSimple())
// Unhandled type. Halt "fast" selection and bail.
return false;
@@ -506,7 +506,7 @@
// it may be i1 if we're doing a truncate because that's
// easy and somewhat common.
if (!TLI.isTypeLegal(DstVT))
- if (DstVT != MVT::i1 || Opcode != ISD::TRUNCATE)
+ if (DstVT != EVT::i1 || Opcode != ISD::TRUNCATE)
// Unhandled type. Halt "fast" selection and bail.
return false;
@@ -514,7 +514,7 @@
// it may be i1 if we're doing zero-extension because that's
// easy and somewhat common.
if (!TLI.isTypeLegal(SrcVT))
- if (SrcVT != MVT::i1 || Opcode != ISD::ZERO_EXTEND)
+ if (SrcVT != EVT::i1 || Opcode != ISD::ZERO_EXTEND)
// Unhandled type. Halt "fast" selection and bail.
return false;
@@ -524,14 +524,14 @@
return false;
// If the operand is i1, arrange for the high bits in the register to be zero.
- if (SrcVT == MVT::i1) {
+ if (SrcVT == EVT::i1) {
SrcVT = TLI.getTypeToTransformTo(SrcVT);
InputReg = FastEmitZExtFromI1(SrcVT.getSimpleVT(), InputReg);
if (!InputReg)
return false;
}
// If the result is i1, truncate to the target's type for i1 first.
- if (DstVT == MVT::i1)
+ if (DstVT == EVT::i1)
DstVT = TLI.getTypeToTransformTo(DstVT);
unsigned ResultReg = FastEmit_r(SrcVT.getSimpleVT(),
@@ -556,11 +556,11 @@
}
// Bitcasts of other values become reg-reg copies or BIT_CONVERT operators.
- MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
- MVT DstVT = TLI.getValueType(I->getType());
+ EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
+ EVT DstVT = TLI.getValueType(I->getType());
- if (SrcVT == MVT::Other || !SrcVT.isSimple() ||
- DstVT == MVT::Other || !DstVT.isSimple() ||
+ if (SrcVT == EVT::Other || !SrcVT.isSimple() ||
+ DstVT == EVT::Other || !DstVT.isSimple() ||
!TLI.isTypeLegal(SrcVT) || !TLI.isTypeLegal(DstVT))
// Unhandled type. Halt "fast" selection and bail.
return false;
@@ -710,8 +710,8 @@
case Instruction::IntToPtr: // Deliberate fall-through.
case Instruction::PtrToInt: {
- MVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
- MVT DstVT = TLI.getValueType(I->getType());
+ EVT SrcVT = TLI.getValueType(I->getOperand(0)->getType());
+ EVT DstVT = TLI.getValueType(I->getType());
if (DstVT.bitsGT(SrcVT))
return SelectCast(I, ISD::ZERO_EXTEND);
if (DstVT.bitsLT(SrcVT))
@@ -759,45 +759,45 @@
FastISel::~FastISel() {}
-unsigned FastISel::FastEmit_(MVT::SimpleValueType, MVT::SimpleValueType,
+unsigned FastISel::FastEmit_(EVT::SimpleValueType, EVT::SimpleValueType,
ISD::NodeType) {
return 0;
}
-unsigned FastISel::FastEmit_r(MVT::SimpleValueType, MVT::SimpleValueType,
+unsigned FastISel::FastEmit_r(EVT::SimpleValueType, EVT::SimpleValueType,
ISD::NodeType, unsigned /*Op0*/) {
return 0;
}
-unsigned FastISel::FastEmit_rr(MVT::SimpleValueType, MVT::SimpleValueType,
+unsigned FastISel::FastEmit_rr(EVT::SimpleValueType, EVT::SimpleValueType,
ISD::NodeType, unsigned /*Op0*/,
unsigned /*Op0*/) {
return 0;
}
-unsigned FastISel::FastEmit_i(MVT::SimpleValueType, MVT::SimpleValueType,
+unsigned FastISel::FastEmit_i(EVT::SimpleValueType, EVT::SimpleValueType,
ISD::NodeType, uint64_t /*Imm*/) {
return 0;
}
-unsigned FastISel::FastEmit_f(MVT::SimpleValueType, MVT::SimpleValueType,
+unsigned FastISel::FastEmit_f(EVT::SimpleValueType, EVT::SimpleValueType,
ISD::NodeType, ConstantFP * /*FPImm*/) {
return 0;
}
-unsigned FastISel::FastEmit_ri(MVT::SimpleValueType, MVT::SimpleValueType,
+unsigned FastISel::FastEmit_ri(EVT::SimpleValueType, EVT::SimpleValueType,
ISD::NodeType, unsigned /*Op0*/,
uint64_t /*Imm*/) {
return 0;
}
-unsigned FastISel::FastEmit_rf(MVT::SimpleValueType, MVT::SimpleValueType,
+unsigned FastISel::FastEmit_rf(EVT::SimpleValueType, EVT::SimpleValueType,
ISD::NodeType, unsigned /*Op0*/,
ConstantFP * /*FPImm*/) {
return 0;
}
-unsigned FastISel::FastEmit_rri(MVT::SimpleValueType, MVT::SimpleValueType,
+unsigned FastISel::FastEmit_rri(EVT::SimpleValueType, EVT::SimpleValueType,
ISD::NodeType,
unsigned /*Op0*/, unsigned /*Op1*/,
uint64_t /*Imm*/) {
@@ -808,9 +808,9 @@
/// to emit an instruction with an immediate operand using FastEmit_ri.
/// If that fails, it materializes the immediate into a register and try
/// FastEmit_rr instead.
-unsigned FastISel::FastEmit_ri_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
+unsigned FastISel::FastEmit_ri_(EVT::SimpleValueType VT, ISD::NodeType Opcode,
unsigned Op0, uint64_t Imm,
- MVT::SimpleValueType ImmType) {
+ EVT::SimpleValueType ImmType) {
// First check if immediate type is legal. If not, we can't use the ri form.
unsigned ResultReg = FastEmit_ri(VT, VT, Opcode, Op0, Imm);
if (ResultReg != 0)
@@ -825,9 +825,9 @@
/// to emit an instruction with a floating-point immediate operand using
/// FastEmit_rf. If that fails, it materializes the immediate into a register
/// and try FastEmit_rr instead.
-unsigned FastISel::FastEmit_rf_(MVT::SimpleValueType VT, ISD::NodeType Opcode,
+unsigned FastISel::FastEmit_rf_(EVT::SimpleValueType VT, ISD::NodeType Opcode,
unsigned Op0, ConstantFP *FPImm,
- MVT::SimpleValueType ImmType) {
+ EVT::SimpleValueType ImmType) {
// First check if immediate type is legal. If not, we can't use the rf form.
unsigned ResultReg = FastEmit_rf(VT, VT, Opcode, Op0, FPImm);
if (ResultReg != 0)
@@ -843,7 +843,7 @@
// be replaced by code that creates a load from a constant-pool entry,
// which will require some target-specific work.
const APFloat &Flt = FPImm->getValueAPF();
- MVT IntVT = TLI.getPointerTy();
+ EVT IntVT = TLI.getPointerTy();
uint64_t x[2];
uint32_t IntBitWidth = IntVT.getSizeInBits();
@@ -988,7 +988,7 @@
return ResultReg;
}
-unsigned FastISel::FastEmitInst_extractsubreg(MVT::SimpleValueType RetVT,
+unsigned FastISel::FastEmitInst_extractsubreg(EVT::SimpleValueType RetVT,
unsigned Op0, uint32_t Idx) {
const TargetRegisterClass* RC = MRI.getRegClass(Op0);
@@ -1009,6 +1009,6 @@
/// FastEmitZExtFromI1 - Emit MachineInstrs to compute the value of Op
/// with all but the least significant bit set to zero.
-unsigned FastISel::FastEmitZExtFromI1(MVT::SimpleValueType VT, unsigned Op) {
+unsigned FastISel::FastEmitZExtFromI1(EVT::SimpleValueType VT, unsigned Op) {
return FastEmit_ri(VT, VT, ISD::AND, Op, 1);
}
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index 4be5b3d..de445ed 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -100,13 +100,13 @@
/// getTypeAction - Return how we should legalize values of this type, either
/// it is already legal or we need to expand it into multiple registers of
/// smaller integer type, or we need to promote it to a larger type.
- LegalizeAction getTypeAction(MVT VT) const {
+ LegalizeAction getTypeAction(EVT VT) const {
return (LegalizeAction)ValueTypeActions.getTypeAction(VT);
}
/// isTypeLegal - Return true if this type is legal on this target.
///
- bool isTypeLegal(MVT VT) const {
+ bool isTypeLegal(EVT VT) const {
return getTypeAction(VT) == Legal;
}
@@ -133,14 +133,14 @@
/// performs the same shuffe in terms of order or result bytes, but on a type
/// whose vector element type is narrower than the original shuffle type.
/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
- SDValue ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl,
+ SDValue ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
SDValue N1, SDValue N2,
SmallVectorImpl<int> &Mask) const;
bool LegalizeAllNodesNotLeadingTo(SDNode *N, SDNode *Dest,
SmallPtrSet<SDNode*, 32> &NodesLeadingTo);
- void LegalizeSetCCCondCode(MVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
+ void LegalizeSetCCCondCode(EVT VT, SDValue &LHS, SDValue &RHS, SDValue &CC,
DebugLoc dl);
SDValue ExpandLibCall(RTLIB::Libcall LC, SDNode *Node, bool isSigned);
@@ -151,18 +151,18 @@
RTLIB::Libcall Call_I32, RTLIB::Libcall Call_I64,
RTLIB::Libcall Call_I128);
- SDValue EmitStackConvert(SDValue SrcOp, MVT SlotVT, MVT DestVT, DebugLoc dl);
+ SDValue EmitStackConvert(SDValue SrcOp, EVT SlotVT, EVT DestVT, DebugLoc dl);
SDValue ExpandBUILD_VECTOR(SDNode *Node);
SDValue ExpandSCALAR_TO_VECTOR(SDNode *Node);
SDValue ExpandDBG_STOPPOINT(SDNode *Node);
void ExpandDYNAMIC_STACKALLOC(SDNode *Node,
SmallVectorImpl<SDValue> &Results);
SDValue ExpandFCOPYSIGN(SDNode *Node);
- SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, MVT DestVT,
+ SDValue ExpandLegalINT_TO_FP(bool isSigned, SDValue LegalOp, EVT DestVT,
DebugLoc dl);
- SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, MVT DestVT, bool isSigned,
+ SDValue PromoteLegalINT_TO_FP(SDValue LegalOp, EVT DestVT, bool isSigned,
DebugLoc dl);
- SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, MVT DestVT, bool isSigned,
+ SDValue PromoteLegalFP_TO_INT(SDValue LegalOp, EVT DestVT, bool isSigned,
DebugLoc dl);
SDValue ExpandBSWAP(SDValue Op, DebugLoc dl);
@@ -181,10 +181,10 @@
/// whose vector element type is narrower than the original shuffle type.
/// e.g. <v4i32> <0, 1, 0, 1> -> v8i16 <0, 1, 2, 3, 0, 1, 2, 3>
SDValue
-SelectionDAGLegalize::ShuffleWithNarrowerEltType(MVT NVT, MVT VT, DebugLoc dl,
+SelectionDAGLegalize::ShuffleWithNarrowerEltType(EVT NVT, EVT VT, DebugLoc dl,
SDValue N1, SDValue N2,
SmallVectorImpl<int> &Mask) const {
- MVT EltVT = NVT.getVectorElementType();
+ EVT EltVT = NVT.getVectorElementType();
unsigned NumMaskElts = VT.getVectorNumElements();
unsigned NumDestElts = NVT.getVectorNumElements();
unsigned NumEltsGrowth = NumDestElts / NumMaskElts;
@@ -213,7 +213,7 @@
CodeGenOpt::Level ol)
: TLI(dag.getTargetLoweringInfo()), DAG(dag), OptLevel(ol),
ValueTypeActions(TLI.getValueTypeActions()) {
- assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
+ assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE &&
"Too many value types for ValueTypeActions to hold!");
}
@@ -254,19 +254,19 @@
// The chain is usually at the end.
SDValue TheChain(Node, Node->getNumValues()-1);
- if (TheChain.getValueType() != MVT::Other) {
+ if (TheChain.getValueType() != EVT::Other) {
// Sometimes it's at the beginning.
TheChain = SDValue(Node, 0);
- if (TheChain.getValueType() != MVT::Other) {
+ if (TheChain.getValueType() != EVT::Other) {
// Otherwise, hunt for it.
for (unsigned i = 1, e = Node->getNumValues(); i != e; ++i)
- if (Node->getValueType(i) == MVT::Other) {
+ if (Node->getValueType(i) == EVT::Other) {
TheChain = SDValue(Node, i);
break;
}
// Otherwise, we walked into a node without a chain.
- if (TheChain.getValueType() != MVT::Other)
+ if (TheChain.getValueType() != EVT::Other)
return 0;
}
}
@@ -290,7 +290,7 @@
assert(Node && "Didn't find callseq_start for a call??");
if (Node->getOpcode() == ISD::CALLSEQ_START) return Node;
- assert(Node->getOperand(0).getValueType() == MVT::Other &&
+ assert(Node->getOperand(0).getValueType() == EVT::Other &&
"Node doesn't have a token chain argument!");
return FindCallStartFromCallEnd(Node->getOperand(0).getNode());
}
@@ -344,24 +344,24 @@
// double. This shrinks FP constants and canonicalizes them for targets where
// an FP extending load is the same cost as a normal load (such as on the x87
// fp stack or PPC FP unit).
- MVT VT = CFP->getValueType(0);
+ EVT VT = CFP->getValueType(0);
ConstantFP *LLVMC = const_cast<ConstantFP*>(CFP->getConstantFPValue());
if (!UseCP) {
- assert((VT == MVT::f64 || VT == MVT::f32) && "Invalid type expansion");
+ assert((VT == EVT::f64 || VT == EVT::f32) && "Invalid type expansion");
return DAG.getConstant(LLVMC->getValueAPF().bitcastToAPInt(),
- (VT == MVT::f64) ? MVT::i64 : MVT::i32);
+ (VT == EVT::f64) ? EVT::i64 : EVT::i32);
}
- MVT OrigVT = VT;
- MVT SVT = VT;
- while (SVT != MVT::f32) {
- SVT = (MVT::SimpleValueType)(SVT.getSimpleVT() - 1);
+ EVT OrigVT = VT;
+ EVT SVT = VT;
+ while (SVT != EVT::f32) {
+ SVT = (EVT::SimpleValueType)(SVT.getSimpleVT() - 1);
if (CFP->isValueValidForType(SVT, CFP->getValueAPF()) &&
// Only do this if the target has a native EXTLOAD instruction from
// smaller type.
TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) &&
TLI.ShouldShrinkFPConstant(OrigVT)) {
- const Type *SType = SVT.getTypeForMVT();
+ const Type *SType = SVT.getTypeForEVT();
LLVMC = cast<ConstantFP>(ConstantExpr::getFPTrunc(LLVMC, SType));
VT = SVT;
Extend = true;
@@ -386,13 +386,13 @@
SDValue Chain = ST->getChain();
SDValue Ptr = ST->getBasePtr();
SDValue Val = ST->getValue();
- MVT VT = Val.getValueType();
+ EVT VT = Val.getValueType();
int Alignment = ST->getAlignment();
int SVOffset = ST->getSrcValueOffset();
DebugLoc dl = ST->getDebugLoc();
if (ST->getMemoryVT().isFloatingPoint() ||
ST->getMemoryVT().isVector()) {
- MVT intVT = MVT::getIntegerVT(VT.getSizeInBits());
+ EVT intVT = EVT::getIntegerVT(VT.getSizeInBits());
if (TLI.isTypeLegal(intVT)) {
// Expand to a bitconvert of the value to the integer type of the
// same size, then a (misaligned) int store.
@@ -403,9 +403,9 @@
} else {
// Do a (aligned) store to a stack slot, then copy from the stack slot
// to the final destination using (unaligned) integer loads and stores.
- MVT StoredVT = ST->getMemoryVT();
- MVT RegVT =
- TLI.getRegisterType(MVT::getIntegerVT(StoredVT.getSizeInBits()));
+ EVT StoredVT = ST->getMemoryVT();
+ EVT RegVT =
+ TLI.getRegisterType(EVT::getIntegerVT(StoredVT.getSizeInBits()));
unsigned StoredBytes = StoredVT.getSizeInBits() / 8;
unsigned RegBytes = RegVT.getSizeInBits() / 8;
unsigned NumRegs = (StoredBytes + RegBytes - 1) / RegBytes;
@@ -439,7 +439,7 @@
// The last store may be partial. Do a truncating store. On big-endian
// machines this requires an extending load from the stack slot to ensure
// that the bits are in the right place.
- MVT MemVT = MVT::getIntegerVT(8 * (StoredBytes - Offset));
+ EVT MemVT = EVT::getIntegerVT(8 * (StoredBytes - Offset));
// Load from the stack slot.
SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr,
@@ -450,7 +450,7 @@
MemVT, ST->isVolatile(),
MinAlign(ST->getAlignment(), Offset)));
// The order of the stores doesn't matter - say it with a TokenFactor.
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Stores[0],
Stores.size());
}
}
@@ -458,8 +458,8 @@
!ST->getMemoryVT().isVector() &&
"Unaligned store of unknown type.");
// Get the half-size VT
- MVT NewStoredVT =
- (MVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
+ EVT NewStoredVT =
+ (EVT::SimpleValueType)(ST->getMemoryVT().getSimpleVT() - 1);
int NumBits = NewStoredVT.getSizeInBits();
int IncrementSize = NumBits / 8;
@@ -480,7 +480,7 @@
ST->getSrcValue(), SVOffset + IncrementSize,
NewStoredVT, ST->isVolatile(), Alignment);
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Store1, Store2);
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Store1, Store2);
}
/// ExpandUnalignedLoad - Expands an unaligned load to 2 half-size loads.
@@ -490,11 +490,11 @@
int SVOffset = LD->getSrcValueOffset();
SDValue Chain = LD->getChain();
SDValue Ptr = LD->getBasePtr();
- MVT VT = LD->getValueType(0);
- MVT LoadedVT = LD->getMemoryVT();
+ EVT VT = LD->getValueType(0);
+ EVT LoadedVT = LD->getMemoryVT();
DebugLoc dl = LD->getDebugLoc();
if (VT.isFloatingPoint() || VT.isVector()) {
- MVT intVT = MVT::getIntegerVT(LoadedVT.getSizeInBits());
+ EVT intVT = EVT::getIntegerVT(LoadedVT.getSizeInBits());
if (TLI.isTypeLegal(intVT)) {
// Expand to a (misaligned) integer load of the same size,
// then bitconvert to floating point or vector.
@@ -510,7 +510,7 @@
} else {
// Copy the value to a (aligned) stack slot using (unaligned) integer
// loads and stores, then do a (aligned) load from the stack slot.
- MVT RegVT = TLI.getRegisterType(intVT);
+ EVT RegVT = TLI.getRegisterType(intVT);
unsigned LoadedBytes = LoadedVT.getSizeInBits() / 8;
unsigned RegBytes = RegVT.getSizeInBits() / 8;
unsigned NumRegs = (LoadedBytes + RegBytes - 1) / RegBytes;
@@ -540,7 +540,7 @@
}
// The last copy may be partial. Do an extending load.
- MVT MemVT = MVT::getIntegerVT(8 * (LoadedBytes - Offset));
+ EVT MemVT = EVT::getIntegerVT(8 * (LoadedBytes - Offset));
SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Chain, Ptr,
LD->getSrcValue(), SVOffset + Offset,
MemVT, LD->isVolatile(),
@@ -552,7 +552,7 @@
NULL, 0, MemVT));
// The order of the stores doesn't matter - say it with a TokenFactor.
- SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0],
+ SDValue TF = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Stores[0],
Stores.size());
// Finally, perform the original load only redirected to the stack slot.
@@ -570,8 +570,8 @@
// Compute the new VT that is half the size of the old one. This is an
// integer MVT.
unsigned NumBits = LoadedVT.getSizeInBits();
- MVT NewLoadedVT;
- NewLoadedVT = MVT::getIntegerVT(NumBits/2);
+ EVT NewLoadedVT;
+ NewLoadedVT = EVT::getIntegerVT(NumBits/2);
NumBits >>= 1;
unsigned Alignment = LD->getAlignment();
@@ -607,7 +607,7 @@
SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
Result = DAG.getNode(ISD::OR, dl, VT, Result, Lo);
- SDValue TF = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
+ SDValue TF = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
Hi.getValue(1));
SDValue Ops[] = { Result, TF };
@@ -631,10 +631,10 @@
// with a "move to register" or "extload into register" instruction, then
// permute it into place, if the idx is a constant and if the idx is
// supported by the target.
- MVT VT = Tmp1.getValueType();
- MVT EltVT = VT.getVectorElementType();
- MVT IdxVT = Tmp3.getValueType();
- MVT PtrVT = TLI.getPointerTy();
+ EVT VT = Tmp1.getValueType();
+ EVT EltVT = VT.getVectorElementType();
+ EVT IdxVT = Tmp3.getValueType();
+ EVT PtrVT = TLI.getPointerTy();
SDValue StackPtr = DAG.CreateStackTemporary(VT);
int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
@@ -665,7 +665,7 @@
// SCALAR_TO_VECTOR requires that the type of the value being inserted
// match the element type of the vector being created, except for
// integers in which case the inserted value can be over width.
- MVT EltVT = Vec.getValueType().getVectorElementType();
+ EVT EltVT = Vec.getValueType().getVectorElementType();
if (Val.getValueType() == EltVT ||
(EltVT.isInteger() && Val.getValueType().bitsGE(EltVT))) {
SDValue ScVec = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl,
@@ -702,27 +702,27 @@
bool isVolatile = ST->isVolatile();
DebugLoc dl = ST->getDebugLoc();
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(ST->getValue())) {
- if (CFP->getValueType(0) == MVT::f32 &&
- getTypeAction(MVT::i32) == Legal) {
+ if (CFP->getValueType(0) == EVT::f32 &&
+ getTypeAction(EVT::i32) == Legal) {
Tmp3 = DAG.getConstant(CFP->getValueAPF().
bitcastToAPInt().zextOrTrunc(32),
- MVT::i32);
+ EVT::i32);
return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
- } else if (CFP->getValueType(0) == MVT::f64) {
+ } else if (CFP->getValueType(0) == EVT::f64) {
// If this target supports 64-bit registers, do a single 64-bit store.
- if (getTypeAction(MVT::i64) == Legal) {
+ if (getTypeAction(EVT::i64) == Legal) {
Tmp3 = DAG.getConstant(CFP->getValueAPF().bitcastToAPInt().
- zextOrTrunc(64), MVT::i64);
+ zextOrTrunc(64), EVT::i64);
return DAG.getStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, isVolatile, Alignment);
- } else if (getTypeAction(MVT::i32) == Legal && !ST->isVolatile()) {
+ } else if (getTypeAction(EVT::i32) == Legal && !ST->isVolatile()) {
// Otherwise, if the target supports 32-bit registers, use 2 32-bit
// stores. If the target supports neither 32- nor 64-bits, this
// xform is certainly not worth it.
const APInt &IntVal =CFP->getValueAPF().bitcastToAPInt();
- SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), MVT::i32);
- SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), MVT::i32);
+ SDValue Lo = DAG.getConstant(APInt(IntVal).trunc(32), EVT::i32);
+ SDValue Hi = DAG.getConstant(IntVal.lshr(32).trunc(32), EVT::i32);
if (TLI.isBigEndian()) std::swap(Lo, Hi);
Lo = DAG.getStore(Tmp1, dl, Lo, Tmp2, ST->getSrcValue(),
@@ -732,7 +732,7 @@
Hi = DAG.getStore(Tmp1, dl, Hi, Tmp2, ST->getSrcValue(), SVOffset+4,
isVolatile, MinAlign(Alignment, 4U));
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
}
}
}
@@ -777,7 +777,7 @@
case ISD::INTRINSIC_VOID:
case ISD::VAARG:
case ISD::STACKSAVE:
- Action = TLI.getOperationAction(Node->getOpcode(), MVT::Other);
+ Action = TLI.getOperationAction(Node->getOpcode(), EVT::Other);
break;
case ISD::SINT_TO_FP:
case ISD::UINT_TO_FP:
@@ -787,7 +787,7 @@
break;
case ISD::FP_ROUND_INREG:
case ISD::SIGN_EXTEND_INREG: {
- MVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
+ EVT InnerType = cast<VTSDNode>(Node->getOperand(1))->getVT();
Action = TLI.getOperationAction(Node->getOpcode(), InnerType);
break;
}
@@ -797,7 +797,7 @@
unsigned CCOperand = Node->getOpcode() == ISD::SELECT_CC ? 4 :
Node->getOpcode() == ISD::SETCC ? 2 : 1;
unsigned CompareOperand = Node->getOpcode() == ISD::BR_CC ? 2 : 0;
- MVT OpVT = Node->getOperand(CompareOperand).getValueType();
+ EVT OpVT = Node->getOperand(CompareOperand).getValueType();
ISD::CondCode CCCode =
cast<CondCodeSDNode>(Node->getOperand(CCOperand))->get();
Action = TLI.getCondCodeAction(CCCode, OpVT);
@@ -882,7 +882,7 @@
case ISD::BR_CC:
case ISD::BRCOND:
// Branches tweak the chain to include LastCALLSEQ_END
- Ops[0] = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Ops[0],
+ Ops[0] = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Ops[0],
LastCALLSEQ_END);
Ops[0] = LegalizeOp(Ops[0]);
LastCALLSEQ_END = DAG.getEntryNode();
@@ -979,7 +979,7 @@
// Merge in the last call, to ensure that this call start after the last
// call ended.
if (LastCALLSEQ_END.getOpcode() != ISD::EntryToken) {
- Tmp1 = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ Tmp1 = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
Tmp1, LastCALLSEQ_END);
Tmp1 = LegalizeOp(Tmp1);
}
@@ -1026,7 +1026,7 @@
Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
// Do not try to legalize the target-specific arguments (#1+), except for
// an optional flag input.
- if (Node->getOperand(Node->getNumOperands()-1).getValueType() != MVT::Flag){
+ if (Node->getOperand(Node->getNumOperands()-1).getValueType() != EVT::Flag){
if (Tmp1 != Node->getOperand(0)) {
SmallVector<SDValue, 8> Ops(Node->op_begin(), Node->op_end());
Ops[0] = Tmp1;
@@ -1058,7 +1058,7 @@
ISD::LoadExtType ExtType = LD->getExtensionType();
if (ExtType == ISD::NON_EXTLOAD) {
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp2, LD->getOffset());
Tmp3 = Result.getValue(0);
Tmp4 = Result.getValue(1);
@@ -1070,7 +1070,7 @@
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
- getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
+ getABITypeAlignment(LD->getMemoryVT().getTypeForEVT());
if (LD->getAlignment() < ABIAlignment){
Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
DAG, TLI);
@@ -1092,7 +1092,7 @@
// Only promote a load of vector type to another.
assert(VT.isVector() && "Cannot promote this load!");
// Change base type to a different vector type.
- MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
+ EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), VT);
Tmp1 = DAG.getLoad(NVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
LD->getSrcValueOffset(),
@@ -1108,7 +1108,7 @@
AddLegalizedOperand(SDValue(Node, 1), Tmp4);
return Op.getResNo() ? Tmp4 : Tmp3;
} else {
- MVT SrcVT = LD->getMemoryVT();
+ EVT SrcVT = LD->getMemoryVT();
unsigned SrcWidth = SrcVT.getSizeInBits();
int SVOffset = LD->getSrcValueOffset();
unsigned Alignment = LD->getAlignment();
@@ -1122,12 +1122,12 @@
// tells the optimizers that those bits are undefined. It would be
// nice to have an effective generic way of getting these benefits...
// Until such a way is found, don't insist on promoting i1 here.
- (SrcVT != MVT::i1 ||
- TLI.getLoadExtAction(ExtType, MVT::i1) == TargetLowering::Promote)) {
+ (SrcVT != EVT::i1 ||
+ TLI.getLoadExtAction(ExtType, EVT::i1) == TargetLowering::Promote)) {
// Promote to a byte-sized load if not loading an integral number of
// bytes. For example, promote EXTLOAD:i20 -> EXTLOAD:i24.
unsigned NewWidth = SrcVT.getStoreSizeInBits();
- MVT NVT = MVT::getIntegerVT(NewWidth);
+ EVT NVT = EVT::getIntegerVT(NewWidth);
SDValue Ch;
// The extra bits are guaranteed to be zero, since we stored them that
@@ -1165,8 +1165,8 @@
assert(ExtraWidth < RoundWidth);
assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
"Load size not an integral number of bytes!");
- MVT RoundVT = MVT::getIntegerVT(RoundWidth);
- MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
+ EVT RoundVT = EVT::getIntegerVT(RoundWidth);
+ EVT ExtraVT = EVT::getIntegerVT(ExtraWidth);
SDValue Lo, Hi, Ch;
unsigned IncrementSize;
@@ -1189,7 +1189,7 @@
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Move the top bits to the right place.
@@ -1218,7 +1218,7 @@
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Move the top bits to the right place.
@@ -1253,7 +1253,7 @@
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
- getABITypeAlignment(LD->getMemoryVT().getTypeForMVT());
+ getABITypeAlignment(LD->getMemoryVT().getTypeForEVT());
if (LD->getAlignment() < ABIAlignment){
Result = ExpandUnalignedLoad(cast<LoadSDNode>(Result.getNode()),
DAG, TLI);
@@ -1267,7 +1267,7 @@
break;
case TargetLowering::Expand:
// f64 = EXTLOAD f32 should expand to LOAD, FP_EXTEND
- if (SrcVT == MVT::f32 && Node->getValueType(0) == MVT::f64) {
+ if (SrcVT == EVT::f32 && Node->getValueType(0) == EVT::f64) {
SDValue Load = DAG.getLoad(SrcVT, dl, Tmp1, Tmp2, LD->getSrcValue(),
LD->getSrcValueOffset(),
LD->isVolatile(), LD->getAlignment());
@@ -1323,7 +1323,7 @@
Result = DAG.UpdateNodeOperands(Result, Tmp1, Tmp3, Tmp2,
ST->getOffset());
- MVT VT = Tmp3.getValueType();
+ EVT VT = Tmp3.getValueType();
switch (TLI.getOperationAction(ISD::STORE, VT)) {
default: llvm_unreachable("This action is not supported yet!");
case TargetLowering::Legal:
@@ -1331,7 +1331,7 @@
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
- getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
+ getABITypeAlignment(ST->getMemoryVT().getTypeForEVT());
if (ST->getAlignment() < ABIAlignment)
Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
TLI);
@@ -1355,14 +1355,14 @@
} else {
Tmp3 = LegalizeOp(ST->getValue());
- MVT StVT = ST->getMemoryVT();
+ EVT StVT = ST->getMemoryVT();
unsigned StWidth = StVT.getSizeInBits();
if (StWidth != StVT.getStoreSizeInBits()) {
// Promote to a byte-sized store with upper bits zero if not
// storing an integral number of bytes. For example, promote
// TRUNCSTORE:i1 X -> TRUNCSTORE:i8 (and X, 1)
- MVT NVT = MVT::getIntegerVT(StVT.getStoreSizeInBits());
+ EVT NVT = EVT::getIntegerVT(StVT.getStoreSizeInBits());
Tmp3 = DAG.getZeroExtendInReg(Tmp3, dl, StVT);
Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getSrcValue(),
SVOffset, NVT, isVolatile, Alignment);
@@ -1376,8 +1376,8 @@
assert(ExtraWidth < RoundWidth);
assert(!(RoundWidth % 8) && !(ExtraWidth % 8) &&
"Store size not an integral number of bytes!");
- MVT RoundVT = MVT::getIntegerVT(RoundWidth);
- MVT ExtraVT = MVT::getIntegerVT(ExtraWidth);
+ EVT RoundVT = EVT::getIntegerVT(RoundWidth);
+ EVT ExtraVT = EVT::getIntegerVT(ExtraWidth);
SDValue Lo, Hi;
unsigned IncrementSize;
@@ -1416,7 +1416,7 @@
}
// The order of the stores doesn't matter.
- Result = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
+ Result = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
} else {
if (Tmp1 != ST->getChain() || Tmp3 != ST->getValue() ||
Tmp2 != ST->getBasePtr())
@@ -1430,7 +1430,7 @@
// expand it.
if (!TLI.allowsUnalignedMemoryAccesses()) {
unsigned ABIAlignment = TLI.getTargetData()->
- getABITypeAlignment(ST->getMemoryVT().getTypeForMVT());
+ getABITypeAlignment(ST->getMemoryVT().getTypeForEVT());
if (ST->getAlignment() < ABIAlignment)
Result = ExpandUnalignedStore(cast<StoreSDNode>(Result.getNode()), DAG,
TLI);
@@ -1498,8 +1498,8 @@
// aligned object on the stack, store each element into it, then load
// the result as a vector.
// Create the stack frame object.
- MVT VT = Node->getValueType(0);
- MVT OpVT = Node->getOperand(0).getValueType();
+ EVT VT = Node->getValueType(0);
+ EVT OpVT = Node->getOperand(0).getValueType();
DebugLoc dl = Node->getDebugLoc();
SDValue FIPtr = DAG.CreateStackTemporary(VT);
int FI = cast<FrameIndexSDNode>(FIPtr.getNode())->getIndex();
@@ -1524,7 +1524,7 @@
SDValue StoreChain;
if (!Stores.empty()) // Not all undef elements?
- StoreChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ StoreChain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&Stores[0], Stores.size());
else
StoreChain = DAG.getEntryNode();
@@ -1537,28 +1537,28 @@
DebugLoc dl = Node->getDebugLoc();
SDValue Tmp1 = Node->getOperand(0);
SDValue Tmp2 = Node->getOperand(1);
- assert((Tmp2.getValueType() == MVT::f32 ||
- Tmp2.getValueType() == MVT::f64) &&
+ assert((Tmp2.getValueType() == EVT::f32 ||
+ Tmp2.getValueType() == EVT::f64) &&
"Ugly special-cased code!");
// Get the sign bit of the RHS.
SDValue SignBit;
- MVT IVT = Tmp2.getValueType() == MVT::f64 ? MVT::i64 : MVT::i32;
+ EVT IVT = Tmp2.getValueType() == EVT::f64 ? EVT::i64 : EVT::i32;
if (isTypeLegal(IVT)) {
SignBit = DAG.getNode(ISD::BIT_CONVERT, dl, IVT, Tmp2);
} else {
assert(isTypeLegal(TLI.getPointerTy()) &&
- (TLI.getPointerTy() == MVT::i32 ||
- TLI.getPointerTy() == MVT::i64) &&
+ (TLI.getPointerTy() == EVT::i32 ||
+ TLI.getPointerTy() == EVT::i64) &&
"Legal type for load?!");
SDValue StackPtr = DAG.CreateStackTemporary(Tmp2.getValueType());
SDValue StorePtr = StackPtr, LoadPtr = StackPtr;
SDValue Ch =
DAG.getStore(DAG.getEntryNode(), dl, Tmp2, StorePtr, NULL, 0);
- if (Tmp2.getValueType() == MVT::f64 && TLI.isLittleEndian())
+ if (Tmp2.getValueType() == EVT::f64 && TLI.isLittleEndian())
LoadPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(),
LoadPtr, DAG.getIntPtrConstant(4));
SignBit = DAG.getExtLoad(ISD::SEXTLOAD, dl, TLI.getPointerTy(),
- Ch, LoadPtr, NULL, 0, MVT::i32);
+ Ch, LoadPtr, NULL, 0, EVT::i32);
}
SignBit =
DAG.getSetCC(dl, TLI.getSetCCResultType(SignBit.getValueType()),
@@ -1577,8 +1577,8 @@
DebugLoc dl = Node->getDebugLoc();
DwarfWriter *DW = DAG.getDwarfWriter();
bool useDEBUG_LOC = TLI.isOperationLegalOrCustom(ISD::DEBUG_LOC,
- MVT::Other);
- bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, MVT::Other);
+ EVT::Other);
+ bool useLABEL = TLI.isOperationLegalOrCustom(ISD::DBG_LABEL, EVT::Other);
const DbgStopPointSDNode *DSP = cast<DbgStopPointSDNode>(Node);
GlobalVariable *CU_GV = cast<GlobalVariable>(DSP->getCompileUnit());
@@ -1592,9 +1592,9 @@
// A bit self-referential to have DebugLoc on Debug_Loc nodes, but it
// won't hurt anything.
if (useDEBUG_LOC) {
- return DAG.getNode(ISD::DEBUG_LOC, dl, MVT::Other, Node->getOperand(0),
- DAG.getConstant(Line, MVT::i32),
- DAG.getConstant(Col, MVT::i32),
+ return DAG.getNode(ISD::DEBUG_LOC, dl, EVT::Other, Node->getOperand(0),
+ DAG.getConstant(Line, EVT::i32),
+ DAG.getConstant(Col, EVT::i32),
DAG.getSrcValue(CU.getGV()));
} else {
unsigned ID = DW->RecordSourceLine(Line, Col, CU);
@@ -1611,7 +1611,7 @@
assert(SPReg && "Target cannot require DYNAMIC_STACKALLOC expansion and"
" not tell us which reg is the stack pointer!");
DebugLoc dl = Node->getDebugLoc();
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
SDValue Tmp1 = SDValue(Node, 0);
SDValue Tmp2 = SDValue(Node, 1);
SDValue Tmp3 = Node->getOperand(2);
@@ -1644,11 +1644,11 @@
/// condition code CC on the current target. This routine assumes LHS and rHS
/// have already been legalized by LegalizeSetCCOperands. It expands SETCC with
/// illegal condition code into AND / OR of multiple SETCC values.
-void SelectionDAGLegalize::LegalizeSetCCCondCode(MVT VT,
+void SelectionDAGLegalize::LegalizeSetCCCondCode(EVT VT,
SDValue &LHS, SDValue &RHS,
SDValue &CC,
DebugLoc dl) {
- MVT OpVT = LHS.getValueType();
+ EVT OpVT = LHS.getValueType();
ISD::CondCode CCCode = cast<CondCodeSDNode>(CC)->get();
switch (TLI.getCondCodeAction(CCCode, OpVT)) {
default: llvm_unreachable("Unknown condition code action!");
@@ -1690,13 +1690,13 @@
/// a load from the stack slot to DestVT, extending it if needed.
/// The resultant code need not be legal.
SDValue SelectionDAGLegalize::EmitStackConvert(SDValue SrcOp,
- MVT SlotVT,
- MVT DestVT,
+ EVT SlotVT,
+ EVT DestVT,
DebugLoc dl) {
// Create the stack frame object.
unsigned SrcAlign =
TLI.getTargetData()->getPrefTypeAlignment(SrcOp.getValueType().
- getTypeForMVT());
+ getTypeForEVT());
SDValue FIPtr = DAG.CreateStackTemporary(SlotVT, SrcAlign);
FrameIndexSDNode *StackPtrFI = cast<FrameIndexSDNode>(FIPtr);
@@ -1707,7 +1707,7 @@
unsigned SlotSize = SlotVT.getSizeInBits();
unsigned DestSize = DestVT.getSizeInBits();
unsigned DestAlign =
- TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForMVT());
+ TLI.getTargetData()->getPrefTypeAlignment(DestVT.getTypeForEVT());
// Emit a store to the stack slot. Use a truncstore if the input value is
// later than DestVT.
@@ -1755,9 +1755,9 @@
unsigned NumElems = Node->getNumOperands();
SDValue Value1, Value2;
DebugLoc dl = Node->getDebugLoc();
- MVT VT = Node->getValueType(0);
- MVT OpVT = Node->getOperand(0).getValueType();
- MVT EltVT = VT.getVectorElementType();
+ EVT VT = Node->getValueType(0);
+ EVT OpVT = Node->getOperand(0).getValueType();
+ EVT EltVT = VT.getVectorElementType();
// If the only non-undef value is the low element, turn this into a
// SCALAR_TO_VECTOR node. If this is { X, X, X, X }, determine X.
@@ -1801,7 +1801,7 @@
CV.push_back(const_cast<ConstantInt *>(V->getConstantIntValue()));
} else {
assert(Node->getOperand(i).getOpcode() == ISD::UNDEF);
- const Type *OpNTy = OpVT.getTypeForMVT();
+ const Type *OpNTy = OpVT.getTypeForEVT();
CV.push_back(UndefValue::get(OpNTy));
}
}
@@ -1854,8 +1854,8 @@
TargetLowering::ArgListTy Args;
TargetLowering::ArgListEntry Entry;
for (unsigned i = 0, e = Node->getNumOperands(); i != e; ++i) {
- MVT ArgVT = Node->getOperand(i).getValueType();
- const Type *ArgTy = ArgVT.getTypeForMVT();
+ EVT ArgVT = Node->getOperand(i).getValueType();
+ const Type *ArgTy = ArgVT.getTypeForEVT();
Entry.Node = Node->getOperand(i); Entry.Ty = ArgTy;
Entry.isSExt = isSigned;
Entry.isZExt = !isSigned;
@@ -1865,7 +1865,7 @@
TLI.getPointerTy());
// Splice the libcall in wherever FindInputOutputChains tells us to.
- const Type *RetTy = Node->getValueType(0).getTypeForMVT();
+ const Type *RetTy = Node->getValueType(0).getTypeForEVT();
std::pair<SDValue, SDValue> CallInfo =
TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
0, CallingConv::C, false,
@@ -1888,10 +1888,10 @@
RTLIB::Libcall LC;
switch (Node->getValueType(0).getSimpleVT()) {
default: llvm_unreachable("Unexpected request for libcall!");
- case MVT::f32: LC = Call_F32; break;
- case MVT::f64: LC = Call_F64; break;
- case MVT::f80: LC = Call_F80; break;
- case MVT::ppcf128: LC = Call_PPCF128; break;
+ case EVT::f32: LC = Call_F32; break;
+ case EVT::f64: LC = Call_F64; break;
+ case EVT::f80: LC = Call_F80; break;
+ case EVT::ppcf128: LC = Call_PPCF128; break;
}
return ExpandLibCall(LC, Node, false);
}
@@ -1904,10 +1904,10 @@
RTLIB::Libcall LC;
switch (Node->getValueType(0).getSimpleVT()) {
default: llvm_unreachable("Unexpected request for libcall!");
- case MVT::i16: LC = Call_I16; break;
- case MVT::i32: LC = Call_I32; break;
- case MVT::i64: LC = Call_I64; break;
- case MVT::i128: LC = Call_I128; break;
+ case EVT::i16: LC = Call_I16; break;
+ case EVT::i32: LC = Call_I32; break;
+ case EVT::i64: LC = Call_I64; break;
+ case EVT::i128: LC = Call_I128; break;
}
return ExpandLibCall(LC, Node, isSigned);
}
@@ -1918,13 +1918,13 @@
/// legal for the target.
SDValue SelectionDAGLegalize::ExpandLegalINT_TO_FP(bool isSigned,
SDValue Op0,
- MVT DestVT,
+ EVT DestVT,
DebugLoc dl) {
- if (Op0.getValueType() == MVT::i32) {
+ if (Op0.getValueType() == EVT::i32) {
// simple 32-bit [signed|unsigned] integer to float/double expansion
// Get the stack frame index of a 8 byte buffer.
- SDValue StackSlot = DAG.CreateStackTemporary(MVT::f64);
+ SDValue StackSlot = DAG.CreateStackTemporary(EVT::f64);
// word offset constant for Hi/Lo address computation
SDValue WordOff = DAG.getConstant(sizeof(int), TLI.getPointerTy());
@@ -1939,8 +1939,8 @@
SDValue Op0Mapped;
if (isSigned) {
// constant used to invert sign bit (signed to unsigned mapping)
- SDValue SignBit = DAG.getConstant(0x80000000u, MVT::i32);
- Op0Mapped = DAG.getNode(ISD::XOR, dl, MVT::i32, Op0, SignBit);
+ SDValue SignBit = DAG.getConstant(0x80000000u, EVT::i32);
+ Op0Mapped = DAG.getNode(ISD::XOR, dl, EVT::i32, Op0, SignBit);
} else {
Op0Mapped = Op0;
}
@@ -1948,28 +1948,28 @@
SDValue Store1 = DAG.getStore(DAG.getEntryNode(), dl,
Op0Mapped, Lo, NULL, 0);
// initial hi portion of constructed double
- SDValue InitialHi = DAG.getConstant(0x43300000u, MVT::i32);
+ SDValue InitialHi = DAG.getConstant(0x43300000u, EVT::i32);
// store the hi of the constructed double - biased exponent
SDValue Store2=DAG.getStore(Store1, dl, InitialHi, Hi, NULL, 0);
// load the constructed double
- SDValue Load = DAG.getLoad(MVT::f64, dl, Store2, StackSlot, NULL, 0);
+ SDValue Load = DAG.getLoad(EVT::f64, dl, Store2, StackSlot, NULL, 0);
// FP constant to bias correct the final result
SDValue Bias = DAG.getConstantFP(isSigned ?
BitsToDouble(0x4330000080000000ULL) :
BitsToDouble(0x4330000000000000ULL),
- MVT::f64);
+ EVT::f64);
// subtract the bias
- SDValue Sub = DAG.getNode(ISD::FSUB, dl, MVT::f64, Load, Bias);
+ SDValue Sub = DAG.getNode(ISD::FSUB, dl, EVT::f64, Load, Bias);
// final result
SDValue Result;
// handle final rounding
- if (DestVT == MVT::f64) {
+ if (DestVT == EVT::f64) {
// do nothing
Result = Sub;
- } else if (DestVT.bitsLT(MVT::f64)) {
+ } else if (DestVT.bitsLT(EVT::f64)) {
Result = DAG.getNode(ISD::FP_ROUND, dl, DestVT, Sub,
DAG.getIntPtrConstant(0));
- } else if (DestVT.bitsGT(MVT::f64)) {
+ } else if (DestVT.bitsGT(EVT::f64)) {
Result = DAG.getNode(ISD::FP_EXTEND, dl, DestVT, Sub);
}
return Result;
@@ -1990,10 +1990,10 @@
uint64_t FF;
switch (Op0.getValueType().getSimpleVT()) {
default: llvm_unreachable("Unsupported integer type!");
- case MVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
- case MVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
- case MVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
- case MVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
+ case EVT::i8 : FF = 0x43800000ULL; break; // 2^8 (as a float)
+ case EVT::i16: FF = 0x47800000ULL; break; // 2^16 (as a float)
+ case EVT::i32: FF = 0x4F800000ULL; break; // 2^32 (as a float)
+ case EVT::i64: FF = 0x5F800000ULL; break; // 2^64 (as a float)
}
if (TLI.isLittleEndian()) FF <<= 32;
Constant *FudgeFactor = ConstantInt::get(Type::Int64Ty, FF);
@@ -2003,8 +2003,8 @@
CPIdx = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), CPIdx, CstOffset);
Alignment = std::min(Alignment, 4u);
SDValue FudgeInReg;
- if (DestVT == MVT::f32)
- FudgeInReg = DAG.getLoad(MVT::f32, dl, DAG.getEntryNode(), CPIdx,
+ if (DestVT == EVT::f32)
+ FudgeInReg = DAG.getLoad(EVT::f32, dl, DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
false, Alignment);
else {
@@ -2012,7 +2012,7 @@
LegalizeOp(DAG.getExtLoad(ISD::EXTLOAD, dl, DestVT,
DAG.getEntryNode(), CPIdx,
PseudoSourceValue::getConstantPool(), 0,
- MVT::f32, false, Alignment));
+ EVT::f32, false, Alignment));
}
return DAG.getNode(ISD::FADD, dl, DestVT, Tmp1, FudgeInReg);
@@ -2024,17 +2024,17 @@
/// legal for the target, and that there is a legal UINT_TO_FP or SINT_TO_FP
/// operation that takes a larger input.
SDValue SelectionDAGLegalize::PromoteLegalINT_TO_FP(SDValue LegalOp,
- MVT DestVT,
+ EVT DestVT,
bool isSigned,
DebugLoc dl) {
// First step, figure out the appropriate *INT_TO_FP operation to use.
- MVT NewInTy = LegalOp.getValueType();
+ EVT NewInTy = LegalOp.getValueType();
unsigned OpToUse = 0;
// Scan for the appropriate larger type to use.
while (1) {
- NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
+ NewInTy = (EVT::SimpleValueType)(NewInTy.getSimpleVT()+1);
assert(NewInTy.isInteger() && "Ran out of possibilities!");
// If the target supports SINT_TO_FP of this type, use it.
@@ -2066,17 +2066,17 @@
/// legal for the target, and that there is a legal FP_TO_UINT or FP_TO_SINT
/// operation that returns a larger result.
SDValue SelectionDAGLegalize::PromoteLegalFP_TO_INT(SDValue LegalOp,
- MVT DestVT,
+ EVT DestVT,
bool isSigned,
DebugLoc dl) {
// First step, figure out the appropriate FP_TO*INT operation to use.
- MVT NewOutTy = DestVT;
+ EVT NewOutTy = DestVT;
unsigned OpToUse = 0;
// Scan for the appropriate larger type to use.
while (1) {
- NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
+ NewOutTy = (EVT::SimpleValueType)(NewOutTy.getSimpleVT()+1);
assert(NewOutTy.isInteger() && "Ran out of possibilities!");
if (TLI.isOperationLegalOrCustom(ISD::FP_TO_SINT, NewOutTy)) {
@@ -2104,16 +2104,16 @@
/// ExpandBSWAP - Open code the operations for BSWAP of the specified operation.
///
SDValue SelectionDAGLegalize::ExpandBSWAP(SDValue Op, DebugLoc dl) {
- MVT VT = Op.getValueType();
- MVT SHVT = TLI.getShiftAmountTy();
+ EVT VT = Op.getValueType();
+ EVT SHVT = TLI.getShiftAmountTy();
SDValue Tmp1, Tmp2, Tmp3, Tmp4, Tmp5, Tmp6, Tmp7, Tmp8;
switch (VT.getSimpleVT()) {
default: llvm_unreachable("Unhandled Expand type in BSWAP!");
- case MVT::i16:
+ case EVT::i16:
Tmp2 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
Tmp1 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
return DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
- case MVT::i32:
+ case EVT::i32:
Tmp4 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
Tmp3 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(8, SHVT));
Tmp2 = DAG.getNode(ISD::SRL, dl, VT, Op, DAG.getConstant(8, SHVT));
@@ -2123,7 +2123,7 @@
Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp3);
Tmp2 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp1);
return DAG.getNode(ISD::OR, dl, VT, Tmp4, Tmp2);
- case MVT::i64:
+ case EVT::i64:
Tmp8 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(56, SHVT));
Tmp7 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(40, SHVT));
Tmp6 = DAG.getNode(ISD::SHL, dl, VT, Op, DAG.getConstant(24, SHVT));
@@ -2160,8 +2160,8 @@
0x0F0F0F0F0F0F0F0FULL, 0x00FF00FF00FF00FFULL,
0x0000FFFF0000FFFFULL, 0x00000000FFFFFFFFULL
};
- MVT VT = Op.getValueType();
- MVT ShVT = TLI.getShiftAmountTy();
+ EVT VT = Op.getValueType();
+ EVT ShVT = TLI.getShiftAmountTy();
unsigned len = VT.getSizeInBits();
for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
//x = (x & mask[i][len/8]) + (x >> (1 << i) & mask[i][len/8])
@@ -2187,8 +2187,8 @@
// return popcount(~x);
//
// but see also: http://www.hackersdelight.org/HDcode/nlz.cc
- MVT VT = Op.getValueType();
- MVT ShVT = TLI.getShiftAmountTy();
+ EVT VT = Op.getValueType();
+ EVT ShVT = TLI.getShiftAmountTy();
unsigned len = VT.getSizeInBits();
for (unsigned i = 0; (1U << i) <= (len / 2); ++i) {
SDValue Tmp3 = DAG.getConstant(1ULL << i, ShVT);
@@ -2203,7 +2203,7 @@
// unless the target has ctlz but not ctpop, in which case we use:
// { return 32 - nlz(~x & (x-1)); }
// see also http://www.hackersdelight.org/HDcode/ntz.cc
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue Tmp3 = DAG.getNode(ISD::AND, dl, VT,
DAG.getNOT(dl, Op, VT),
DAG.getNode(ISD::SUB, dl, VT, Op,
@@ -2261,7 +2261,7 @@
Results.push_back(Node->getOperand(i));
break;
case ISD::UNDEF: {
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
if (VT.isInteger())
Results.push_back(DAG.getConstant(0, VT));
else if (VT.isFloatingPoint())
@@ -2297,7 +2297,7 @@
case ISD::SIGN_EXTEND_INREG: {
// NOTE: we could fall back on load/store here too for targets without
// SAR. However, it is doubtful that any exist.
- MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
+ EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
unsigned BitsDiff = Node->getValueType(0).getSizeInBits() -
ExtraVT.getSizeInBits();
SDValue ShiftCst = DAG.getConstant(BitsDiff, TLI.getShiftAmountTy());
@@ -2314,7 +2314,7 @@
// NOTE: there is a choice here between constantly creating new stack
// slots and always reusing the same one. We currently always create
// new ones, as reuse may inhibit scheduling.
- MVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
+ EVT ExtraVT = cast<VTSDNode>(Node->getOperand(1))->getVT();
Tmp1 = EmitStackConvert(Node->getOperand(0), ExtraVT,
Node->getValueType(0), dl);
Results.push_back(Tmp1);
@@ -2328,8 +2328,8 @@
break;
case ISD::FP_TO_UINT: {
SDValue True, False;
- MVT VT = Node->getOperand(0).getValueType();
- MVT NVT = Node->getValueType(0);
+ EVT VT = Node->getOperand(0).getValueType();
+ EVT NVT = Node->getValueType(0);
const uint64_t zero[] = {0, 0};
APFloat apf = APFloat(APInt(VT.getSizeInBits(), 2, zero));
APInt x = APInt::getSignBit(NVT.getSizeInBits());
@@ -2350,14 +2350,14 @@
}
case ISD::VAARG: {
const Value *V = cast<SrcValueSDNode>(Node->getOperand(2))->getValue();
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
Tmp1 = Node->getOperand(0);
Tmp2 = Node->getOperand(1);
SDValue VAList = DAG.getLoad(TLI.getPointerTy(), dl, Tmp1, Tmp2, V, 0);
// Increment the pointer, VAList, to the next vaarg
Tmp3 = DAG.getNode(ISD::ADD, dl, TLI.getPointerTy(), VAList,
DAG.getConstant(TLI.getTargetData()->
- getTypeAllocSize(VT.getTypeForMVT()),
+ getTypeAllocSize(VT.getTypeForEVT()),
TLI.getPointerTy()));
// Store the incremented VAList to the legalized pointer
Tmp3 = DAG.getStore(VAList.getValue(1), dl, Tmp3, Tmp2, V, 0);
@@ -2405,8 +2405,8 @@
SmallVector<int, 8> Mask;
cast<ShuffleVectorSDNode>(Node)->getMask(Mask);
- MVT VT = Node->getValueType(0);
- MVT EltVT = VT.getVectorElementType();
+ EVT VT = Node->getValueType(0);
+ EVT EltVT = VT.getVectorElementType();
unsigned NumElems = VT.getVectorNumElements();
SmallVector<SDValue, 8> Ops;
for (unsigned i = 0; i != NumElems; ++i) {
@@ -2429,7 +2429,7 @@
break;
}
case ISD::EXTRACT_ELEMENT: {
- MVT OpTy = Node->getOperand(0).getValueType();
+ EVT OpTy = Node->getOperand(0).getValueType();
if (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
// 1 -> Hi
Tmp1 = DAG.getNode(ISD::SRL, dl, OpTy, Node->getOperand(0),
@@ -2478,7 +2478,7 @@
break;
case ISD::FABS: {
// Expand Y = FABS(X) -> Y = (X >u 0.0) ? X : fneg(X).
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
Tmp1 = Node->getOperand(0);
Tmp2 = DAG.getConstantFP(0.0, VT);
Tmp2 = DAG.getSetCC(dl, TLI.getSetCCResultType(Tmp1.getValueType()),
@@ -2593,7 +2593,7 @@
break;
}
case ISD::SUB: {
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
assert(TLI.isOperationLegalOrCustom(ISD::ADD, VT) &&
TLI.isOperationLegalOrCustom(ISD::XOR, VT) &&
"Don't know how to expand this subtraction!");
@@ -2605,7 +2605,7 @@
}
case ISD::UREM:
case ISD::SREM: {
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
SDVTList VTs = DAG.getVTList(VT, VT);
bool isSigned = Node->getOpcode() == ISD::SREM;
unsigned DivOpc = isSigned ? ISD::SDIV : ISD::UDIV;
@@ -2633,7 +2633,7 @@
case ISD::SDIV: {
bool isSigned = Node->getOpcode() == ISD::SDIV;
unsigned DivRemOpc = isSigned ? ISD::SDIVREM : ISD::UDIVREM;
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
SDVTList VTs = DAG.getVTList(VT, VT);
if (TLI.isOperationLegalOrCustom(DivRemOpc, VT))
Tmp1 = DAG.getNode(DivRemOpc, dl, VTs, Node->getOperand(0),
@@ -2651,7 +2651,7 @@
case ISD::MULHS: {
unsigned ExpandOpcode = Node->getOpcode() == ISD::MULHU ? ISD::UMUL_LOHI :
ISD::SMUL_LOHI;
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
SDVTList VTs = DAG.getVTList(VT, VT);
assert(TLI.isOperationLegalOrCustom(ExpandOpcode, VT) &&
"If this wasn't legal, it shouldn't have been created!");
@@ -2661,7 +2661,7 @@
break;
}
case ISD::MUL: {
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
SDVTList VTs = DAG.getVTList(VT, VT);
// See if multiply or divide can be lowered using two-result operations.
// We just need the low half of the multiply; try both the signed
@@ -2700,7 +2700,7 @@
ISD::ADD : ISD::SUB, dl, LHS.getValueType(),
LHS, RHS);
Results.push_back(Sum);
- MVT OType = Node->getValueType(1);
+ EVT OType = Node->getValueType(1);
SDValue Zero = DAG.getConstant(0, LHS.getValueType());
@@ -2741,7 +2741,7 @@
}
case ISD::UMULO:
case ISD::SMULO: {
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
SDValue LHS = Node->getOperand(0);
SDValue RHS = Node->getOperand(1);
SDValue BottomHalf;
@@ -2757,8 +2757,8 @@
BottomHalf = DAG.getNode(Ops[isSigned][1], dl, DAG.getVTList(VT, VT), LHS,
RHS);
TopHalf = BottomHalf.getValue(1);
- } else if (TLI.isTypeLegal(MVT::getIntegerVT(VT.getSizeInBits() * 2))) {
- MVT WideVT = MVT::getIntegerVT(VT.getSizeInBits() * 2);
+ } else if (TLI.isTypeLegal(EVT::getIntegerVT(VT.getSizeInBits() * 2))) {
+ EVT WideVT = EVT::getIntegerVT(VT.getSizeInBits() * 2);
LHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, LHS);
RHS = DAG.getNode(Ops[isSigned][2], dl, WideVT, RHS);
Tmp1 = DAG.getNode(ISD::MUL, dl, WideVT, LHS, RHS);
@@ -2787,7 +2787,7 @@
break;
}
case ISD::BUILD_PAIR: {
- MVT PairTy = Node->getValueType(0);
+ EVT PairTy = Node->getValueType(0);
Tmp1 = DAG.getNode(ISD::ZERO_EXTEND, dl, PairTy, Node->getOperand(0));
Tmp2 = DAG.getNode(ISD::ANY_EXTEND, dl, PairTy, Node->getOperand(1));
Tmp2 = DAG.getNode(ISD::SHL, dl, PairTy, Tmp2,
@@ -2816,14 +2816,14 @@
SDValue Table = Node->getOperand(1);
SDValue Index = Node->getOperand(2);
- MVT PTy = TLI.getPointerTy();
+ EVT PTy = TLI.getPointerTy();
MachineFunction &MF = DAG.getMachineFunction();
unsigned EntrySize = MF.getJumpTableInfo()->getEntrySize();
Index= DAG.getNode(ISD::MUL, dl, PTy,
Index, DAG.getConstant(EntrySize, PTy));
SDValue Addr = DAG.getNode(ISD::ADD, dl, PTy, Index, Table);
- MVT MemVT = MVT::getIntegerVT(EntrySize * 8);
+ EVT MemVT = EVT::getIntegerVT(EntrySize * 8);
SDValue LD = DAG.getExtLoad(ISD::SEXTLOAD, dl, PTy, Chain, Addr,
PseudoSourceValue::getJumpTable(), 0, MemVT);
Addr = LD;
@@ -2834,7 +2834,7 @@
Addr = DAG.getNode(ISD::ADD, dl, PTy, Addr,
TLI.getPICJumpTableRelocBase(Table, DAG));
}
- Tmp1 = DAG.getNode(ISD::BRIND, dl, MVT::Other, LD.getValue(1), Addr);
+ Tmp1 = DAG.getNode(ISD::BRIND, dl, EVT::Other, LD.getValue(1), Addr);
Results.push_back(Tmp1);
break;
}
@@ -2844,12 +2844,12 @@
Tmp1 = Node->getOperand(0);
Tmp2 = Node->getOperand(1);
if (Tmp2.getOpcode() == ISD::SETCC) {
- Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other,
+ Tmp1 = DAG.getNode(ISD::BR_CC, dl, EVT::Other,
Tmp1, Tmp2.getOperand(2),
Tmp2.getOperand(0), Tmp2.getOperand(1),
Node->getOperand(2));
} else {
- Tmp1 = DAG.getNode(ISD::BR_CC, dl, MVT::Other, Tmp1,
+ Tmp1 = DAG.getNode(ISD::BR_CC, dl, EVT::Other, Tmp1,
DAG.getCondCode(ISD::SETNE), Tmp2,
DAG.getConstant(0, Tmp2.getValueType()),
Node->getOperand(2));
@@ -2870,7 +2870,7 @@
// Otherwise, SETCC for the given comparison type must be completely
// illegal; expand it into a SELECT_CC.
- MVT VT = Node->getValueType(0);
+ EVT VT = Node->getValueType(0);
Tmp1 = DAG.getNode(ISD::SELECT_CC, dl, VT, Tmp1, Tmp2,
DAG.getConstant(1, VT), DAG.getConstant(0, VT), Tmp3);
Results.push_back(Tmp1);
@@ -2929,13 +2929,13 @@
}
void SelectionDAGLegalize::PromoteNode(SDNode *Node,
SmallVectorImpl<SDValue> &Results) {
- MVT OVT = Node->getValueType(0);
+ EVT OVT = Node->getValueType(0);
if (Node->getOpcode() == ISD::UINT_TO_FP ||
Node->getOpcode() == ISD::SINT_TO_FP ||
Node->getOpcode() == ISD::SETCC) {
OVT = Node->getOperand(0).getValueType();
}
- MVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
+ EVT NVT = TLI.getTypeToPromoteTo(Node->getOpcode(), OVT);
DebugLoc dl = Node->getDebugLoc();
SDValue Tmp1, Tmp2, Tmp3;
switch (Node->getOpcode()) {
diff --git a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
index 5957e3a..ebaf2fb 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp
@@ -25,16 +25,16 @@
using namespace llvm;
/// GetFPLibCall - Return the right libcall for the given floating point type.
-static RTLIB::Libcall GetFPLibCall(MVT VT,
+static RTLIB::Libcall GetFPLibCall(EVT VT,
RTLIB::Libcall Call_F32,
RTLIB::Libcall Call_F64,
RTLIB::Libcall Call_F80,
RTLIB::Libcall Call_PPCF128) {
return
- VT == MVT::f32 ? Call_F32 :
- VT == MVT::f64 ? Call_F64 :
- VT == MVT::f80 ? Call_F80 :
- VT == MVT::ppcf128 ? Call_PPCF128 :
+ VT == EVT::f32 ? Call_F32 :
+ VT == EVT::f64 ? Call_F64 :
+ VT == EVT::f80 ? Call_F80 :
+ VT == EVT::ppcf128 ? Call_PPCF128 :
RTLIB::UNKNOWN_LIBCALL;
}
@@ -126,7 +126,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FABS(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned Size = NVT.getSizeInBits();
// Mask = ~(1 << (Size-1))
@@ -137,7 +137,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FADD(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
@@ -149,7 +149,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FCEIL(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::CEIL_F32,
@@ -164,8 +164,8 @@
SDValue RHS = BitConvertToInteger(N->getOperand(1));
DebugLoc dl = N->getDebugLoc();
- MVT LVT = LHS.getValueType();
- MVT RVT = RHS.getValueType();
+ EVT LVT = LHS.getValueType();
+ EVT RVT = RHS.getValueType();
unsigned LSize = LVT.getSizeInBits();
unsigned RSize = RVT.getSizeInBits();
@@ -200,7 +200,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FCOS(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::COS_F32,
@@ -211,7 +211,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FDIV(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
@@ -223,7 +223,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::EXP_F32,
@@ -234,7 +234,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FEXP2(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::EXP2_F32,
@@ -245,7 +245,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FFLOOR(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::FLOOR_F32,
@@ -256,7 +256,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::LOG_F32,
@@ -267,7 +267,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG2(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::LOG2_F32,
@@ -278,7 +278,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FLOG10(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::LOG10_F32,
@@ -289,7 +289,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FMUL(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
@@ -301,7 +301,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FNEARBYINT(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::NEARBYINT_F32,
@@ -312,7 +312,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FNEG(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
// Expand Y = FNEG(X) -> Y = SUB -0.0, X
SDValue Ops[2] = { DAG.getConstantFP(-0.0, N->getValueType(0)),
GetSoftenedFloat(N->getOperand(0)) };
@@ -325,7 +325,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FP_EXTEND(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = N->getOperand(0);
RTLIB::Libcall LC = RTLIB::getFPEXT(Op.getValueType(), N->getValueType(0));
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_EXTEND!");
@@ -333,7 +333,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FP_ROUND(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = N->getOperand(0);
RTLIB::Libcall LC = RTLIB::getFPROUND(Op.getValueType(), N->getValueType(0));
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND!");
@@ -341,7 +341,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FPOW(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
@@ -353,9 +353,9 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FPOWI(SDNode *N) {
- assert(N->getOperand(1).getValueType() == MVT::i32 &&
+ assert(N->getOperand(1).getValueType() == EVT::i32 &&
"Unsupported power type!");
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)), N->getOperand(1) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::POWI_F32,
@@ -366,7 +366,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FREM(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
@@ -378,7 +378,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FRINT(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::RINT_F32,
@@ -389,7 +389,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FSIN(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::SIN_F32,
@@ -400,7 +400,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FSQRT(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::SQRT_F32,
@@ -411,7 +411,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FSUB(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Ops[2] = { GetSoftenedFloat(N->getOperand(0)),
GetSoftenedFloat(N->getOperand(1)) };
return MakeLibCall(GetFPLibCall(N->getValueType(0),
@@ -423,7 +423,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatRes_FTRUNC(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Op = GetSoftenedFloat(N->getOperand(0));
return MakeLibCall(GetFPLibCall(N->getValueType(0),
RTLIB::TRUNC_F32,
@@ -435,8 +435,8 @@
SDValue DAGTypeLegalizer::SoftenFloatRes_LOAD(SDNode *N) {
LoadSDNode *L = cast<LoadSDNode>(N);
- MVT VT = N->getValueType(0);
- MVT NVT = TLI.getTypeToTransformTo(VT);
+ EVT VT = N->getValueType(0);
+ EVT NVT = TLI.getTypeToTransformTo(VT);
DebugLoc dl = N->getDebugLoc();
SDValue NewL;
@@ -486,8 +486,8 @@
SDValue DAGTypeLegalizer::SoftenFloatRes_VAARG(SDNode *N) {
SDValue Chain = N->getOperand(0); // Get the chain.
SDValue Ptr = N->getOperand(1); // Get the pointer.
- MVT VT = N->getValueType(0);
- MVT NVT = TLI.getTypeToTransformTo(VT);
+ EVT VT = N->getValueType(0);
+ EVT NVT = TLI.getTypeToTransformTo(VT);
DebugLoc dl = N->getDebugLoc();
SDValue NewVAARG;
@@ -501,18 +501,18 @@
SDValue DAGTypeLegalizer::SoftenFloatRes_XINT_TO_FP(SDNode *N) {
bool Signed = N->getOpcode() == ISD::SINT_TO_FP;
- MVT SVT = N->getOperand(0).getValueType();
- MVT RVT = N->getValueType(0);
- MVT NVT = MVT();
+ EVT SVT = N->getOperand(0).getValueType();
+ EVT RVT = N->getValueType(0);
+ EVT NVT = EVT();
DebugLoc dl = N->getDebugLoc();
// If the input is not legal, eg: i1 -> fp, then it needs to be promoted to
// a larger type, eg: i8 -> fp. Even if it is legal, no libcall may exactly
// match. Look for an appropriate libcall.
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- for (unsigned t = MVT::FIRST_INTEGER_VALUETYPE;
- t <= MVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) {
- NVT = (MVT::SimpleValueType)t;
+ for (unsigned t = EVT::FIRST_INTEGER_VALUETYPE;
+ t <= EVT::LAST_INTEGER_VALUETYPE && LC == RTLIB::UNKNOWN_LIBCALL; ++t) {
+ NVT = (EVT::SimpleValueType)t;
// The source needs to big enough to hold the operand.
if (NVT.bitsGE(SVT))
LC = Signed ? RTLIB::getSINTTOFP(NVT, RVT):RTLIB::getUINTTOFP (NVT, RVT);
@@ -574,70 +574,70 @@
ISD::CondCode &CCCode, DebugLoc dl) {
SDValue LHSInt = GetSoftenedFloat(NewLHS);
SDValue RHSInt = GetSoftenedFloat(NewRHS);
- MVT VT = NewLHS.getValueType();
+ EVT VT = NewLHS.getValueType();
- assert((VT == MVT::f32 || VT == MVT::f64) && "Unsupported setcc type!");
+ assert((VT == EVT::f32 || VT == EVT::f64) && "Unsupported setcc type!");
// Expand into one or more soft-fp libcall(s).
RTLIB::Libcall LC1 = RTLIB::UNKNOWN_LIBCALL, LC2 = RTLIB::UNKNOWN_LIBCALL;
switch (CCCode) {
case ISD::SETEQ:
case ISD::SETOEQ:
- LC1 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
break;
case ISD::SETNE:
case ISD::SETUNE:
- LC1 = (VT == MVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::UNE_F32 : RTLIB::UNE_F64;
break;
case ISD::SETGE:
case ISD::SETOGE:
- LC1 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
break;
case ISD::SETLT:
case ISD::SETOLT:
- LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
break;
case ISD::SETLE:
case ISD::SETOLE:
- LC1 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
break;
case ISD::SETGT:
case ISD::SETOGT:
- LC1 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
break;
case ISD::SETUO:
- LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
break;
case ISD::SETO:
- LC1 = (VT == MVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::O_F32 : RTLIB::O_F64;
break;
default:
- LC1 = (VT == MVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::UO_F32 : RTLIB::UO_F64;
switch (CCCode) {
case ISD::SETONE:
// SETONE = SETOLT | SETOGT
- LC1 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
+ LC1 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
// Fallthrough
case ISD::SETUGT:
- LC2 = (VT == MVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
+ LC2 = (VT == EVT::f32) ? RTLIB::OGT_F32 : RTLIB::OGT_F64;
break;
case ISD::SETUGE:
- LC2 = (VT == MVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
+ LC2 = (VT == EVT::f32) ? RTLIB::OGE_F32 : RTLIB::OGE_F64;
break;
case ISD::SETULT:
- LC2 = (VT == MVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
+ LC2 = (VT == EVT::f32) ? RTLIB::OLT_F32 : RTLIB::OLT_F64;
break;
case ISD::SETULE:
- LC2 = (VT == MVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
+ LC2 = (VT == EVT::f32) ? RTLIB::OLE_F32 : RTLIB::OLE_F64;
break;
case ISD::SETUEQ:
- LC2 = (VT == MVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
+ LC2 = (VT == EVT::f32) ? RTLIB::OEQ_F32 : RTLIB::OEQ_F64;
break;
default: assert(false && "Do not know how to soften this setcc!");
}
}
- MVT RetVT = MVT::i32; // FIXME: is this the correct return type?
+ EVT RetVT = EVT::i32; // FIXME: is this the correct return type?
SDValue Ops[2] = { LHSInt, RHSInt };
NewLHS = MakeLibCall(LC1, RetVT, Ops, 2, false/*sign irrelevant*/, dl);
NewRHS = DAG.getConstant(0, RetVT);
@@ -659,8 +659,8 @@
}
SDValue DAGTypeLegalizer::SoftenFloatOp_FP_ROUND(SDNode *N) {
- MVT SVT = N->getOperand(0).getValueType();
- MVT RVT = N->getValueType(0);
+ EVT SVT = N->getOperand(0).getValueType();
+ EVT RVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getFPROUND(SVT, RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_ROUND libcall");
@@ -688,7 +688,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_SINT(SDNode *N) {
- MVT RVT = N->getValueType(0);
+ EVT RVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!");
SDValue Op = GetSoftenedFloat(N->getOperand(0));
@@ -696,7 +696,7 @@
}
SDValue DAGTypeLegalizer::SoftenFloatOp_FP_TO_UINT(SDNode *N) {
- MVT RVT = N->getValueType(0);
+ EVT RVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getFPTOUINT(N->getOperand(0).getValueType(), RVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_UINT!");
SDValue Op = GetSoftenedFloat(N->getOperand(0));
@@ -829,7 +829,7 @@
void DAGTypeLegalizer::ExpandFloatRes_ConstantFP(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
assert(NVT.getSizeInBits() == integerPartWidth &&
"Do not know how to expand this float constant!");
APInt C = cast<ConstantFPSDNode>(N)->getValueAPF().bitcastToAPInt();
@@ -841,7 +841,7 @@
void DAGTypeLegalizer::ExpandFloatRes_FABS(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- assert(N->getValueType(0) == MVT::ppcf128 &&
+ assert(N->getValueType(0) == EVT::ppcf128 &&
"Logic only correct for ppcf128!");
DebugLoc dl = N->getDebugLoc();
SDValue Tmp;
@@ -981,7 +981,7 @@
void DAGTypeLegalizer::ExpandFloatRes_FP_EXTEND(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
Hi = DAG.getNode(ISD::FP_EXTEND, N->getDebugLoc(), NVT, N->getOperand(0));
Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT);
}
@@ -1066,7 +1066,7 @@
SDValue Ptr = LD->getBasePtr();
DebugLoc dl = N->getDebugLoc();
- MVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0));
assert(NVT.isByteSized() && "Expanded type not byte sized!");
assert(LD->getMemoryVT().bitsLE(NVT) && "Float type not round?");
@@ -1088,31 +1088,31 @@
void DAGTypeLegalizer::ExpandFloatRes_XINT_TO_FP(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- assert(N->getValueType(0) == MVT::ppcf128 && "Unsupported XINT_TO_FP!");
- MVT VT = N->getValueType(0);
- MVT NVT = TLI.getTypeToTransformTo(VT);
+ assert(N->getValueType(0) == EVT::ppcf128 && "Unsupported XINT_TO_FP!");
+ EVT VT = N->getValueType(0);
+ EVT NVT = TLI.getTypeToTransformTo(VT);
SDValue Src = N->getOperand(0);
- MVT SrcVT = Src.getValueType();
+ EVT SrcVT = Src.getValueType();
bool isSigned = N->getOpcode() == ISD::SINT_TO_FP;
DebugLoc dl = N->getDebugLoc();
// First do an SINT_TO_FP, whether the original was signed or unsigned.
// When promoting partial word types to i32 we must honor the signedness,
// though.
- if (SrcVT.bitsLE(MVT::i32)) {
+ if (SrcVT.bitsLE(EVT::i32)) {
// The integer can be represented exactly in an f64.
Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
- MVT::i32, Src);
+ EVT::i32, Src);
Lo = DAG.getConstantFP(APFloat(APInt(NVT.getSizeInBits(), 0)), NVT);
Hi = DAG.getNode(ISD::SINT_TO_FP, dl, NVT, Src);
} else {
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (SrcVT.bitsLE(MVT::i64)) {
+ if (SrcVT.bitsLE(EVT::i64)) {
Src = DAG.getNode(isSigned ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND, dl,
- MVT::i64, Src);
+ EVT::i64, Src);
LC = RTLIB::SINTTOFP_I64_PPCF128;
- } else if (SrcVT.bitsLE(MVT::i128)) {
- Src = DAG.getNode(ISD::SIGN_EXTEND, dl, MVT::i128, Src);
+ } else if (SrcVT.bitsLE(EVT::i128)) {
+ Src = DAG.getNode(ISD::SIGN_EXTEND, dl, EVT::i128, Src);
LC = RTLIB::SINTTOFP_I128_PPCF128;
}
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported XINT_TO_FP!");
@@ -1137,20 +1137,20 @@
switch (SrcVT.getSimpleVT()) {
default:
assert(false && "Unsupported UINT_TO_FP!");
- case MVT::i32:
+ case EVT::i32:
Parts = TwoE32;
break;
- case MVT::i64:
+ case EVT::i64:
Parts = TwoE64;
break;
- case MVT::i128:
+ case EVT::i128:
Parts = TwoE128;
break;
}
Lo = DAG.getNode(ISD::FADD, dl, VT, Hi,
DAG.getConstantFP(APFloat(APInt(128, 2, Parts)),
- MVT::ppcf128));
+ EVT::ppcf128));
Lo = DAG.getNode(ISD::SELECT_CC, dl, VT, Src, DAG.getConstant(0, SrcVT),
Lo, Hi, DAG.getCondCode(ISD::SETLT));
GetPairElements(Lo, Lo, Hi);
@@ -1222,8 +1222,8 @@
GetExpandedFloat(NewLHS, LHSLo, LHSHi);
GetExpandedFloat(NewRHS, RHSLo, RHSHi);
- MVT VT = NewLHS.getValueType();
- assert(VT == MVT::ppcf128 && "Unsupported setcc type!");
+ EVT VT = NewLHS.getValueType();
+ assert(VT == EVT::ppcf128 && "Unsupported setcc type!");
// FIXME: This generated code sucks. We want to generate
// FCMPU crN, hi1, hi2
@@ -1264,7 +1264,7 @@
}
SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) {
- assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
+ assert(N->getOperand(0).getValueType() == EVT::ppcf128 &&
"Logic only correct for ppcf128!");
SDValue Lo, Hi;
GetExpandedFloat(N->getOperand(0), Lo, Hi);
@@ -1274,19 +1274,19 @@
}
SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) {
- MVT RVT = N->getValueType(0);
+ EVT RVT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
// Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
// PPC (the libcall is not available). FIXME: Do this in a less hacky way.
- if (RVT == MVT::i32) {
- assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
+ if (RVT == EVT::i32) {
+ assert(N->getOperand(0).getValueType() == EVT::ppcf128 &&
"Logic only correct for ppcf128!");
- SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, MVT::ppcf128,
- N->getOperand(0), DAG.getValueType(MVT::f64));
- Res = DAG.getNode(ISD::FP_ROUND, dl, MVT::f64, Res,
+ SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, dl, EVT::ppcf128,
+ N->getOperand(0), DAG.getValueType(EVT::f64));
+ Res = DAG.getNode(ISD::FP_ROUND, dl, EVT::f64, Res,
DAG.getIntPtrConstant(1));
- return DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Res);
+ return DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, Res);
}
RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT);
@@ -1295,29 +1295,29 @@
}
SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_UINT(SDNode *N) {
- MVT RVT = N->getValueType(0);
+ EVT RVT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
// Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on
// PPC (the libcall is not available). FIXME: Do this in a less hacky way.
- if (RVT == MVT::i32) {
- assert(N->getOperand(0).getValueType() == MVT::ppcf128 &&
+ if (RVT == EVT::i32) {
+ assert(N->getOperand(0).getValueType() == EVT::ppcf128 &&
"Logic only correct for ppcf128!");
const uint64_t TwoE31[] = {0x41e0000000000000LL, 0};
APFloat APF = APFloat(APInt(128, 2, TwoE31));
- SDValue Tmp = DAG.getConstantFP(APF, MVT::ppcf128);
+ SDValue Tmp = DAG.getConstantFP(APF, EVT::ppcf128);
// X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X
// FIXME: generated code sucks.
- return DAG.getNode(ISD::SELECT_CC, dl, MVT::i32, N->getOperand(0), Tmp,
- DAG.getNode(ISD::ADD, dl, MVT::i32,
- DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32,
+ return DAG.getNode(ISD::SELECT_CC, dl, EVT::i32, N->getOperand(0), Tmp,
+ DAG.getNode(ISD::ADD, dl, EVT::i32,
+ DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32,
DAG.getNode(ISD::FSUB, dl,
- MVT::ppcf128,
+ EVT::ppcf128,
N->getOperand(0),
Tmp)),
- DAG.getConstant(0x80000000, MVT::i32)),
+ DAG.getConstant(0x80000000, EVT::i32)),
DAG.getNode(ISD::FP_TO_SINT, dl,
- MVT::i32, N->getOperand(0)),
+ EVT::i32, N->getOperand(0)),
DAG.getCondCode(ISD::SETGE));
}
@@ -1372,7 +1372,7 @@
SDValue Chain = ST->getChain();
SDValue Ptr = ST->getBasePtr();
- MVT NVT = TLI.getTypeToTransformTo(ST->getValue().getValueType());
+ EVT NVT = TLI.getTypeToTransformTo(ST->getValue().getValueType());
assert(NVT.isByteSized() && "Expanded type not byte sized!");
assert(ST->getMemoryVT().bitsLE(NVT) && "Float type not round?");
diff --git a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
index 5be0706..b1b2ae3 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
@@ -162,10 +162,10 @@
SDValue DAGTypeLegalizer::PromoteIntRes_BIT_CONVERT(SDNode *N) {
SDValue InOp = N->getOperand(0);
- MVT InVT = InOp.getValueType();
- MVT NInVT = TLI.getTypeToTransformTo(InVT);
- MVT OutVT = N->getValueType(0);
- MVT NOutVT = TLI.getTypeToTransformTo(OutVT);
+ EVT InVT = InOp.getValueType();
+ EVT NInVT = TLI.getTypeToTransformTo(InVT);
+ EVT OutVT = N->getValueType(0);
+ EVT NOutVT = TLI.getTypeToTransformTo(OutVT);
DebugLoc dl = N->getDebugLoc();
switch (getTypeAction(InVT)) {
@@ -202,7 +202,7 @@
std::swap(Lo, Hi);
InOp = DAG.getNode(ISD::ANY_EXTEND, dl,
- MVT::getIntegerVT(NOutVT.getSizeInBits()),
+ EVT::getIntegerVT(NOutVT.getSizeInBits()),
JoinIntegers(Lo, Hi));
return DAG.getNode(ISD::BIT_CONVERT, dl, NOutVT, InOp);
}
@@ -218,8 +218,8 @@
SDValue DAGTypeLegalizer::PromoteIntRes_BSWAP(SDNode *N) {
SDValue Op = GetPromotedInteger(N->getOperand(0));
- MVT OVT = N->getValueType(0);
- MVT NVT = Op.getValueType();
+ EVT OVT = N->getValueType(0);
+ EVT NVT = Op.getValueType();
DebugLoc dl = N->getDebugLoc();
unsigned DiffBits = NVT.getSizeInBits() - OVT.getSizeInBits();
@@ -236,7 +236,7 @@
}
SDValue DAGTypeLegalizer::PromoteIntRes_Constant(SDNode *N) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
// FIXME there is no actual debug info here
DebugLoc dl = N->getDebugLoc();
// Zero extend things like i1, sign extend everything else. It shouldn't
@@ -254,7 +254,7 @@
CvtCode == ISD::CVT_US || CvtCode == ISD::CVT_UU ||
CvtCode == ISD::CVT_SF || CvtCode == ISD::CVT_UF) &&
"can only promote integers");
- MVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT OutVT = TLI.getTypeToTransformTo(N->getValueType(0));
return DAG.getConvertRndSat(OutVT, N->getDebugLoc(), N->getOperand(0),
N->getOperand(1), N->getOperand(2),
N->getOperand(3), N->getOperand(4), CvtCode);
@@ -264,8 +264,8 @@
// Zero extend to the promoted type and do the count there.
SDValue Op = ZExtPromotedInteger(N->getOperand(0));
DebugLoc dl = N->getDebugLoc();
- MVT OVT = N->getValueType(0);
- MVT NVT = Op.getValueType();
+ EVT OVT = N->getValueType(0);
+ EVT NVT = Op.getValueType();
Op = DAG.getNode(ISD::CTLZ, dl, NVT, Op);
// Subtract off the extra leading bits in the bigger type.
return DAG.getNode(ISD::SUB, dl, NVT, Op,
@@ -281,8 +281,8 @@
SDValue DAGTypeLegalizer::PromoteIntRes_CTTZ(SDNode *N) {
SDValue Op = GetPromotedInteger(N->getOperand(0));
- MVT OVT = N->getValueType(0);
- MVT NVT = Op.getValueType();
+ EVT OVT = N->getValueType(0);
+ EVT NVT = Op.getValueType();
DebugLoc dl = N->getDebugLoc();
// The count is the same in the promoted type except if the original
// value was zero. This can be handled by setting the bit just off
@@ -295,13 +295,13 @@
SDValue DAGTypeLegalizer::PromoteIntRes_EXTRACT_VECTOR_ELT(SDNode *N) {
DebugLoc dl = N->getDebugLoc();
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, NVT, N->getOperand(0),
N->getOperand(1));
}
SDValue DAGTypeLegalizer::PromoteIntRes_FP_TO_XINT(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned NewOpc = N->getOpcode();
DebugLoc dl = N->getDebugLoc();
@@ -325,7 +325,7 @@
}
SDValue DAGTypeLegalizer::PromoteIntRes_INT_EXTEND(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
DebugLoc dl = N->getDebugLoc();
if (getTypeAction(N->getOperand(0).getValueType()) == PromoteInteger) {
@@ -352,7 +352,7 @@
SDValue DAGTypeLegalizer::PromoteIntRes_LOAD(LoadSDNode *N) {
assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
ISD::LoadExtType ExtType =
ISD::isNON_EXTLoad(N) ? ISD::EXTLOAD : N->getExtensionType();
DebugLoc dl = N->getDebugLoc();
@@ -370,8 +370,8 @@
/// Promote the overflow flag of an overflowing arithmetic node.
SDValue DAGTypeLegalizer::PromoteIntRes_Overflow(SDNode *N) {
// Simply change the return type of the boolean result.
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(1));
- MVT ValueVTs[] = { N->getValueType(0), NVT };
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(1));
+ EVT ValueVTs[] = { N->getValueType(0), NVT };
SDValue Ops[] = { N->getOperand(0), N->getOperand(1) };
SDValue Res = DAG.getNode(N->getOpcode(), N->getDebugLoc(),
DAG.getVTList(ValueVTs, 2), Ops, 2);
@@ -391,8 +391,8 @@
// sign extension of its truncation to the original type.
SDValue LHS = SExtPromotedInteger(N->getOperand(0));
SDValue RHS = SExtPromotedInteger(N->getOperand(1));
- MVT OVT = N->getOperand(0).getValueType();
- MVT NVT = LHS.getValueType();
+ EVT OVT = N->getOperand(0).getValueType();
+ EVT NVT = LHS.getValueType();
DebugLoc dl = N->getDebugLoc();
// Do the arithmetic in the larger type.
@@ -436,7 +436,7 @@
}
SDValue DAGTypeLegalizer::PromoteIntRes_SETCC(SDNode *N) {
- MVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
+ EVT SVT = TLI.getSetCCResultType(N->getOperand(0).getValueType());
assert(isTypeLegal(SVT) && "Illegal SetCC type!");
DebugLoc dl = N->getDebugLoc();
@@ -445,7 +445,7 @@
N->getOperand(1), N->getOperand(2));
// Convert to the expected type.
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
assert(NVT.bitsLE(SVT) && "Integer type overpromoted?");
return DAG.getNode(ISD::TRUNCATE, dl, NVT, SetCC);
}
@@ -481,14 +481,14 @@
SDValue DAGTypeLegalizer::PromoteIntRes_SRL(SDNode *N) {
// The input value must be properly zero extended.
- MVT VT = N->getValueType(0);
- MVT NVT = TLI.getTypeToTransformTo(VT);
+ EVT VT = N->getValueType(0);
+ EVT NVT = TLI.getTypeToTransformTo(VT);
SDValue Res = ZExtPromotedInteger(N->getOperand(0));
return DAG.getNode(ISD::SRL, N->getDebugLoc(), NVT, Res, N->getOperand(1));
}
SDValue DAGTypeLegalizer::PromoteIntRes_TRUNCATE(SDNode *N) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Res;
switch (getTypeAction(N->getOperand(0).getValueType())) {
@@ -514,8 +514,8 @@
// zero extension of its truncation to the original type.
SDValue LHS = ZExtPromotedInteger(N->getOperand(0));
SDValue RHS = ZExtPromotedInteger(N->getOperand(1));
- MVT OVT = N->getOperand(0).getValueType();
- MVT NVT = LHS.getValueType();
+ EVT OVT = N->getOperand(0).getValueType();
+ EVT NVT = LHS.getValueType();
DebugLoc dl = N->getDebugLoc();
// Do the arithmetic in the larger type.
@@ -549,10 +549,10 @@
SDValue DAGTypeLegalizer::PromoteIntRes_VAARG(SDNode *N) {
SDValue Chain = N->getOperand(0); // Get the chain.
SDValue Ptr = N->getOperand(1); // Get the pointer.
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
- MVT RegVT = TLI.getRegisterType(VT);
+ EVT RegVT = TLI.getRegisterType(VT);
unsigned NumRegs = TLI.getNumRegisters(VT);
// The argument is passed as NumRegs registers of type RegVT.
@@ -567,7 +567,7 @@
std::reverse(Parts.begin(), Parts.end());
// Assemble the parts in the promoted type.
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Res = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[0]);
for (unsigned i = 1; i < NumRegs; ++i) {
SDValue Part = DAG.getNode(ISD::ZERO_EXTEND, dl, NVT, Parts[i]);
@@ -718,7 +718,7 @@
assert(OpNo == 1 && "only know how to promote condition");
// Promote all the way up to the canonical SetCC type.
- MVT SVT = TLI.getSetCCResultType(MVT::Other);
+ EVT SVT = TLI.getSetCCResultType(EVT::Other);
SDValue Cond = PromoteTargetBoolean(N->getOperand(1), SVT);
// The chain (Op#0) and basic block destination (Op#2) are always legal types.
@@ -728,7 +728,7 @@
SDValue DAGTypeLegalizer::PromoteIntOp_BUILD_PAIR(SDNode *N) {
// Since the result type is legal, the operands must promote to it.
- MVT OVT = N->getOperand(0).getValueType();
+ EVT OVT = N->getOperand(0).getValueType();
SDValue Lo = ZExtPromotedInteger(N->getOperand(0));
SDValue Hi = GetPromotedInteger(N->getOperand(1));
assert(Lo.getValueType() == N->getValueType(0) && "Operand over promoted?");
@@ -743,7 +743,7 @@
// The vector type is legal but the element type is not. This implies
// that the vector is a power-of-two in length and that the element
// type does not have a strange size (eg: it is not i1).
- MVT VecVT = N->getValueType(0);
+ EVT VecVT = N->getValueType(0);
unsigned NumElts = VecVT.getVectorNumElements();
assert(!(NumElts & 1) && "Legal vector of one illegal element?");
@@ -802,7 +802,7 @@
NewOps[0] = N->getOperand(0);
for (unsigned i = 1; i < array_lengthof(NewOps); ++i) {
SDValue Flag = GetPromotedInteger(N->getOperand(i));
- NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, MVT::i1);
+ NewOps[i] = DAG.getZeroExtendInReg(Flag, dl, EVT::i1);
}
return DAG.UpdateNodeOperands(SDValue (N, 0), NewOps,
array_lengthof(NewOps));
@@ -819,7 +819,7 @@
assert(OpNo == 0 && "Only know how to promote condition");
// Promote all the way up to the canonical SetCC type.
- MVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
+ EVT SVT = TLI.getSetCCResultType(N->getOperand(1).getValueType());
SDValue Cond = PromoteTargetBoolean(N->getOperand(0), SVT);
return DAG.UpdateNodeOperands(SDValue(N, 0), Cond,
@@ -990,10 +990,10 @@
SDValue InL, InH;
GetExpandedInteger(N->getOperand(0), InL, InH);
- MVT NVT = InL.getValueType();
+ EVT NVT = InL.getValueType();
unsigned VTBits = N->getValueType(0).getSizeInBits();
unsigned NVTBits = NVT.getSizeInBits();
- MVT ShTy = N->getOperand(1).getValueType();
+ EVT ShTy = N->getOperand(1).getValueType();
if (N->getOpcode() == ISD::SHL) {
if (Amt > VTBits) {
@@ -1009,7 +1009,7 @@
TLI.isOperationLegalOrCustom(ISD::ADDC,
TLI.getTypeToExpandTo(NVT))) {
// Emit this X << 1 as X+X.
- SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
+ SDVTList VTList = DAG.getVTList(NVT, EVT::Flag);
SDValue LoOps[2] = { InL, InL };
Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
SDValue HiOps[3] = { InH, InH, Lo.getValue(1) };
@@ -1077,8 +1077,8 @@
bool DAGTypeLegalizer::
ExpandShiftWithKnownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
SDValue Amt = N->getOperand(1);
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
- MVT ShTy = Amt.getValueType();
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT ShTy = Amt.getValueType();
unsigned ShBits = ShTy.getSizeInBits();
unsigned NVTBits = NVT.getSizeInBits();
assert(isPowerOf2_32(NVTBits) &&
@@ -1155,8 +1155,8 @@
bool DAGTypeLegalizer::
ExpandShiftWithUnknownAmountBit(SDNode *N, SDValue &Lo, SDValue &Hi) {
SDValue Amt = N->getOperand(1);
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
- MVT ShTy = Amt.getValueType();
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT ShTy = Amt.getValueType();
unsigned NVTBits = NVT.getSizeInBits();
assert(isPowerOf2_32(NVTBits) &&
"Expanded integer type size not a power of two!");
@@ -1230,14 +1230,14 @@
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
- MVT NVT = LHSL.getValueType();
+ EVT NVT = LHSL.getValueType();
SDValue LoOps[2] = { LHSL, RHSL };
SDValue HiOps[3] = { LHSH, RHSH };
// Do not generate ADDC/ADDE or SUBC/SUBE if the target does not support
// them. TODO: Teach operation legalization how to expand unsupported
// ADDC/ADDE/SUBC/SUBE. The problem is that these operations generate
- // a carry of type MVT::Flag, but there doesn't seem to be any way to
+ // a carry of type EVT::Flag, but there doesn't seem to be any way to
// generate a value of this type in the expanded code sequence.
bool hasCarry =
TLI.isOperationLegalOrCustom(N->getOpcode() == ISD::ADD ?
@@ -1245,7 +1245,7 @@
TLI.getTypeToExpandTo(NVT));
if (hasCarry) {
- SDVTList VTList = DAG.getVTList(NVT, MVT::Flag);
+ SDVTList VTList = DAG.getVTList(NVT, EVT::Flag);
if (N->getOpcode() == ISD::ADD) {
Lo = DAG.getNode(ISD::ADDC, dl, VTList, LoOps, 2);
HiOps[2] = Lo.getValue(1);
@@ -1290,7 +1290,7 @@
DebugLoc dl = N->getDebugLoc();
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
- SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
+ SDVTList VTList = DAG.getVTList(LHSL.getValueType(), EVT::Flag);
SDValue LoOps[2] = { LHSL, RHSL };
SDValue HiOps[3] = { LHSH, RHSH };
@@ -1316,7 +1316,7 @@
DebugLoc dl = N->getDebugLoc();
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
GetExpandedInteger(N->getOperand(1), RHSL, RHSH);
- SDVTList VTList = DAG.getVTList(LHSL.getValueType(), MVT::Flag);
+ SDVTList VTList = DAG.getVTList(LHSL.getValueType(), EVT::Flag);
SDValue LoOps[3] = { LHSL, RHSL, N->getOperand(2) };
SDValue HiOps[3] = { LHSH, RHSH };
@@ -1331,7 +1331,7 @@
void DAGTypeLegalizer::ExpandIntRes_ANY_EXTEND(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
DebugLoc dl = N->getDebugLoc();
SDValue Op = N->getOperand(0);
if (Op.getValueType().bitsLE(NVT)) {
@@ -1355,14 +1355,14 @@
SDValue &Lo, SDValue &Hi) {
DebugLoc dl = N->getDebugLoc();
GetExpandedInteger(N->getOperand(0), Lo, Hi);
- MVT NVT = Lo.getValueType();
- MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
+ EVT NVT = Lo.getValueType();
+ EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
unsigned NVTBits = NVT.getSizeInBits();
unsigned EVTBits = EVT.getSizeInBits();
if (NVTBits < EVTBits) {
Hi = DAG.getNode(ISD::AssertSext, dl, NVT, Hi,
- DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
+ DAG.getValueType(EVT::getIntegerVT(EVTBits - NVTBits)));
} else {
Lo = DAG.getNode(ISD::AssertSext, dl, NVT, Lo, DAG.getValueType(EVT));
// The high part replicates the sign bit of Lo, make it explicit.
@@ -1375,14 +1375,14 @@
SDValue &Lo, SDValue &Hi) {
DebugLoc dl = N->getDebugLoc();
GetExpandedInteger(N->getOperand(0), Lo, Hi);
- MVT NVT = Lo.getValueType();
- MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
+ EVT NVT = Lo.getValueType();
+ EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
unsigned NVTBits = NVT.getSizeInBits();
unsigned EVTBits = EVT.getSizeInBits();
if (NVTBits < EVTBits) {
Hi = DAG.getNode(ISD::AssertZext, dl, NVT, Hi,
- DAG.getValueType(MVT::getIntegerVT(EVTBits - NVTBits)));
+ DAG.getValueType(EVT::getIntegerVT(EVTBits - NVTBits)));
} else {
Lo = DAG.getNode(ISD::AssertZext, dl, NVT, Lo, DAG.getValueType(EVT));
// The high part must be zero, make it explicit.
@@ -1400,7 +1400,7 @@
void DAGTypeLegalizer::ExpandIntRes_Constant(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned NBitWidth = NVT.getSizeInBits();
const APInt &Cst = cast<ConstantSDNode>(N)->getAPIntValue();
Lo = DAG.getConstant(APInt(Cst).trunc(NBitWidth), NVT);
@@ -1412,7 +1412,7 @@
DebugLoc dl = N->getDebugLoc();
// ctlz (HiLo) -> Hi != 0 ? ctlz(Hi) : (ctlz(Lo)+32)
GetExpandedInteger(N->getOperand(0), Lo, Hi);
- MVT NVT = Lo.getValueType();
+ EVT NVT = Lo.getValueType();
SDValue HiNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Hi,
DAG.getConstant(0, NVT), ISD::SETNE);
@@ -1431,7 +1431,7 @@
DebugLoc dl = N->getDebugLoc();
// ctpop(HiLo) -> ctpop(Hi)+ctpop(Lo)
GetExpandedInteger(N->getOperand(0), Lo, Hi);
- MVT NVT = Lo.getValueType();
+ EVT NVT = Lo.getValueType();
Lo = DAG.getNode(ISD::ADD, dl, NVT, DAG.getNode(ISD::CTPOP, dl, NVT, Lo),
DAG.getNode(ISD::CTPOP, dl, NVT, Hi));
Hi = DAG.getConstant(0, NVT);
@@ -1442,7 +1442,7 @@
DebugLoc dl = N->getDebugLoc();
// cttz (HiLo) -> Lo != 0 ? cttz(Lo) : (cttz(Hi)+32)
GetExpandedInteger(N->getOperand(0), Lo, Hi);
- MVT NVT = Lo.getValueType();
+ EVT NVT = Lo.getValueType();
SDValue LoNotZero = DAG.getSetCC(dl, TLI.getSetCCResultType(NVT), Lo,
DAG.getConstant(0, NVT), ISD::SETNE);
@@ -1459,7 +1459,7 @@
void DAGTypeLegalizer::ExpandIntRes_FP_TO_SINT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
DebugLoc dl = N->getDebugLoc();
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
SDValue Op = N->getOperand(0);
RTLIB::Libcall LC = RTLIB::getFPTOSINT(Op.getValueType(), VT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-sint conversion!");
@@ -1469,7 +1469,7 @@
void DAGTypeLegalizer::ExpandIntRes_FP_TO_UINT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
DebugLoc dl = N->getDebugLoc();
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
SDValue Op = N->getOperand(0);
RTLIB::Libcall LC = RTLIB::getFPTOUINT(Op.getValueType(), VT);
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unexpected fp-to-uint conversion!");
@@ -1485,8 +1485,8 @@
assert(ISD::isUNINDEXEDLoad(N) && "Indexed load during type legalization!");
- MVT VT = N->getValueType(0);
- MVT NVT = TLI.getTypeToTransformTo(VT);
+ EVT VT = N->getValueType(0);
+ EVT NVT = TLI.getTypeToTransformTo(VT);
SDValue Ch = N->getChain();
SDValue Ptr = N->getBasePtr();
ISD::LoadExtType ExtType = N->getExtensionType();
@@ -1498,7 +1498,7 @@
assert(NVT.isByteSized() && "Expanded type not byte sized!");
if (N->getMemoryVT().bitsLE(NVT)) {
- MVT EVT = N->getMemoryVT();
+ EVT EVT = N->getMemoryVT();
Lo = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
EVT, isVolatile, Alignment);
@@ -1527,7 +1527,7 @@
unsigned ExcessBits =
N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
- MVT NEVT = MVT::getIntegerVT(ExcessBits);
+ EVT NEVT = EVT::getIntegerVT(ExcessBits);
// Increment the pointer to the other half.
unsigned IncrementSize = NVT.getSizeInBits()/8;
@@ -1539,19 +1539,19 @@
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
Hi.getValue(1));
} else {
// Big-endian - high bits are at low addresses. Favor aligned loads at
// the cost of some bit-fiddling.
- MVT EVT = N->getMemoryVT();
+ EVT EVT = N->getMemoryVT();
unsigned EBytes = EVT.getStoreSizeInBits()/8;
unsigned IncrementSize = NVT.getSizeInBits()/8;
unsigned ExcessBits = (EBytes - IncrementSize)*8;
// Load both the high bits and maybe some of the low bits.
Hi = DAG.getExtLoad(ExtType, dl, NVT, Ch, Ptr, N->getSrcValue(), SVOffset,
- MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
+ EVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits),
isVolatile, Alignment);
// Increment the pointer to the other half.
@@ -1560,12 +1560,12 @@
// Load the rest of the low bits.
Lo = DAG.getExtLoad(ISD::ZEXTLOAD, dl, NVT, Ch, Ptr, N->getSrcValue(),
SVOffset+IncrementSize,
- MVT::getIntegerVT(ExcessBits),
+ EVT::getIntegerVT(ExcessBits),
isVolatile, MinAlign(Alignment, IncrementSize));
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
Hi.getValue(1));
if (ExcessBits < NVT.getSizeInBits()) {
@@ -1599,8 +1599,8 @@
void DAGTypeLegalizer::ExpandIntRes_MUL(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT VT = N->getValueType(0);
- MVT NVT = TLI.getTypeToTransformTo(VT);
+ EVT VT = N->getValueType(0);
+ EVT NVT = TLI.getTypeToTransformTo(VT);
DebugLoc dl = N->getDebugLoc();
bool HasMULHS = TLI.isOperationLegalOrCustom(ISD::MULHS, NVT);
@@ -1673,13 +1673,13 @@
// If nothing else, we can make a libcall.
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == MVT::i16)
+ if (VT == EVT::i16)
LC = RTLIB::MUL_I16;
- else if (VT == MVT::i32)
+ else if (VT == EVT::i32)
LC = RTLIB::MUL_I32;
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
LC = RTLIB::MUL_I64;
- else if (VT == MVT::i128)
+ else if (VT == EVT::i128)
LC = RTLIB::MUL_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported MUL!");
@@ -1689,17 +1689,17 @@
void DAGTypeLegalizer::ExpandIntRes_SDIV(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == MVT::i16)
+ if (VT == EVT::i16)
LC = RTLIB::SDIV_I16;
- else if (VT == MVT::i32)
+ else if (VT == EVT::i32)
LC = RTLIB::SDIV_I32;
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
LC = RTLIB::SDIV_I64;
- else if (VT == MVT::i128)
+ else if (VT == EVT::i128)
LC = RTLIB::SDIV_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SDIV!");
@@ -1709,7 +1709,7 @@
void DAGTypeLegalizer::ExpandIntRes_Shift(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
// If we can emit an efficient shift operation, do so now. Check to see if
@@ -1735,7 +1735,7 @@
// Next check to see if the target supports this SHL_PARTS operation or if it
// will custom expand it.
- MVT NVT = TLI.getTypeToTransformTo(VT);
+ EVT NVT = TLI.getTypeToTransformTo(VT);
TargetLowering::LegalizeAction Action = TLI.getOperationAction(PartsOpc, NVT);
if ((Action == TargetLowering::Legal && TLI.isTypeLegal(NVT)) ||
Action == TargetLowering::Custom) {
@@ -1744,7 +1744,7 @@
GetExpandedInteger(N->getOperand(0), LHSL, LHSH);
SDValue Ops[] = { LHSL, LHSH, N->getOperand(1) };
- MVT VT = LHSL.getValueType();
+ EVT VT = LHSL.getValueType();
Lo = DAG.getNode(PartsOpc, dl, DAG.getVTList(VT, VT), Ops, 3);
Hi = Lo.getValue(1);
return;
@@ -1755,34 +1755,34 @@
bool isSigned;
if (N->getOpcode() == ISD::SHL) {
isSigned = false; /*sign irrelevant*/
- if (VT == MVT::i16)
+ if (VT == EVT::i16)
LC = RTLIB::SHL_I16;
- else if (VT == MVT::i32)
+ else if (VT == EVT::i32)
LC = RTLIB::SHL_I32;
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
LC = RTLIB::SHL_I64;
- else if (VT == MVT::i128)
+ else if (VT == EVT::i128)
LC = RTLIB::SHL_I128;
} else if (N->getOpcode() == ISD::SRL) {
isSigned = false;
- if (VT == MVT::i16)
+ if (VT == EVT::i16)
LC = RTLIB::SRL_I16;
- else if (VT == MVT::i32)
+ else if (VT == EVT::i32)
LC = RTLIB::SRL_I32;
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
LC = RTLIB::SRL_I64;
- else if (VT == MVT::i128)
+ else if (VT == EVT::i128)
LC = RTLIB::SRL_I128;
} else {
assert(N->getOpcode() == ISD::SRA && "Unknown shift!");
isSigned = true;
- if (VT == MVT::i16)
+ if (VT == EVT::i16)
LC = RTLIB::SRA_I16;
- else if (VT == MVT::i32)
+ else if (VT == EVT::i32)
LC = RTLIB::SRA_I32;
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
LC = RTLIB::SRA_I64;
- else if (VT == MVT::i128)
+ else if (VT == EVT::i128)
LC = RTLIB::SRA_I128;
}
@@ -1798,7 +1798,7 @@
void DAGTypeLegalizer::ExpandIntRes_SIGN_EXTEND(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
DebugLoc dl = N->getDebugLoc();
SDValue Op = N->getOperand(0);
if (Op.getValueType().bitsLE(NVT)) {
@@ -1821,7 +1821,7 @@
unsigned ExcessBits =
Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
- DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
+ DAG.getValueType(EVT::getIntegerVT(ExcessBits)));
}
}
@@ -1829,7 +1829,7 @@
ExpandIntRes_SIGN_EXTEND_INREG(SDNode *N, SDValue &Lo, SDValue &Hi) {
DebugLoc dl = N->getDebugLoc();
GetExpandedInteger(N->getOperand(0), Lo, Hi);
- MVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
+ EVT EVT = cast<VTSDNode>(N->getOperand(1))->getVT();
if (EVT.bitsLE(Lo.getValueType())) {
// sext_inreg the low part if needed.
@@ -1847,23 +1847,23 @@
unsigned ExcessBits =
EVT.getSizeInBits() - Lo.getValueType().getSizeInBits();
Hi = DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Hi.getValueType(), Hi,
- DAG.getValueType(MVT::getIntegerVT(ExcessBits)));
+ DAG.getValueType(EVT::getIntegerVT(ExcessBits)));
}
}
void DAGTypeLegalizer::ExpandIntRes_SREM(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == MVT::i16)
+ if (VT == EVT::i16)
LC = RTLIB::SREM_I16;
- else if (VT == MVT::i32)
+ else if (VT == EVT::i32)
LC = RTLIB::SREM_I32;
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
LC = RTLIB::SREM_I64;
- else if (VT == MVT::i128)
+ else if (VT == EVT::i128)
LC = RTLIB::SREM_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported SREM!");
@@ -1873,7 +1873,7 @@
void DAGTypeLegalizer::ExpandIntRes_TRUNCATE(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
DebugLoc dl = N->getDebugLoc();
Lo = DAG.getNode(ISD::TRUNCATE, dl, NVT, N->getOperand(0));
Hi = DAG.getNode(ISD::SRL, dl,
@@ -1884,17 +1884,17 @@
void DAGTypeLegalizer::ExpandIntRes_UDIV(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == MVT::i16)
+ if (VT == EVT::i16)
LC = RTLIB::UDIV_I16;
- else if (VT == MVT::i32)
+ else if (VT == EVT::i32)
LC = RTLIB::UDIV_I32;
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
LC = RTLIB::UDIV_I64;
- else if (VT == MVT::i128)
+ else if (VT == EVT::i128)
LC = RTLIB::UDIV_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UDIV!");
@@ -1904,17 +1904,17 @@
void DAGTypeLegalizer::ExpandIntRes_UREM(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
RTLIB::Libcall LC = RTLIB::UNKNOWN_LIBCALL;
- if (VT == MVT::i16)
+ if (VT == EVT::i16)
LC = RTLIB::UREM_I16;
- else if (VT == MVT::i32)
+ else if (VT == EVT::i32)
LC = RTLIB::UREM_I32;
- else if (VT == MVT::i64)
+ else if (VT == EVT::i64)
LC = RTLIB::UREM_I64;
- else if (VT == MVT::i128)
+ else if (VT == EVT::i128)
LC = RTLIB::UREM_I128;
assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported UREM!");
@@ -1924,7 +1924,7 @@
void DAGTypeLegalizer::ExpandIntRes_ZERO_EXTEND(SDNode *N,
SDValue &Lo, SDValue &Hi) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
DebugLoc dl = N->getDebugLoc();
SDValue Op = N->getOperand(0);
if (Op.getValueType().bitsLE(NVT)) {
@@ -1943,7 +1943,7 @@
SplitInteger(Res, Lo, Hi);
unsigned ExcessBits =
Op.getValueType().getSizeInBits() - NVT.getSizeInBits();
- Hi = DAG.getZeroExtendInReg(Hi, dl, MVT::getIntegerVT(ExcessBits));
+ Hi = DAG.getZeroExtendInReg(Hi, dl, EVT::getIntegerVT(ExcessBits));
}
}
@@ -2016,7 +2016,7 @@
GetExpandedInteger(NewLHS, LHSLo, LHSHi);
GetExpandedInteger(NewRHS, RHSLo, RHSHi);
- MVT VT = NewLHS.getValueType();
+ EVT VT = NewLHS.getValueType();
if (CCCode == ISD::SETEQ || CCCode == ISD::SETNE) {
if (RHSLo == RHSHi) {
@@ -2174,7 +2174,7 @@
SDValue DAGTypeLegalizer::ExpandIntOp_SINT_TO_FP(SDNode *N) {
SDValue Op = N->getOperand(0);
- MVT DstVT = N->getValueType(0);
+ EVT DstVT = N->getValueType(0);
RTLIB::Libcall LC = RTLIB::getSINTTOFP(Op.getValueType(), DstVT);
assert(LC != RTLIB::UNKNOWN_LIBCALL &&
"Don't know how to expand this SINT_TO_FP!");
@@ -2188,8 +2188,8 @@
assert(ISD::isUNINDEXEDStore(N) && "Indexed store during type legalization!");
assert(OpNo == 1 && "Can only expand the stored value so far");
- MVT VT = N->getOperand(1).getValueType();
- MVT NVT = TLI.getTypeToTransformTo(VT);
+ EVT VT = N->getOperand(1).getValueType();
+ EVT NVT = TLI.getTypeToTransformTo(VT);
SDValue Ch = N->getChain();
SDValue Ptr = N->getBasePtr();
int SVOffset = N->getSrcValueOffset();
@@ -2213,7 +2213,7 @@
unsigned ExcessBits =
N->getMemoryVT().getSizeInBits() - NVT.getSizeInBits();
- MVT NEVT = MVT::getIntegerVT(ExcessBits);
+ EVT NEVT = EVT::getIntegerVT(ExcessBits);
// Increment the pointer to the other half.
unsigned IncrementSize = NVT.getSizeInBits()/8;
@@ -2222,17 +2222,17 @@
Hi = DAG.getTruncStore(Ch, dl, Hi, Ptr, N->getSrcValue(),
SVOffset+IncrementSize, NEVT,
isVolatile, MinAlign(Alignment, IncrementSize));
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
} else {
// Big-endian - high bits are at low addresses. Favor aligned stores at
// the cost of some bit-fiddling.
GetExpandedInteger(N->getValue(), Lo, Hi);
- MVT EVT = N->getMemoryVT();
- unsigned EBytes = EVT.getStoreSizeInBits()/8;
+ EVT ExtVT = N->getMemoryVT();
+ unsigned EBytes = ExtVT.getStoreSizeInBits()/8;
unsigned IncrementSize = NVT.getSizeInBits()/8;
unsigned ExcessBits = (EBytes - IncrementSize)*8;
- MVT HiVT = MVT::getIntegerVT(EVT.getSizeInBits() - ExcessBits);
+ EVT HiVT = EVT::getIntegerVT(ExtVT.getSizeInBits() - ExcessBits);
if (ExcessBits < NVT.getSizeInBits()) {
// Transfer high bits from the top of Lo to the bottom of Hi.
@@ -2255,9 +2255,9 @@
// Store the lowest ExcessBits bits in the second half.
Lo = DAG.getTruncStore(Ch, dl, Lo, Ptr, N->getSrcValue(),
SVOffset+IncrementSize,
- MVT::getIntegerVT(ExcessBits),
+ EVT::getIntegerVT(ExcessBits),
isVolatile, MinAlign(Alignment, IncrementSize));
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
}
}
@@ -2270,8 +2270,8 @@
SDValue DAGTypeLegalizer::ExpandIntOp_UINT_TO_FP(SDNode *N) {
SDValue Op = N->getOperand(0);
- MVT SrcVT = Op.getValueType();
- MVT DstVT = N->getValueType(0);
+ EVT SrcVT = Op.getValueType();
+ EVT DstVT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
if (TLI.getOperationAction(ISD::SINT_TO_FP, SrcVT) == TargetLowering::Custom){
@@ -2288,11 +2288,11 @@
const uint64_t F32TwoE128 = 0x7F800000ULL;
APInt FF(32, 0);
- if (SrcVT == MVT::i32)
+ if (SrcVT == EVT::i32)
FF = APInt(32, F32TwoE32);
- else if (SrcVT == MVT::i64)
+ else if (SrcVT == EVT::i64)
FF = APInt(32, F32TwoE64);
- else if (SrcVT == MVT::i128)
+ else if (SrcVT == EVT::i128)
FF = APInt(32, F32TwoE128);
else
assert(false && "Unsupported UINT_TO_FP!");
@@ -2323,7 +2323,7 @@
// Load the value out, extending it from f32 to the destination float type.
// FIXME: Avoid the extend by constructing the right constant pool?
SDValue Fudge = DAG.getExtLoad(ISD::EXTLOAD, dl, DstVT, DAG.getEntryNode(),
- FudgePtr, NULL, 0, MVT::f32,
+ FudgePtr, NULL, 0, EVT::f32,
false, Alignment);
return DAG.getNode(ISD::FADD, dl, DstVT, SignedConv, Fudge);
}
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
index 4e4c69a..db08823 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp
@@ -211,7 +211,7 @@
// Scan the values produced by the node, checking to see if any result
// types are illegal.
for (unsigned i = 0, NumResults = N->getNumValues(); i < NumResults; ++i) {
- MVT ResultVT = N->getValueType(i);
+ EVT ResultVT = N->getValueType(i);
switch (getTypeAction(ResultVT)) {
default:
assert(false && "Unknown action!");
@@ -264,7 +264,7 @@
if (IgnoreNodeResults(N->getOperand(i).getNode()))
continue;
- MVT OpVT = N->getOperand(i).getValueType();
+ EVT OpVT = N->getOperand(i).getValueType();
switch (getTypeAction(OpVT)) {
default:
assert(false && "Unknown action!");
@@ -861,7 +861,7 @@
SDValue DAGTypeLegalizer::BitConvertToInteger(SDValue Op) {
unsigned BitWidth = Op.getValueType().getSizeInBits();
return DAG.getNode(ISD::BIT_CONVERT, Op.getDebugLoc(),
- MVT::getIntegerVT(BitWidth), Op);
+ EVT::getIntegerVT(BitWidth), Op);
}
/// BitConvertVectorToIntegerVector - Convert to a vector of integers of the
@@ -869,14 +869,14 @@
SDValue DAGTypeLegalizer::BitConvertVectorToIntegerVector(SDValue Op) {
assert(Op.getValueType().isVector() && "Only applies to vectors!");
unsigned EltWidth = Op.getValueType().getVectorElementType().getSizeInBits();
- MVT EltNVT = MVT::getIntegerVT(EltWidth);
+ EVT EltNVT = EVT::getIntegerVT(EltWidth);
unsigned NumElts = Op.getValueType().getVectorNumElements();
return DAG.getNode(ISD::BIT_CONVERT, Op.getDebugLoc(),
- MVT::getVectorVT(EltNVT, NumElts), Op);
+ EVT::getVectorVT(EltNVT, NumElts), Op);
}
SDValue DAGTypeLegalizer::CreateStackStoreLoad(SDValue Op,
- MVT DestVT) {
+ EVT DestVT) {
DebugLoc dl = Op.getDebugLoc();
// Create the stack frame object. Make sure it is aligned for both
// the source and destination types.
@@ -895,7 +895,7 @@
/// The last parameter being TRUE means we are dealing with a
/// node with illegal result types. The second parameter denotes the type of
/// illegal ResNo in that case.
-bool DAGTypeLegalizer::CustomLowerNode(SDNode *N, MVT VT, bool LegalizeResult) {
+bool DAGTypeLegalizer::CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult) {
// See if the target wants to custom lower this node.
if (TLI.getOperationAction(N->getOpcode(), VT) != TargetLowering::Custom)
return false;
@@ -920,14 +920,14 @@
/// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a type
/// which is split into two not necessarily identical pieces.
-void DAGTypeLegalizer::GetSplitDestVTs(MVT InVT, MVT &LoVT, MVT &HiVT) {
+void DAGTypeLegalizer::GetSplitDestVTs(EVT InVT, EVT &LoVT, EVT &HiVT) {
// Currently all types are split in half.
if (!InVT.isVector()) {
LoVT = HiVT = TLI.getTypeToTransformTo(InVT);
} else {
unsigned NumElements = InVT.getVectorNumElements();
assert(!(NumElements & 1) && "Splitting vector, but not in half!");
- LoVT = HiVT = MVT::getVectorVT(InVT.getVectorElementType(), NumElements/2);
+ LoVT = HiVT = EVT::getVectorVT(InVT.getVectorElementType(), NumElements/2);
}
}
@@ -936,14 +936,14 @@
void DAGTypeLegalizer::GetPairElements(SDValue Pair,
SDValue &Lo, SDValue &Hi) {
DebugLoc dl = Pair.getDebugLoc();
- MVT NVT = TLI.getTypeToTransformTo(Pair.getValueType());
+ EVT NVT = TLI.getTypeToTransformTo(Pair.getValueType());
Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Pair,
DAG.getIntPtrConstant(0));
Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, NVT, Pair,
DAG.getIntPtrConstant(1));
}
-SDValue DAGTypeLegalizer::GetVectorElementPointer(SDValue VecPtr, MVT EltVT,
+SDValue DAGTypeLegalizer::GetVectorElementPointer(SDValue VecPtr, EVT EltVT,
SDValue Index) {
DebugLoc dl = Index.getDebugLoc();
// Make sure the index type is big enough to compute in.
@@ -965,9 +965,9 @@
// Arbitrarily use dlHi for result DebugLoc
DebugLoc dlHi = Hi.getDebugLoc();
DebugLoc dlLo = Lo.getDebugLoc();
- MVT LVT = Lo.getValueType();
- MVT HVT = Hi.getValueType();
- MVT NVT = MVT::getIntegerVT(LVT.getSizeInBits() + HVT.getSizeInBits());
+ EVT LVT = Lo.getValueType();
+ EVT HVT = Hi.getValueType();
+ EVT NVT = EVT::getIntegerVT(LVT.getSizeInBits() + HVT.getSizeInBits());
Lo = DAG.getNode(ISD::ZERO_EXTEND, dlLo, NVT, Lo);
Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi);
@@ -999,7 +999,7 @@
/// MakeLibCall - Generate a libcall taking the given operands as arguments and
/// returning a result of type RetVT.
-SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
+SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, EVT RetVT,
const SDValue *Ops, unsigned NumOps,
bool isSigned, DebugLoc dl) {
TargetLowering::ArgListTy Args;
@@ -1008,7 +1008,7 @@
TargetLowering::ArgListEntry Entry;
for (unsigned i = 0; i != NumOps; ++i) {
Entry.Node = Ops[i];
- Entry.Ty = Entry.Node.getValueType().getTypeForMVT();
+ Entry.Ty = Entry.Node.getValueType().getTypeForEVT();
Entry.isSExt = isSigned;
Entry.isZExt = !isSigned;
Args.push_back(Entry);
@@ -1016,7 +1016,7 @@
SDValue Callee = DAG.getExternalSymbol(TLI.getLibcallName(LC),
TLI.getPointerTy());
- const Type *RetTy = RetVT.getTypeForMVT();
+ const Type *RetTy = RetVT.getTypeForEVT();
std::pair<SDValue,SDValue> CallInfo =
TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
false, 0, CallingConv::C, false,
@@ -1028,7 +1028,7 @@
/// PromoteTargetBoolean - Promote the given target boolean to a target boolean
/// of the given type. A target boolean is an integer value, not necessarily of
/// type i1, the bits of which conform to getBooleanContents.
-SDValue DAGTypeLegalizer::PromoteTargetBoolean(SDValue Bool, MVT VT) {
+SDValue DAGTypeLegalizer::PromoteTargetBoolean(SDValue Bool, EVT VT) {
DebugLoc dl = Bool.getDebugLoc();
ISD::NodeType ExtendCode;
switch (TLI.getBooleanContents()) {
@@ -1054,7 +1054,7 @@
/// SplitInteger - Return the lower LoVT bits of Op in Lo and the upper HiVT
/// bits in Hi.
void DAGTypeLegalizer::SplitInteger(SDValue Op,
- MVT LoVT, MVT HiVT,
+ EVT LoVT, EVT HiVT,
SDValue &Lo, SDValue &Hi) {
DebugLoc dl = Op.getDebugLoc();
assert(LoVT.getSizeInBits() + HiVT.getSizeInBits() ==
@@ -1069,7 +1069,7 @@
/// type half the size of Op's.
void DAGTypeLegalizer::SplitInteger(SDValue Op,
SDValue &Lo, SDValue &Hi) {
- MVT HalfVT = MVT::getIntegerVT(Op.getValueType().getSizeInBits()/2);
+ EVT HalfVT = EVT::getIntegerVT(Op.getValueType().getSizeInBits()/2);
SplitInteger(Op, HalfVT, HalfVT, Lo, Hi);
}
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/lib/CodeGen/SelectionDAG/LegalizeTypes.h
index 0dd82c4..8801cee 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypes.h
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypes.h
@@ -74,7 +74,7 @@
TargetLowering::ValueTypeActionImpl ValueTypeActions;
/// getTypeAction - Return how we should legalize values of this type.
- LegalizeAction getTypeAction(MVT VT) const {
+ LegalizeAction getTypeAction(EVT VT) const {
switch (ValueTypeActions.getTypeAction(VT)) {
default:
assert(false && "Unknown legalize action!");
@@ -109,7 +109,7 @@
}
/// isTypeLegal - Return true if this type is legal on this target.
- bool isTypeLegal(MVT VT) const {
+ bool isTypeLegal(EVT VT) const {
return ValueTypeActions.getTypeAction(VT) == TargetLowering::Legal;
}
@@ -159,7 +159,7 @@
explicit DAGTypeLegalizer(SelectionDAG &dag)
: TLI(dag.getTargetLoweringInfo()), DAG(dag),
ValueTypeActions(TLI.getValueTypeActions()) {
- assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
+ assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE &&
"Too many value types for ValueTypeActions to hold!");
}
@@ -185,19 +185,19 @@
// Common routines.
SDValue BitConvertToInteger(SDValue Op);
SDValue BitConvertVectorToIntegerVector(SDValue Op);
- SDValue CreateStackStoreLoad(SDValue Op, MVT DestVT);
- bool CustomLowerNode(SDNode *N, MVT VT, bool LegalizeResult);
- SDValue GetVectorElementPointer(SDValue VecPtr, MVT EltVT, SDValue Index);
+ SDValue CreateStackStoreLoad(SDValue Op, EVT DestVT);
+ bool CustomLowerNode(SDNode *N, EVT VT, bool LegalizeResult);
+ SDValue GetVectorElementPointer(SDValue VecPtr, EVT EltVT, SDValue Index);
SDValue JoinIntegers(SDValue Lo, SDValue Hi);
SDValue LibCallify(RTLIB::Libcall LC, SDNode *N, bool isSigned);
- SDValue MakeLibCall(RTLIB::Libcall LC, MVT RetVT,
+ SDValue MakeLibCall(RTLIB::Libcall LC, EVT RetVT,
const SDValue *Ops, unsigned NumOps, bool isSigned,
DebugLoc dl);
- SDValue PromoteTargetBoolean(SDValue Bool, MVT VT);
+ SDValue PromoteTargetBoolean(SDValue Bool, EVT VT);
void ReplaceValueWith(SDValue From, SDValue To);
void ReplaceValueWithHelper(SDValue From, SDValue To);
void SplitInteger(SDValue Op, SDValue &Lo, SDValue &Hi);
- void SplitInteger(SDValue Op, MVT LoVT, MVT HiVT,
+ void SplitInteger(SDValue Op, EVT LoVT, EVT HiVT,
SDValue &Lo, SDValue &Hi);
//===--------------------------------------------------------------------===//
@@ -224,7 +224,7 @@
/// SExtPromotedInteger - Get a promoted operand and sign extend it to the
/// final size.
SDValue SExtPromotedInteger(SDValue Op) {
- MVT OldVT = Op.getValueType();
+ EVT OldVT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
Op = GetPromotedInteger(Op);
return DAG.getNode(ISD::SIGN_EXTEND_INREG, dl, Op.getValueType(), Op,
@@ -234,7 +234,7 @@
/// ZExtPromotedInteger - Get a promoted operand and zero extend it to the
/// final size.
SDValue ZExtPromotedInteger(SDValue Op) {
- MVT OldVT = Op.getValueType();
+ EVT OldVT = Op.getValueType();
DebugLoc dl = Op.getDebugLoc();
Op = GetPromotedInteger(Op);
return DAG.getZeroExtendInReg(Op, dl, OldVT);
@@ -641,7 +641,7 @@
SDValue BasePtr, const Value *SV,
int SVOffset, unsigned Alignment,
bool isVolatile, unsigned LdWidth,
- MVT ResType, DebugLoc dl);
+ EVT ResType, DebugLoc dl);
/// Helper genWidenVectorStores - Helper function to generate a set of
/// stores to store a widen vector into non widen memory
@@ -664,7 +664,7 @@
/// Modifies a vector input (widen or narrows) to a vector of NVT. The
/// input vector must have the same element type as NVT.
- SDValue ModifyToType(SDValue InOp, MVT WidenVT);
+ SDValue ModifyToType(SDValue InOp, EVT WidenVT);
//===--------------------------------------------------------------------===//
@@ -686,7 +686,7 @@
/// GetSplitDestVTs - Compute the VTs needed for the low/hi parts of a type
/// which is split (or expanded) into two not necessarily identical pieces.
- void GetSplitDestVTs(MVT InVT, MVT &LoVT, MVT &HiVT);
+ void GetSplitDestVTs(EVT InVT, EVT &LoVT, EVT &HiVT);
/// GetPairElements - Use ISD::EXTRACT_ELEMENT nodes to extract the low and
/// high parts of the given value.
diff --git a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
index 0803426..8533866 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp
@@ -34,10 +34,10 @@
void DAGTypeLegalizer::ExpandRes_BIT_CONVERT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- MVT OutVT = N->getValueType(0);
- MVT NOutVT = TLI.getTypeToTransformTo(OutVT);
+ EVT OutVT = N->getValueType(0);
+ EVT NOutVT = TLI.getTypeToTransformTo(OutVT);
SDValue InOp = N->getOperand(0);
- MVT InVT = InOp.getValueType();
+ EVT InVT = InOp.getValueType();
DebugLoc dl = N->getDebugLoc();
// Handle some special cases efficiently.
@@ -76,7 +76,7 @@
case WidenVector: {
assert(!(InVT.getVectorNumElements() & 1) && "Unsupported BIT_CONVERT");
InOp = GetWidenedVector(InOp);
- MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
+ EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
InVT.getVectorNumElements()/2);
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
DAG.getIntPtrConstant(0));
@@ -93,7 +93,7 @@
if (InVT.isVector() && OutVT.isInteger()) {
// Handle cases like i64 = BIT_CONVERT v1i64 on x86, where the operand
// is legal but the result is not.
- MVT NVT = MVT::getVectorVT(NOutVT, 2);
+ EVT NVT = EVT::getVectorVT(NOutVT, 2);
if (isTypeLegal(NVT)) {
SDValue CastInOp = DAG.getNode(ISD::BIT_CONVERT, dl, NVT, InOp);
@@ -115,7 +115,7 @@
// Create the stack frame object. Make sure it is aligned for both
// the source and expanded destination types.
unsigned Alignment =
- TLI.getTargetData()->getPrefTypeAlignment(NOutVT.getTypeForMVT());
+ TLI.getTargetData()->getPrefTypeAlignment(NOutVT.getTypeForEVT());
SDValue StackPtr = DAG.CreateStackTemporary(InVT, Alignment);
int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
const Value *SV = PseudoSourceValue::getFixedStack(SPFI);
@@ -167,11 +167,11 @@
// Convert to a vector of the expanded element type, for example
// <3 x i64> -> <6 x i32>.
- MVT OldVT = N->getValueType(0);
- MVT NewVT = TLI.getTypeToTransformTo(OldVT);
+ EVT OldVT = N->getValueType(0);
+ EVT NewVT = TLI.getTypeToTransformTo(OldVT);
SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::getVectorVT(NewVT, 2*OldElts),
+ EVT::getVectorVT(NewVT, 2*OldElts),
OldVec);
// Extract the elements at 2 * Idx and 2 * Idx + 1 from the new vector.
@@ -198,7 +198,7 @@
DebugLoc dl = N->getDebugLoc();
LoadSDNode *LD = cast<LoadSDNode>(N);
- MVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(LD->getValueType(0));
SDValue Chain = LD->getChain();
SDValue Ptr = LD->getBasePtr();
int SVOffset = LD->getSrcValueOffset();
@@ -220,7 +220,7 @@
// Build a factor node to remember that this load is independent of the
// other one.
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Handle endianness of the load.
@@ -233,7 +233,7 @@
}
void DAGTypeLegalizer::ExpandRes_VAARG(SDNode *N, SDValue &Lo, SDValue &Hi) {
- MVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT NVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue Chain = N->getOperand(0);
SDValue Ptr = N->getOperand(1);
DebugLoc dl = N->getDebugLoc();
@@ -263,8 +263,8 @@
// instead, but only if the new vector type is legal (otherwise there
// is no point, and it might create expansion loops). For example, on
// x86 this turns v1i64 = BIT_CONVERT i64 into v1i64 = BIT_CONVERT v2i32.
- MVT OVT = N->getOperand(0).getValueType();
- MVT NVT = MVT::getVectorVT(TLI.getTypeToTransformTo(OVT), 2);
+ EVT OVT = N->getOperand(0).getValueType();
+ EVT NVT = EVT::getVectorVT(TLI.getTypeToTransformTo(OVT), 2);
if (isTypeLegal(NVT)) {
SDValue Parts[2];
@@ -284,10 +284,10 @@
SDValue DAGTypeLegalizer::ExpandOp_BUILD_VECTOR(SDNode *N) {
// The vector type is legal but the element type needs expansion.
- MVT VecVT = N->getValueType(0);
+ EVT VecVT = N->getValueType(0);
unsigned NumElts = VecVT.getVectorNumElements();
- MVT OldVT = N->getOperand(0).getValueType();
- MVT NewVT = TLI.getTypeToTransformTo(OldVT);
+ EVT OldVT = N->getOperand(0).getValueType();
+ EVT NewVT = TLI.getTypeToTransformTo(OldVT);
DebugLoc dl = N->getDebugLoc();
assert(OldVT == VecVT.getVectorElementType() &&
@@ -308,7 +308,7 @@
}
SDValue NewVec = DAG.getNode(ISD::BUILD_VECTOR, dl,
- MVT::getVectorVT(NewVT, NewElts.size()),
+ EVT::getVectorVT(NewVT, NewElts.size()),
&NewElts[0], NewElts.size());
// Convert the new vector to the old vector type.
@@ -323,20 +323,20 @@
SDValue DAGTypeLegalizer::ExpandOp_INSERT_VECTOR_ELT(SDNode *N) {
// The vector type is legal but the element type needs expansion.
- MVT VecVT = N->getValueType(0);
+ EVT VecVT = N->getValueType(0);
unsigned NumElts = VecVT.getVectorNumElements();
DebugLoc dl = N->getDebugLoc();
SDValue Val = N->getOperand(1);
- MVT OldEVT = Val.getValueType();
- MVT NewEVT = TLI.getTypeToTransformTo(OldEVT);
+ EVT OldEVT = Val.getValueType();
+ EVT NewEVT = TLI.getTypeToTransformTo(OldEVT);
assert(OldEVT == VecVT.getVectorElementType() &&
"Inserted element type doesn't match vector element type!");
// Bitconvert to a vector of twice the length with elements of the expanded
// type, insert the expanded vector elements, and then convert back.
- MVT NewVecVT = MVT::getVectorVT(NewEVT, NumElts*2);
+ EVT NewVecVT = EVT::getVectorVT(NewEVT, NumElts*2);
SDValue NewVec = DAG.getNode(ISD::BIT_CONVERT, dl,
NewVecVT, N->getOperand(0));
@@ -358,7 +358,7 @@
SDValue DAGTypeLegalizer::ExpandOp_SCALAR_TO_VECTOR(SDNode *N) {
DebugLoc dl = N->getDebugLoc();
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
assert(VT.getVectorElementType() == N->getOperand(0).getValueType() &&
"SCALAR_TO_VECTOR operand type doesn't match vector element type!");
unsigned NumElts = VT.getVectorNumElements();
@@ -376,7 +376,7 @@
DebugLoc dl = N->getDebugLoc();
StoreSDNode *St = cast<StoreSDNode>(N);
- MVT NVT = TLI.getTypeToTransformTo(St->getValue().getValueType());
+ EVT NVT = TLI.getTypeToTransformTo(St->getValue().getValueType());
SDValue Chain = St->getChain();
SDValue Ptr = St->getBasePtr();
int SVOffset = St->getSrcValueOffset();
@@ -402,7 +402,7 @@
SVOffset + IncrementSize,
isVolatile, MinAlign(Alignment, IncrementSize));
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
}
@@ -462,7 +462,7 @@
}
void DAGTypeLegalizer::SplitRes_UNDEF(SDNode *N, SDValue &Lo, SDValue &Hi) {
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc dl = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
Lo = DAG.getUNDEF(LoVT);
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
index 58a0927..aa647fd 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
@@ -129,7 +129,7 @@
if (!HasVectorValue)
return TranslateLegalizeResults(Op, Result);
- MVT QueryType;
+ EVT QueryType;
switch (Op.getOpcode()) {
default:
return TranslateLegalizeResults(Op, Result);
@@ -231,10 +231,10 @@
// Vector "promotion" is basically just bitcasting and doing the operation
// in a different type. For example, x86 promotes ISD::AND on v2i32 to
// v1i64.
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
assert(Op.getNode()->getNumValues() == 1 &&
"Can't promote a vector with multiple results!");
- MVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
+ EVT NVT = TLI.getTypeToPromoteTo(Op.getOpcode(), VT);
DebugLoc dl = Op.getDebugLoc();
SmallVector<SDValue, 4> Operands(Op.getNumOperands());
@@ -260,11 +260,11 @@
}
SDValue VectorLegalizer::UnrollVSETCC(SDValue Op) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
unsigned NumElems = VT.getVectorNumElements();
- MVT EltVT = VT.getVectorElementType();
+ EVT EltVT = VT.getVectorElementType();
SDValue LHS = Op.getOperand(0), RHS = Op.getOperand(1), CC = Op.getOperand(2);
- MVT TmpEltVT = LHS.getValueType().getVectorElementType();
+ EVT TmpEltVT = LHS.getValueType().getVectorElementType();
DebugLoc dl = Op.getDebugLoc();
SmallVector<SDValue, 8> Ops(NumElems);
for (unsigned i = 0; i < NumElems; ++i) {
@@ -287,11 +287,11 @@
/// the operation be expanded. "Unroll" the vector, splitting out the scalars
/// and operating on each element individually.
SDValue VectorLegalizer::UnrollVectorOp(SDValue Op) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
assert(Op.getNode()->getNumValues() == 1 &&
"Can't unroll a vector with multiple results!");
unsigned NE = VT.getVectorNumElements();
- MVT EltVT = VT.getVectorElementType();
+ EVT EltVT = VT.getVectorElementType();
DebugLoc dl = Op.getDebugLoc();
SmallVector<SDValue, 8> Scalars;
@@ -299,14 +299,14 @@
for (unsigned i = 0; i != NE; ++i) {
for (unsigned j = 0; j != Op.getNumOperands(); ++j) {
SDValue Operand = Op.getOperand(j);
- MVT OperandVT = Operand.getValueType();
+ EVT OperandVT = Operand.getValueType();
if (OperandVT.isVector()) {
// A vector operand; extract a single element.
- MVT OperandEltVT = OperandVT.getVectorElementType();
+ EVT OperandEltVT = OperandVT.getVectorElementType();
Operands[j] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
OperandEltVT,
Operand,
- DAG.getConstant(i, MVT::i32));
+ DAG.getConstant(i, EVT::i32));
} else {
// A scalar operand; just use it as is.
Operands[j] = Operand;
diff --git a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
index 9ec0846..a10d167 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp
@@ -118,13 +118,13 @@
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_BIT_CONVERT(SDNode *N) {
- MVT NewVT = N->getValueType(0).getVectorElementType();
+ EVT NewVT = N->getValueType(0).getVectorElementType();
return DAG.getNode(ISD::BIT_CONVERT, N->getDebugLoc(),
NewVT, N->getOperand(0));
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_CONVERT_RNDSAT(SDNode *N) {
- MVT NewVT = N->getValueType(0).getVectorElementType();
+ EVT NewVT = N->getValueType(0).getVectorElementType();
SDValue Op0 = GetScalarizedVector(N->getOperand(0));
return DAG.getConvertRndSat(NewVT, N->getDebugLoc(),
Op0, DAG.getValueType(NewVT),
@@ -150,7 +150,7 @@
// The value to insert may have a wider type than the vector element type,
// so be sure to truncate it to the element type if necessary.
SDValue Op = N->getOperand(1);
- MVT EltVT = N->getValueType(0).getVectorElementType();
+ EVT EltVT = N->getValueType(0).getVectorElementType();
if (Op.getValueType() != EltVT)
// FIXME: Can this happen for floating point types?
Op = DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, Op);
@@ -177,7 +177,7 @@
SDValue DAGTypeLegalizer::ScalarizeVecRes_UnaryOp(SDNode *N) {
// Get the dest type - it doesn't always match the input type, e.g. int_to_fp.
- MVT DestVT = N->getValueType(0).getVectorElementType();
+ EVT DestVT = N->getValueType(0).getVectorElementType();
SDValue Op = GetScalarizedVector(N->getOperand(0));
return DAG.getNode(N->getOpcode(), N->getDebugLoc(), DestVT, Op);
}
@@ -185,7 +185,7 @@
SDValue DAGTypeLegalizer::ScalarizeVecRes_SCALAR_TO_VECTOR(SDNode *N) {
// If the operand is wider than the vector element type then it is implicitly
// truncated. Make that explicit here.
- MVT EltVT = N->getValueType(0).getVectorElementType();
+ EVT EltVT = N->getValueType(0).getVectorElementType();
SDValue InOp = N->getOperand(0);
if (InOp.getValueType() != EltVT)
return DAG.getNode(ISD::TRUNCATE, N->getDebugLoc(), EltVT, InOp);
@@ -213,7 +213,7 @@
DebugLoc DL = N->getDebugLoc();
// Turn it into a scalar SETCC.
- return DAG.getNode(ISD::SETCC, DL, MVT::i1, LHS, RHS, N->getOperand(2));
+ return DAG.getNode(ISD::SETCC, DL, EVT::i1, LHS, RHS, N->getOperand(2));
}
SDValue DAGTypeLegalizer::ScalarizeVecRes_UNDEF(SDNode *N) {
@@ -232,8 +232,8 @@
SDValue DAGTypeLegalizer::ScalarizeVecRes_VSETCC(SDNode *N) {
SDValue LHS = GetScalarizedVector(N->getOperand(0));
SDValue RHS = GetScalarizedVector(N->getOperand(1));
- MVT NVT = N->getValueType(0).getVectorElementType();
- MVT SVT = TLI.getSetCCResultType(LHS.getValueType());
+ EVT NVT = N->getValueType(0).getVectorElementType();
+ EVT SVT = TLI.getSetCCResultType(LHS.getValueType());
DebugLoc DL = N->getDebugLoc();
// Turn it into a scalar SETCC.
@@ -247,16 +247,16 @@
if (TLI.getBooleanContents() !=
TargetLowering::ZeroOrNegativeOneBooleanContent)
Res = DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, SVT, Res,
- DAG.getValueType(MVT::i1));
+ DAG.getValueType(EVT::i1));
// Truncate to the final type.
return DAG.getNode(ISD::TRUNCATE, DL, NVT, Res);
}
// The SETCC result type is smaller than the vector element type.
- // If the SetCC result is not sign-extended, chop it down to MVT::i1.
+ // If the SetCC result is not sign-extended, chop it down to EVT::i1.
if (TLI.getBooleanContents() !=
TargetLowering::ZeroOrNegativeOneBooleanContent)
- Res = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Res);
+ Res = DAG.getNode(ISD::TRUNCATE, DL, EVT::i1, Res);
// Sign extend to the final type.
return DAG.getNode(ISD::SIGN_EXTEND, DL, NVT, Res);
}
@@ -472,12 +472,12 @@
SDValue &Hi) {
// We know the result is a vector. The input may be either a vector or a
// scalar value.
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
DebugLoc dl = N->getDebugLoc();
SDValue InOp = N->getOperand(0);
- MVT InVT = InOp.getValueType();
+ EVT InVT = InOp.getValueType();
// Handle some special cases efficiently.
switch (getTypeAction(InVT)) {
@@ -512,8 +512,8 @@
}
// In the general case, convert the input to an integer and split it by hand.
- MVT LoIntVT = MVT::getIntegerVT(LoVT.getSizeInBits());
- MVT HiIntVT = MVT::getIntegerVT(HiVT.getSizeInBits());
+ EVT LoIntVT = EVT::getIntegerVT(LoVT.getSizeInBits());
+ EVT HiIntVT = EVT::getIntegerVT(HiVT.getSizeInBits());
if (TLI.isBigEndian())
std::swap(LoIntVT, HiIntVT);
@@ -527,7 +527,7 @@
void DAGTypeLegalizer::SplitVecRes_BUILD_VECTOR(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc dl = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
unsigned LoNumElts = LoVT.getVectorNumElements();
@@ -549,7 +549,7 @@
return;
}
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
SmallVector<SDValue, 8> LoOps(N->op_begin(), N->op_begin()+NumSubvectors);
@@ -561,7 +561,7 @@
void DAGTypeLegalizer::SplitVecRes_CONVERT_RNDSAT(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc dl = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
@@ -574,11 +574,11 @@
// Split the input.
SDValue VLo, VHi;
- MVT InVT = N->getOperand(0).getValueType();
+ EVT InVT = N->getOperand(0).getValueType();
switch (getTypeAction(InVT)) {
default: llvm_unreachable("Unexpected type action!");
case Legal: {
- MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
+ EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
DAG.getIntPtrConstant(0));
@@ -594,7 +594,7 @@
// the two types must have different lengths. Use the widened result
// and extract from it to do the split.
SDValue InOp = GetWidenedVector(N->getOperand(0));
- MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
+ EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
VLo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
DAG.getIntPtrConstant(0));
@@ -617,10 +617,10 @@
SDValue &Hi) {
SDValue Vec = N->getOperand(0);
SDValue Idx = N->getOperand(1);
- MVT IdxVT = Idx.getValueType();
+ EVT IdxVT = Idx.getValueType();
DebugLoc dl = N->getDebugLoc();
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, LoVT, Vec, Idx);
@@ -658,8 +658,8 @@
}
// Spill the vector to the stack.
- MVT VecVT = Vec.getValueType();
- MVT EltVT = VecVT.getVectorElementType();
+ EVT VecVT = Vec.getValueType();
+ EVT EltVT = VecVT.getVectorElementType();
SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
SDValue Store = DAG.getStore(DAG.getEntryNode(), dl, Vec, StackPtr, NULL, 0);
@@ -667,7 +667,7 @@
// so use a truncating store.
SDValue EltPtr = GetVectorElementPointer(StackPtr, EltVT, Idx);
unsigned Alignment =
- TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForMVT());
+ TLI.getTargetData()->getPrefTypeAlignment(VecVT.getTypeForEVT());
Store = DAG.getTruncStore(Store, dl, Elt, EltPtr, NULL, 0, EltVT);
// Load the Lo part from the stack slot.
@@ -685,7 +685,7 @@
void DAGTypeLegalizer::SplitVecRes_SCALAR_TO_VECTOR(SDNode *N, SDValue &Lo,
SDValue &Hi) {
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc dl = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
Lo = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, LoVT, N->getOperand(0));
@@ -695,7 +695,7 @@
void DAGTypeLegalizer::SplitVecRes_LOAD(LoadSDNode *LD, SDValue &Lo,
SDValue &Hi) {
assert(ISD::isUNINDEXEDLoad(LD) && "Indexed load during type legalization!");
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc dl = LD->getDebugLoc();
GetSplitDestVTs(LD->getValueType(0), LoVT, HiVT);
@@ -705,11 +705,11 @@
SDValue Offset = DAG.getUNDEF(Ptr.getValueType());
const Value *SV = LD->getSrcValue();
int SVOffset = LD->getSrcValueOffset();
- MVT MemoryVT = LD->getMemoryVT();
+ EVT MemoryVT = LD->getMemoryVT();
unsigned Alignment = LD->getAlignment();
bool isVolatile = LD->isVolatile();
- MVT LoMemVT, HiMemVT;
+ EVT LoMemVT, HiMemVT;
GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
Lo = DAG.getLoad(ISD::UNINDEXED, dl, ExtType, LoVT, Ch, Ptr, Offset,
@@ -725,7 +725,7 @@
// Build a factor node to remember that this load is independent of the
// other one.
- Ch = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo.getValue(1),
+ Ch = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo.getValue(1),
Hi.getValue(1));
// Legalized the chain result - switch anything that used the old chain to
@@ -734,14 +734,14 @@
}
void DAGTypeLegalizer::SplitVecRes_SETCC(SDNode *N, SDValue &Lo, SDValue &Hi) {
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc DL = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
// Split the input.
- MVT InVT = N->getOperand(0).getValueType();
+ EVT InVT = N->getOperand(0).getValueType();
SDValue LL, LH, RL, RH;
- MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
+ EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
LL = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DL, InNVT, N->getOperand(0),
DAG.getIntPtrConstant(0));
@@ -760,16 +760,16 @@
void DAGTypeLegalizer::SplitVecRes_UnaryOp(SDNode *N, SDValue &Lo,
SDValue &Hi) {
// Get the dest types - they may not match the input types, e.g. int_to_fp.
- MVT LoVT, HiVT;
+ EVT LoVT, HiVT;
DebugLoc dl = N->getDebugLoc();
GetSplitDestVTs(N->getValueType(0), LoVT, HiVT);
// Split the input.
- MVT InVT = N->getOperand(0).getValueType();
+ EVT InVT = N->getOperand(0).getValueType();
switch (getTypeAction(InVT)) {
default: llvm_unreachable("Unexpected type action!");
case Legal: {
- MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
+ EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, N->getOperand(0),
DAG.getIntPtrConstant(0));
@@ -785,7 +785,7 @@
// the two types must have different lengths. Use the widened result
// and extract from it to do the split.
SDValue InOp = GetWidenedVector(N->getOperand(0));
- MVT InNVT = MVT::getVectorVT(InVT.getVectorElementType(),
+ EVT InNVT = EVT::getVectorVT(InVT.getVectorElementType(),
LoVT.getVectorNumElements());
Lo = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, InNVT, InOp,
DAG.getIntPtrConstant(0));
@@ -806,7 +806,7 @@
DebugLoc dl = N->getDebugLoc();
GetSplitVector(N->getOperand(0), Inputs[0], Inputs[1]);
GetSplitVector(N->getOperand(1), Inputs[2], Inputs[3]);
- MVT NewVT = Inputs[0].getValueType();
+ EVT NewVT = Inputs[0].getValueType();
unsigned NewElts = NewVT.getVectorNumElements();
// If Lo or Hi uses elements from at most two of the four input vectors, then
@@ -864,7 +864,7 @@
}
if (useBuildVector) {
- MVT EltVT = NewVT.getVectorElementType();
+ EVT EltVT = NewVT.getVectorElementType();
SmallVector<SDValue, 16> SVOps;
// Extract the input elements by hand.
@@ -969,13 +969,13 @@
SDValue DAGTypeLegalizer::SplitVecOp_UnaryOp(SDNode *N) {
// The result has a legal vector type, but the input needs splitting.
- MVT ResVT = N->getValueType(0);
+ EVT ResVT = N->getValueType(0);
SDValue Lo, Hi;
DebugLoc dl = N->getDebugLoc();
GetSplitVector(N->getOperand(0), Lo, Hi);
- MVT InVT = Lo.getValueType();
+ EVT InVT = Lo.getValueType();
- MVT OutVT = MVT::getVectorVT(ResVT.getVectorElementType(),
+ EVT OutVT = EVT::getVectorVT(ResVT.getVectorElementType(),
InVT.getVectorNumElements());
Lo = DAG.getNode(N->getOpcode(), dl, OutVT, Lo);
@@ -1003,7 +1003,7 @@
SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_SUBVECTOR(SDNode *N) {
// We know that the extracted result type is legal. For now, assume the index
// is a constant.
- MVT SubVT = N->getValueType(0);
+ EVT SubVT = N->getValueType(0);
SDValue Idx = N->getOperand(1);
DebugLoc dl = N->getDebugLoc();
SDValue Lo, Hi;
@@ -1025,7 +1025,7 @@
SDValue DAGTypeLegalizer::SplitVecOp_EXTRACT_VECTOR_ELT(SDNode *N) {
SDValue Vec = N->getOperand(0);
SDValue Idx = N->getOperand(1);
- MVT VecVT = Vec.getValueType();
+ EVT VecVT = Vec.getValueType();
if (isa<ConstantSDNode>(Idx)) {
uint64_t IdxVal = cast<ConstantSDNode>(Idx)->getZExtValue();
@@ -1044,7 +1044,7 @@
}
// Store the vector to the stack.
- MVT EltVT = VecVT.getVectorElementType();
+ EVT EltVT = VecVT.getVectorElementType();
DebugLoc dl = N->getDebugLoc();
SDValue StackPtr = DAG.CreateStackTemporary(VecVT);
int SPFI = cast<FrameIndexSDNode>(StackPtr.getNode())->getIndex();
@@ -1066,13 +1066,13 @@
SDValue Ch = N->getChain();
SDValue Ptr = N->getBasePtr();
int SVOffset = N->getSrcValueOffset();
- MVT MemoryVT = N->getMemoryVT();
+ EVT MemoryVT = N->getMemoryVT();
unsigned Alignment = N->getAlignment();
bool isVol = N->isVolatile();
SDValue Lo, Hi;
GetSplitVector(N->getOperand(1), Lo, Hi);
- MVT LoMemVT, HiMemVT;
+ EVT LoMemVT, HiMemVT;
GetSplitDestVTs(MemoryVT, LoMemVT, HiMemVT);
unsigned IncrementSize = LoMemVT.getSizeInBits()/8;
@@ -1097,7 +1097,7 @@
Hi = DAG.getStore(Ch, dl, Hi, Ptr, N->getSrcValue(), SVOffset+IncrementSize,
isVol, MinAlign(Alignment, IncrementSize));
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other, Lo, Hi);
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other, Lo, Hi);
}
@@ -1197,7 +1197,7 @@
SDValue DAGTypeLegalizer::WidenVecRes_Binary(SDNode *N) {
// Binary op widening.
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue InOp1 = GetWidenedVector(N->getOperand(0));
SDValue InOp2 = GetWidenedVector(N->getOperand(1));
return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp1, InOp2);
@@ -1207,12 +1207,12 @@
SDValue InOp = N->getOperand(0);
DebugLoc dl = N->getDebugLoc();
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned WidenNumElts = WidenVT.getVectorNumElements();
- MVT InVT = InOp.getValueType();
- MVT InEltVT = InVT.getVectorElementType();
- MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts);
+ EVT InVT = InOp.getValueType();
+ EVT InEltVT = InVT.getVectorElementType();
+ EVT InWidenVT = EVT::getVectorVT(InEltVT, WidenNumElts);
unsigned Opcode = N->getOpcode();
unsigned InVTNumElts = InVT.getVectorNumElements();
@@ -1254,7 +1254,7 @@
// Otherwise unroll into some nasty scalar code and rebuild the vector.
SmallVector<SDValue, 16> Ops(WidenNumElts);
- MVT EltVT = WidenVT.getVectorElementType();
+ EVT EltVT = WidenVT.getVectorElementType();
unsigned MinElts = std::min(InVTNumElts, WidenNumElts);
unsigned i;
for (i=0; i < MinElts; ++i)
@@ -1270,16 +1270,16 @@
}
SDValue DAGTypeLegalizer::WidenVecRes_Shift(SDNode *N) {
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue InOp = GetWidenedVector(N->getOperand(0));
SDValue ShOp = N->getOperand(1);
- MVT ShVT = ShOp.getValueType();
+ EVT ShVT = ShOp.getValueType();
if (getTypeAction(ShVT) == WidenVector) {
ShOp = GetWidenedVector(ShOp);
ShVT = ShOp.getValueType();
}
- MVT ShWidenVT = MVT::getVectorVT(ShVT.getVectorElementType(),
+ EVT ShWidenVT = EVT::getVectorVT(ShVT.getVectorElementType(),
WidenVT.getVectorNumElements());
if (ShVT != ShWidenVT)
ShOp = ModifyToType(ShOp, ShWidenVT);
@@ -1289,16 +1289,16 @@
SDValue DAGTypeLegalizer::WidenVecRes_Unary(SDNode *N) {
// Unary op widening.
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
SDValue InOp = GetWidenedVector(N->getOperand(0));
return DAG.getNode(N->getOpcode(), N->getDebugLoc(), WidenVT, InOp);
}
SDValue DAGTypeLegalizer::WidenVecRes_BIT_CONVERT(SDNode *N) {
SDValue InOp = N->getOperand(0);
- MVT InVT = InOp.getValueType();
- MVT VT = N->getValueType(0);
- MVT WidenVT = TLI.getTypeToTransformTo(VT);
+ EVT InVT = InOp.getValueType();
+ EVT VT = N->getValueType(0);
+ EVT WidenVT = TLI.getTypeToTransformTo(VT);
DebugLoc dl = N->getDebugLoc();
switch (getTypeAction(InVT)) {
@@ -1338,13 +1338,13 @@
// Determine new input vector type. The new input vector type will use
// the same element type (if its a vector) or use the input type as a
// vector. It is the same size as the type to widen to.
- MVT NewInVT;
+ EVT NewInVT;
unsigned NewNumElts = WidenSize / InSize;
if (InVT.isVector()) {
- MVT InEltVT = InVT.getVectorElementType();
- NewInVT= MVT::getVectorVT(InEltVT, WidenSize / InEltVT.getSizeInBits());
+ EVT InEltVT = InVT.getVectorElementType();
+ NewInVT= EVT::getVectorVT(InEltVT, WidenSize / InEltVT.getSizeInBits());
} else {
- NewInVT = MVT::getVectorVT(InVT, NewNumElts);
+ NewInVT = EVT::getVectorVT(InVT, NewNumElts);
}
if (TLI.isTypeLegal(NewInVT)) {
@@ -1376,11 +1376,11 @@
SDValue DAGTypeLegalizer::WidenVecRes_BUILD_VECTOR(SDNode *N) {
DebugLoc dl = N->getDebugLoc();
// Build a vector with undefined for the new nodes.
- MVT VT = N->getValueType(0);
- MVT EltVT = VT.getVectorElementType();
+ EVT VT = N->getValueType(0);
+ EVT EltVT = VT.getVectorElementType();
unsigned NumElts = VT.getVectorNumElements();
- MVT WidenVT = TLI.getTypeToTransformTo(VT);
+ EVT WidenVT = TLI.getTypeToTransformTo(VT);
unsigned WidenNumElts = WidenVT.getVectorNumElements();
SmallVector<SDValue, 16> NewOps(N->op_begin(), N->op_end());
@@ -1392,8 +1392,8 @@
}
SDValue DAGTypeLegalizer::WidenVecRes_CONCAT_VECTORS(SDNode *N) {
- MVT InVT = N->getOperand(0).getValueType();
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT InVT = N->getOperand(0).getValueType();
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
DebugLoc dl = N->getDebugLoc();
unsigned WidenNumElts = WidenVT.getVectorNumElements();
unsigned NumOperands = N->getNumOperands();
@@ -1442,7 +1442,7 @@
}
// Fall back to use extracts and build vector.
- MVT EltVT = WidenVT.getVectorElementType();
+ EVT EltVT = WidenVT.getVectorElementType();
unsigned NumInElts = InVT.getVectorNumElements();
SmallVector<SDValue, 16> Ops(WidenNumElts);
unsigned Idx = 0;
@@ -1466,12 +1466,12 @@
SDValue RndOp = N->getOperand(3);
SDValue SatOp = N->getOperand(4);
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned WidenNumElts = WidenVT.getVectorNumElements();
- MVT InVT = InOp.getValueType();
- MVT InEltVT = InVT.getVectorElementType();
- MVT InWidenVT = MVT::getVectorVT(InEltVT, WidenNumElts);
+ EVT InVT = InOp.getValueType();
+ EVT InEltVT = InVT.getVectorElementType();
+ EVT InWidenVT = EVT::getVectorVT(InEltVT, WidenNumElts);
SDValue DTyOp = DAG.getValueType(WidenVT);
SDValue STyOp = DAG.getValueType(InWidenVT);
@@ -1518,7 +1518,7 @@
// Otherwise unroll into some nasty scalar code and rebuild the vector.
SmallVector<SDValue, 16> Ops(WidenNumElts);
- MVT EltVT = WidenVT.getVectorElementType();
+ EVT EltVT = WidenVT.getVectorElementType();
DTyOp = DAG.getValueType(EltVT);
STyOp = DAG.getValueType(InEltVT);
@@ -1539,8 +1539,8 @@
}
SDValue DAGTypeLegalizer::WidenVecRes_EXTRACT_SUBVECTOR(SDNode *N) {
- MVT VT = N->getValueType(0);
- MVT WidenVT = TLI.getTypeToTransformTo(VT);
+ EVT VT = N->getValueType(0);
+ EVT WidenVT = TLI.getTypeToTransformTo(VT);
unsigned WidenNumElts = WidenVT.getVectorNumElements();
SDValue InOp = N->getOperand(0);
SDValue Idx = N->getOperand(1);
@@ -1549,7 +1549,7 @@
if (getTypeAction(InOp.getValueType()) == WidenVector)
InOp = GetWidenedVector(InOp);
- MVT InVT = InOp.getValueType();
+ EVT InVT = InOp.getValueType();
ConstantSDNode *CIdx = dyn_cast<ConstantSDNode>(Idx);
if (CIdx) {
@@ -1567,8 +1567,8 @@
// We could try widening the input to the right length but for now, extract
// the original elements, fill the rest with undefs and build a vector.
SmallVector<SDValue, 16> Ops(WidenNumElts);
- MVT EltVT = VT.getVectorElementType();
- MVT IdxVT = Idx.getValueType();
+ EVT EltVT = VT.getVectorElementType();
+ EVT IdxVT = Idx.getValueType();
unsigned NumElts = VT.getVectorNumElements();
unsigned i;
if (CIdx) {
@@ -1600,8 +1600,8 @@
SDValue DAGTypeLegalizer::WidenVecRes_LOAD(SDNode *N) {
LoadSDNode *LD = cast<LoadSDNode>(N);
- MVT WidenVT = TLI.getTypeToTransformTo(LD->getValueType(0));
- MVT LdVT = LD->getMemoryVT();
+ EVT WidenVT = TLI.getTypeToTransformTo(LD->getValueType(0));
+ EVT LdVT = LD->getMemoryVT();
DebugLoc dl = N->getDebugLoc();
assert(LdVT.isVector() && WidenVT.isVector());
@@ -1620,8 +1620,8 @@
// For extension loads, we can not play the tricks of chopping legal
// vector types and bit cast it to the right type. Instead, we unroll
// the load and build a vector.
- MVT EltVT = WidenVT.getVectorElementType();
- MVT LdEltVT = LdVT.getVectorElementType();
+ EVT EltVT = WidenVT.getVectorElementType();
+ EVT LdEltVT = LdVT.getVectorElementType();
unsigned NumElts = LdVT.getVectorNumElements();
// Load each element and widen
@@ -1660,7 +1660,7 @@
if (LdChain.size() == 1)
NewChain = LdChain[0];
else
- NewChain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &LdChain[0],
+ NewChain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &LdChain[0],
LdChain.size());
// Modified the chain - switch anything that used the old chain to use
@@ -1671,20 +1671,20 @@
}
SDValue DAGTypeLegalizer::WidenVecRes_SCALAR_TO_VECTOR(SDNode *N) {
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
return DAG.getNode(ISD::SCALAR_TO_VECTOR, N->getDebugLoc(),
WidenVT, N->getOperand(0));
}
SDValue DAGTypeLegalizer::WidenVecRes_SELECT(SDNode *N) {
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned WidenNumElts = WidenVT.getVectorNumElements();
SDValue Cond1 = N->getOperand(0);
- MVT CondVT = Cond1.getValueType();
+ EVT CondVT = Cond1.getValueType();
if (CondVT.isVector()) {
- MVT CondEltVT = CondVT.getVectorElementType();
- MVT CondWidenVT = MVT::getVectorVT(CondEltVT, WidenNumElts);
+ EVT CondEltVT = CondVT.getVectorElementType();
+ EVT CondWidenVT = EVT::getVectorVT(CondEltVT, WidenNumElts);
if (getTypeAction(CondVT) == WidenVector)
Cond1 = GetWidenedVector(Cond1);
@@ -1708,15 +1708,15 @@
}
SDValue DAGTypeLegalizer::WidenVecRes_UNDEF(SDNode *N) {
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
return DAG.getUNDEF(WidenVT);
}
SDValue DAGTypeLegalizer::WidenVecRes_VECTOR_SHUFFLE(ShuffleVectorSDNode *N) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
- MVT WidenVT = TLI.getTypeToTransformTo(VT);
+ EVT WidenVT = TLI.getTypeToTransformTo(VT);
unsigned NumElts = VT.getVectorNumElements();
unsigned WidenNumElts = WidenVT.getVectorNumElements();
@@ -1738,13 +1738,13 @@
}
SDValue DAGTypeLegalizer::WidenVecRes_VSETCC(SDNode *N) {
- MVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
+ EVT WidenVT = TLI.getTypeToTransformTo(N->getValueType(0));
unsigned WidenNumElts = WidenVT.getVectorNumElements();
SDValue InOp1 = N->getOperand(0);
- MVT InVT = InOp1.getValueType();
+ EVT InVT = InOp1.getValueType();
assert(InVT.isVector() && "can not widen non vector type");
- MVT WidenInVT = MVT::getVectorVT(InVT.getVectorElementType(), WidenNumElts);
+ EVT WidenInVT = EVT::getVectorVT(InVT.getVectorElementType(), WidenNumElts);
InOp1 = GetWidenedVector(InOp1);
SDValue InOp2 = GetWidenedVector(N->getOperand(1));
@@ -1812,15 +1812,15 @@
// Since the result is legal and the input is illegal, it is unlikely
// that we can fix the input to a legal type so unroll the convert
// into some scalar code and create a nasty build vector.
- MVT VT = N->getValueType(0);
- MVT EltVT = VT.getVectorElementType();
+ EVT VT = N->getValueType(0);
+ EVT EltVT = VT.getVectorElementType();
DebugLoc dl = N->getDebugLoc();
unsigned NumElts = VT.getVectorNumElements();
SDValue InOp = N->getOperand(0);
if (getTypeAction(InOp.getValueType()) == WidenVector)
InOp = GetWidenedVector(InOp);
- MVT InVT = InOp.getValueType();
- MVT InEltVT = InVT.getVectorElementType();
+ EVT InVT = InOp.getValueType();
+ EVT InEltVT = InVT.getVectorElementType();
unsigned Opcode = N->getOpcode();
SmallVector<SDValue, 16> Ops(NumElts);
@@ -1833,9 +1833,9 @@
}
SDValue DAGTypeLegalizer::WidenVecOp_BIT_CONVERT(SDNode *N) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
SDValue InOp = GetWidenedVector(N->getOperand(0));
- MVT InWidenVT = InOp.getValueType();
+ EVT InWidenVT = InOp.getValueType();
DebugLoc dl = N->getDebugLoc();
// Check if we can convert between two legal vector types and extract.
@@ -1843,7 +1843,7 @@
unsigned Size = VT.getSizeInBits();
if (InWidenSize % Size == 0 && !VT.isVector()) {
unsigned NewNumElts = InWidenSize / Size;
- MVT NewVT = MVT::getVectorVT(VT, NewNumElts);
+ EVT NewVT = EVT::getVectorVT(VT, NewNumElts);
if (TLI.isTypeLegal(NewVT)) {
SDValue BitOp = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, InOp);
return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, VT, BitOp,
@@ -1858,13 +1858,13 @@
// If the input vector is not legal, it is likely that we will not find a
// legal vector of the same size. Replace the concatenate vector with a
// nasty build vector.
- MVT VT = N->getValueType(0);
- MVT EltVT = VT.getVectorElementType();
+ EVT VT = N->getValueType(0);
+ EVT EltVT = VT.getVectorElementType();
DebugLoc dl = N->getDebugLoc();
unsigned NumElts = VT.getVectorNumElements();
SmallVector<SDValue, 16> Ops(NumElts);
- MVT InVT = N->getOperand(0).getValueType();
+ EVT InVT = N->getOperand(0).getValueType();
unsigned NumInElts = InVT.getVectorNumElements();
unsigned Idx = 0;
@@ -1899,8 +1899,8 @@
SDValue ValOp = GetWidenedVector(ST->getValue());
DebugLoc dl = N->getDebugLoc();
- MVT StVT = ST->getMemoryVT();
- MVT ValVT = ValOp.getValueType();
+ EVT StVT = ST->getMemoryVT();
+ EVT ValVT = ValOp.getValueType();
// It must be true that we the widen vector type is bigger than where
// we need to store.
assert(StVT.isVector() && ValOp.getValueType().isVector());
@@ -1911,8 +1911,8 @@
// For truncating stores, we can not play the tricks of chopping legal
// vector types and bit cast it to the right type. Instead, we unroll
// the store.
- MVT StEltVT = StVT.getVectorElementType();
- MVT ValEltVT = ValVT.getVectorElementType();
+ EVT StEltVT = StVT.getVectorElementType();
+ EVT ValEltVT = ValVT.getVectorElementType();
unsigned Increment = ValEltVT.getSizeInBits() / 8;
unsigned NumElts = StVT.getVectorNumElements();
SDValue EOp = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, ValEltVT, ValOp,
@@ -1941,7 +1941,7 @@
return StChain[0];
else
return DAG.getNode(ISD::TokenFactor, dl,
- MVT::Other,&StChain[0],StChain.size());
+ EVT::Other,&StChain[0],StChain.size());
}
//===----------------------------------------------------------------------===//
@@ -1958,8 +1958,8 @@
// Returns NewVecVT and NewEltVT - the vector type and its associated
// element type.
static void FindAssocWidenVecType(const TargetLowering &TLI, unsigned Width,
- MVT VecVT,
- MVT& NewEltVT, MVT& NewVecVT) {
+ EVT VecVT,
+ EVT& NewEltVT, EVT& NewVecVT) {
unsigned EltWidth = Width + 1;
if (TLI.isTypeLegal(VecVT)) {
// We start with the preferred with, making it a power of 2 and find a
@@ -1969,9 +1969,9 @@
do {
assert(EltWidth > 0);
EltWidth = 1 << Log2_32(EltWidth - 1);
- NewEltVT = MVT::getIntegerVT(EltWidth);
+ NewEltVT = EVT::getIntegerVT(EltWidth);
unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
- NewVecVT = MVT::getVectorVT(NewEltVT, NumElts);
+ NewVecVT = EVT::getVectorVT(NewEltVT, NumElts);
} while (!TLI.isTypeLegal(NewVecVT) ||
VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
} else {
@@ -1984,9 +1984,9 @@
do {
assert(EltWidth > 0);
EltWidth = 1 << Log2_32(EltWidth - 1);
- NewEltVT = MVT::getIntegerVT(EltWidth);
+ NewEltVT = EVT::getIntegerVT(EltWidth);
unsigned NumElts = VecVT.getSizeInBits() / EltWidth;
- NewVecVT = MVT::getVectorVT(NewEltVT, NumElts);
+ NewVecVT = EVT::getVectorVT(NewEltVT, NumElts);
} while (!TLI.isTypeLegal(NewEltVT) ||
VecVT.getSizeInBits() != NewVecVT.getSizeInBits());
}
@@ -2000,7 +2000,7 @@
unsigned Alignment,
bool isVolatile,
unsigned LdWidth,
- MVT ResType,
+ EVT ResType,
DebugLoc dl) {
// The strategy assumes that we can efficiently load powers of two widths.
// The routines chops the vector into the largest power of 2 load and
@@ -2011,7 +2011,7 @@
// the load is nonvolatile, we an use a wider load for the value.
// Find the vector type that can load from.
- MVT NewEltVT, NewVecVT;
+ EVT NewEltVT, NewVecVT;
unsigned NewEltVTWidth;
FindAssocWidenVecType(TLI, LdWidth, ResType, NewEltVT, NewVecVT);
NewEltVTWidth = NewEltVT.getSizeInBits();
@@ -2075,8 +2075,8 @@
// want to store. This avoids requiring a stack convert.
// Find a width of the element type we can store with
- MVT WidenVT = ValOp.getValueType();
- MVT NewEltVT, NewVecVT;
+ EVT WidenVT = ValOp.getValueType();
+ EVT NewEltVT, NewVecVT;
FindAssocWidenVecType(TLI, StWidth, WidenVT, NewEltVT, NewVecVT);
unsigned NewEltVTWidth = NewEltVT.getSizeInBits();
@@ -2125,10 +2125,10 @@
/// Modifies a vector input (widen or narrows) to a vector of NVT. The
/// input vector must have the same element type as NVT.
-SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, MVT NVT) {
+SDValue DAGTypeLegalizer::ModifyToType(SDValue InOp, EVT NVT) {
// Note that InOp might have been widened so it might already have
// the right width or it might need be narrowed.
- MVT InVT = InOp.getValueType();
+ EVT InVT = InOp.getValueType();
assert(InVT.getVectorElementType() == NVT.getVectorElementType() &&
"input and widen element type must match");
DebugLoc dl = InOp.getDebugLoc();
@@ -2156,7 +2156,7 @@
// Fall back to extract and build.
SmallVector<SDValue, 16> Ops(WidenNumElts);
- MVT EltVT = NVT.getVectorElementType();
+ EVT EltVT = NVT.getVectorElementType();
unsigned MinNumElts = std::min(WidenNumElts, InNumElts);
unsigned Idx;
for (Idx = 0; Idx < MinNumElts; ++Idx)
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
index 515ec91..ee83f06 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp
@@ -215,16 +215,16 @@
SUnit *NewSU;
bool TryUnfold = false;
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
- MVT VT = N->getValueType(i);
- if (VT == MVT::Flag)
+ EVT VT = N->getValueType(i);
+ if (VT == EVT::Flag)
return NULL;
- else if (VT == MVT::Other)
+ else if (VT == EVT::Other)
TryUnfold = true;
}
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
const SDValue &Op = N->getOperand(i);
- MVT VT = Op.getNode()->getValueType(Op.getResNo());
- if (VT == MVT::Flag)
+ EVT VT = Op.getNode()->getValueType(Op.getResNo());
+ if (VT == EVT::Flag)
return NULL;
}
@@ -420,7 +420,7 @@
/// getPhysicalRegisterVT - Returns the ValueType of the physical register
/// definition of the specified node.
/// FIXME: Move to SelectionDAG?
-static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
+static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
const TargetInstrInfo *TII) {
const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
@@ -534,7 +534,7 @@
assert(LRegs.size() == 1 && "Can't handle this yet!");
unsigned Reg = LRegs[0];
SUnit *LRDef = LiveRegDefs[Reg];
- MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
+ EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
const TargetRegisterClass *RC =
TRI->getPhysicalRegisterRegClass(Reg, VT);
const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 7c30990..5c7b849 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -352,16 +352,16 @@
SUnit *NewSU;
bool TryUnfold = false;
for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
- MVT VT = N->getValueType(i);
- if (VT == MVT::Flag)
+ EVT VT = N->getValueType(i);
+ if (VT == EVT::Flag)
return NULL;
- else if (VT == MVT::Other)
+ else if (VT == EVT::Other)
TryUnfold = true;
}
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
const SDValue &Op = N->getOperand(i);
- MVT VT = Op.getNode()->getValueType(Op.getResNo());
- if (VT == MVT::Flag)
+ EVT VT = Op.getNode()->getValueType(Op.getResNo());
+ if (VT == EVT::Flag)
return NULL;
}
@@ -571,7 +571,7 @@
/// getPhysicalRegisterVT - Returns the ValueType of the physical register
/// definition of the specified node.
/// FIXME: Move to SelectionDAG?
-static MVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
+static EVT getPhysicalRegisterVT(SDNode *N, unsigned Reg,
const TargetInstrInfo *TII) {
const TargetInstrDesc &TID = TII->get(N->getMachineOpcode());
assert(TID.ImplicitDefs && "Physical reg def must be in implicit def list!");
@@ -630,7 +630,7 @@
if (Node->getOpcode() == ISD::INLINEASM) {
// Inline asm can clobber physical defs.
unsigned NumOps = Node->getNumOperands();
- if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
+ if (Node->getOperand(NumOps-1).getValueType() == EVT::Flag)
--NumOps; // Ignore the flag operand.
for (unsigned i = 2; i != NumOps;) {
@@ -754,7 +754,7 @@
assert(LRegs.size() == 1 && "Can't handle this yet!");
unsigned Reg = LRegs[0];
SUnit *LRDef = LiveRegDefs[Reg];
- MVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
+ EVT VT = getPhysicalRegisterVT(LRDef->getNode(), Reg, TII);
const TargetRegisterClass *RC =
TRI->getPhysicalRegisterRegClass(Reg, VT);
const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
@@ -1216,8 +1216,8 @@
if (!SUImpDefs)
return false;
for (unsigned i = NumDefs, e = N->getNumValues(); i != e; ++i) {
- MVT VT = N->getValueType(i);
- if (VT == MVT::Flag || VT == MVT::Other)
+ EVT VT = N->getValueType(i);
+ if (VT == EVT::Flag || VT == EVT::Other)
continue;
if (!N->hasAnyUseOfValue(i))
continue;
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
index 4e8e972..4d2882a 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -111,7 +111,7 @@
// Scan up to find flagged preds.
SDNode *N = NI;
while (N->getNumOperands() &&
- N->getOperand(N->getNumOperands()-1).getValueType() == MVT::Flag) {
+ N->getOperand(N->getNumOperands()-1).getValueType() == EVT::Flag) {
N = N->getOperand(N->getNumOperands()-1).getNode();
assert(N->getNodeId() == -1 && "Node already inserted!");
N->setNodeId(NodeSUnit->NodeNum);
@@ -119,7 +119,7 @@
// Scan down to find any flagged succs.
N = NI;
- while (N->getValueType(N->getNumValues()-1) == MVT::Flag) {
+ while (N->getValueType(N->getNumValues()-1) == EVT::Flag) {
SDValue FlagVal(N, N->getNumValues()-1);
// There are either zero or one users of the Flag result.
@@ -189,9 +189,9 @@
assert(OpSU && "Node has no SUnit!");
if (OpSU == SU) continue; // In the same group.
- MVT OpVT = N->getOperand(i).getValueType();
- assert(OpVT != MVT::Flag && "Flagged nodes should be in same sunit!");
- bool isChain = OpVT == MVT::Other;
+ EVT OpVT = N->getOperand(i).getValueType();
+ assert(OpVT != EVT::Flag && "Flagged nodes should be in same sunit!");
+ bool isChain = OpVT == EVT::Other;
unsigned PhysReg = 0;
int Cost = 1;
@@ -244,9 +244,9 @@
/// not go into the resulting MachineInstr).
unsigned ScheduleDAGSDNodes::CountResults(SDNode *Node) {
unsigned N = Node->getNumValues();
- while (N && Node->getValueType(N - 1) == MVT::Flag)
+ while (N && Node->getValueType(N - 1) == EVT::Flag)
--N;
- if (N && Node->getValueType(N - 1) == MVT::Other)
+ if (N && Node->getValueType(N - 1) == EVT::Other)
--N; // Skip over chain result.
return N;
}
@@ -266,9 +266,9 @@
/// operand
unsigned ScheduleDAGSDNodes::ComputeMemOperandsEnd(SDNode *Node) {
unsigned N = Node->getNumOperands();
- while (N && Node->getOperand(N - 1).getValueType() == MVT::Flag)
+ while (N && Node->getOperand(N - 1).getValueType() == EVT::Flag)
--N;
- if (N && Node->getOperand(N - 1).getValueType() == MVT::Other)
+ if (N && Node->getOperand(N - 1).getValueType() == EVT::Other)
--N; // Ignore chain if it exists.
return N;
}
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
index 1d845a5..d8736a1 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp
@@ -69,8 +69,8 @@
SDValue Op = User->getOperand(i);
if (Op.getNode() != Node || Op.getResNo() != ResNo)
continue;
- MVT VT = Node->getValueType(Op.getResNo());
- if (VT == MVT::Other || VT == MVT::Flag)
+ EVT VT = Node->getValueType(Op.getResNo());
+ if (VT == EVT::Other || VT == EVT::Flag)
continue;
Match = false;
if (User->isMachineOpcode()) {
@@ -95,7 +95,7 @@
break;
}
- MVT VT = Node->getValueType(ResNo);
+ EVT VT = Node->getValueType(ResNo);
const TargetRegisterClass *SrcRC = 0, *DstRC = 0;
SrcRC = TRI->getPhysicalRegisterRegClass(SrcReg, VT);
@@ -238,8 +238,8 @@
unsigned IIOpNum,
const TargetInstrDesc *II,
DenseMap<SDValue, unsigned> &VRBaseMap) {
- assert(Op.getValueType() != MVT::Other &&
- Op.getValueType() != MVT::Flag &&
+ assert(Op.getValueType() != EVT::Other &&
+ Op.getValueType() != EVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
// Get/emit the operand.
unsigned VReg = getVR(Op, VRBaseMap);
@@ -322,8 +322,8 @@
MI->addOperand(MachineOperand::CreateES(ES->getSymbol(), 0,
ES->getTargetFlags()));
} else {
- assert(Op.getValueType() != MVT::Other &&
- Op.getValueType() != MVT::Flag &&
+ assert(Op.getValueType() != EVT::Other &&
+ Op.getValueType() != EVT::Flag &&
"Chain and flag operands should occur at end of operand list!");
AddRegisterOperand(MI, Op, IIOpNum, II, VRBaseMap);
}
@@ -334,7 +334,7 @@
/// type matches the specified type.
static const TargetRegisterClass*
getSuperRegisterRegClass(const TargetRegisterClass *TRC,
- unsigned SubIdx, MVT VT) {
+ unsigned SubIdx, EVT VT) {
// Pick the register class of the superegister for this type
for (TargetRegisterInfo::regclass_iterator I = TRC->superregclasses_begin(),
E = TRC->superregclasses_end(); I != E; ++I)
@@ -599,7 +599,7 @@
}
case ISD::INLINEASM: {
unsigned NumOps = Node->getNumOperands();
- if (Node->getOperand(NumOps-1).getValueType() == MVT::Flag)
+ if (Node->getOperand(NumOps-1).getValueType() == EVT::Flag)
--NumOps; // Ignore the flag operand.
// Create the inline asm machine instruction.
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index bead83d..712feda 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -47,19 +47,19 @@
/// makeVTList - Return an instance of the SDVTList struct initialized with the
/// specified members.
-static SDVTList makeVTList(const MVT *VTs, unsigned NumVTs) {
+static SDVTList makeVTList(const EVT *VTs, unsigned NumVTs) {
SDVTList Res = {VTs, NumVTs};
return Res;
}
-static const fltSemantics *MVTToAPFloatSemantics(MVT VT) {
+static const fltSemantics *EVTToAPFloatSemantics(EVT VT) {
switch (VT.getSimpleVT()) {
default: llvm_unreachable("Unknown FP format");
- case MVT::f32: return &APFloat::IEEEsingle;
- case MVT::f64: return &APFloat::IEEEdouble;
- case MVT::f80: return &APFloat::x87DoubleExtended;
- case MVT::f128: return &APFloat::IEEEquad;
- case MVT::ppcf128: return &APFloat::PPCDoubleDouble;
+ case EVT::f32: return &APFloat::IEEEsingle;
+ case EVT::f64: return &APFloat::IEEEdouble;
+ case EVT::f80: return &APFloat::x87DoubleExtended;
+ case EVT::f128: return &APFloat::IEEEquad;
+ case EVT::ppcf128: return &APFloat::PPCDoubleDouble;
}
}
@@ -77,19 +77,19 @@
return getValueAPF().bitwiseIsEqual(V);
}
-bool ConstantFPSDNode::isValueValidForType(MVT VT,
+bool ConstantFPSDNode::isValueValidForType(EVT VT,
const APFloat& Val) {
assert(VT.isFloatingPoint() && "Can only convert between FP types");
// PPC long double cannot be converted to any other type.
- if (VT == MVT::ppcf128 ||
+ if (VT == EVT::ppcf128 ||
&Val.getSemantics() == &APFloat::PPCDoubleDouble)
return false;
// convert modifies in place, so make a copy.
APFloat Val2 = APFloat(Val);
bool losesInfo;
- (void) Val2.convert(*MVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven,
+ (void) Val2.convert(*EVTToAPFloatSemantics(VT), APFloat::rmNearestTiesToEven,
&losesInfo);
return !losesInfo;
}
@@ -502,7 +502,7 @@
/// doNotCSE - Return true if CSE should not be performed for this node.
static bool doNotCSE(SDNode *N) {
- if (N->getValueType(0) == MVT::Flag)
+ if (N->getValueType(0) == EVT::Flag)
return true; // Never CSE anything that produces a flag.
switch (N->getOpcode()) {
@@ -517,7 +517,7 @@
// Check that remaining values produced are not flags.
for (unsigned i = 1, e = N->getNumValues(); i != e; ++i)
- if (N->getValueType(i) == MVT::Flag)
+ if (N->getValueType(i) == EVT::Flag)
return true; // Never CSE anything that produces a flag.
return false;
@@ -638,7 +638,7 @@
break;
}
case ISD::VALUETYPE: {
- MVT VT = cast<VTSDNode>(N)->getVT();
+ EVT VT = cast<VTSDNode>(N)->getVT();
if (VT.isExtended()) {
Erased = ExtendedValueTypeNodes.erase(VT);
} else {
@@ -656,7 +656,7 @@
// Verify that the node was actually in one of the CSE maps, unless it has a
// flag result (which cannot be CSE'd) or is one of the special cases that are
// not subject to CSE.
- if (!Erased && N->getValueType(N->getNumValues()-1) != MVT::Flag &&
+ if (!Erased && N->getValueType(N->getNumValues()-1) != EVT::Flag &&
!N->isMachineOpcode() && !doNotCSE(N)) {
N->dump(this);
cerr << "\n";
@@ -754,7 +754,7 @@
default:
break;
case ISD::BUILD_PAIR: {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
assert(N->getNumValues() == 1 && "Too many results!");
assert(!VT.isVector() && (VT.isInteger() || VT.isFloatingPoint()) &&
"Wrong return type!");
@@ -772,7 +772,7 @@
assert(N->getValueType(0).isVector() && "Wrong return type!");
assert(N->getNumOperands() == N->getValueType(0).getVectorNumElements() &&
"Wrong number of operands!");
- MVT EltVT = N->getValueType(0).getVectorElementType();
+ EVT EltVT = N->getValueType(0).getVectorElementType();
for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I)
assert((I->getValueType() == EltVT ||
(EltVT.isInteger() && I->getValueType().isInteger() &&
@@ -783,13 +783,13 @@
}
}
-/// getMVTAlignment - Compute the default alignment value for the
+/// getEVTAlignment - Compute the default alignment value for the
/// given type.
///
-unsigned SelectionDAG::getMVTAlignment(MVT VT) const {
- const Type *Ty = VT == MVT::iPTR ?
+unsigned SelectionDAG::getEVTAlignment(EVT VT) const {
+ const Type *Ty = VT == EVT::iPTR ?
PointerType::get(Type::Int8Ty, 0) :
- VT.getTypeForMVT();
+ VT.getTypeForEVT();
return TLI.getTargetData()->getABITypeAlignment(Ty);
}
@@ -798,7 +798,7 @@
SelectionDAG::SelectionDAG(TargetLowering &tli, FunctionLoweringInfo &fli)
: TLI(tli), FLI(fli), DW(0),
EntryNode(ISD::EntryToken, DebugLoc::getUnknownLoc(),
- getVTList(MVT::Other)), Root(getEntryNode()) {
+ getVTList(EVT::Other)), Root(getEntryNode()) {
AllNodes.push_back(&EntryNode);
}
@@ -839,7 +839,7 @@
Root = getEntryNode();
}
-SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, MVT VT) {
+SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, DebugLoc DL, EVT VT) {
if (Op.getValueType() == VT) return Op;
APInt Imm = APInt::getLowBitsSet(Op.getValueSizeInBits(),
VT.getSizeInBits());
@@ -849,29 +849,29 @@
/// getNOT - Create a bitwise NOT operation as (XOR Val, -1).
///
-SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, MVT VT) {
- MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
+SDValue SelectionDAG::getNOT(DebugLoc DL, SDValue Val, EVT VT) {
+ EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
SDValue NegOne =
getConstant(APInt::getAllOnesValue(EltVT.getSizeInBits()), VT);
return getNode(ISD::XOR, DL, VT, Val, NegOne);
}
-SDValue SelectionDAG::getConstant(uint64_t Val, MVT VT, bool isT) {
- MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
+SDValue SelectionDAG::getConstant(uint64_t Val, EVT VT, bool isT) {
+ EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
assert((EltVT.getSizeInBits() >= 64 ||
(uint64_t)((int64_t)Val >> EltVT.getSizeInBits()) + 1 < 2) &&
"getConstant with a uint64_t value that doesn't fit in the type!");
return getConstant(APInt(EltVT.getSizeInBits(), Val), VT, isT);
}
-SDValue SelectionDAG::getConstant(const APInt &Val, MVT VT, bool isT) {
+SDValue SelectionDAG::getConstant(const APInt &Val, EVT VT, bool isT) {
return getConstant(*ConstantInt::get(*Context, Val), VT, isT);
}
-SDValue SelectionDAG::getConstant(const ConstantInt &Val, MVT VT, bool isT) {
+SDValue SelectionDAG::getConstant(const ConstantInt &Val, EVT VT, bool isT) {
assert(VT.isInteger() && "Cannot create FP integer constant!");
- MVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
+ EVT EltVT = VT.isVector() ? VT.getVectorElementType() : VT;
assert(Val.getBitWidth() == EltVT.getSizeInBits() &&
"APInt size does not match type size!");
@@ -906,14 +906,14 @@
}
-SDValue SelectionDAG::getConstantFP(const APFloat& V, MVT VT, bool isTarget) {
+SDValue SelectionDAG::getConstantFP(const APFloat& V, EVT VT, bool isTarget) {
return getConstantFP(*ConstantFP::get(*getContext(), V), VT, isTarget);
}
-SDValue SelectionDAG::getConstantFP(const ConstantFP& V, MVT VT, bool isTarget){
+SDValue SelectionDAG::getConstantFP(const ConstantFP& V, EVT VT, bool isTarget){
assert(VT.isFloatingPoint() && "Cannot create integer FP constant!");
- MVT EltVT =
+ EVT EltVT =
VT.isVector() ? VT.getVectorElementType() : VT;
// Do the map lookup using the actual bit pattern for the floating point
@@ -946,24 +946,24 @@
return Result;
}
-SDValue SelectionDAG::getConstantFP(double Val, MVT VT, bool isTarget) {
- MVT EltVT =
+SDValue SelectionDAG::getConstantFP(double Val, EVT VT, bool isTarget) {
+ EVT EltVT =
VT.isVector() ? VT.getVectorElementType() : VT;
- if (EltVT==MVT::f32)
+ if (EltVT==EVT::f32)
return getConstantFP(APFloat((float)Val), VT, isTarget);
else
return getConstantFP(APFloat(Val), VT, isTarget);
}
SDValue SelectionDAG::getGlobalAddress(const GlobalValue *GV,
- MVT VT, int64_t Offset,
+ EVT VT, int64_t Offset,
bool isTargetGA,
unsigned char TargetFlags) {
assert((TargetFlags == 0 || isTargetGA) &&
"Cannot set target flags on target-independent globals");
// Truncate (with sign-extension) the offset value to the pointer size.
- MVT PTy = TLI.getPointerTy();
+ EVT PTy = TLI.getPointerTy();
unsigned BitWidth = PTy.getSizeInBits();
if (BitWidth < 64)
Offset = (Offset << (64 - BitWidth) >> (64 - BitWidth));
@@ -996,7 +996,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getFrameIndex(int FI, MVT VT, bool isTarget) {
+SDValue SelectionDAG::getFrameIndex(int FI, EVT VT, bool isTarget) {
unsigned Opc = isTarget ? ISD::TargetFrameIndex : ISD::FrameIndex;
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opc, getVTList(VT), 0, 0);
@@ -1011,7 +1011,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getJumpTable(int JTI, MVT VT, bool isTarget,
+SDValue SelectionDAG::getJumpTable(int JTI, EVT VT, bool isTarget,
unsigned char TargetFlags) {
assert((TargetFlags == 0 || isTarget) &&
"Cannot set target flags on target-independent jump tables");
@@ -1030,7 +1030,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getConstantPool(Constant *C, MVT VT,
+SDValue SelectionDAG::getConstantPool(Constant *C, EVT VT,
unsigned Alignment, int Offset,
bool isTarget,
unsigned char TargetFlags) {
@@ -1056,7 +1056,7 @@
}
-SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, MVT VT,
+SDValue SelectionDAG::getConstantPool(MachineConstantPoolValue *C, EVT VT,
unsigned Alignment, int Offset,
bool isTarget,
unsigned char TargetFlags) {
@@ -1083,7 +1083,7 @@
SDValue SelectionDAG::getBasicBlock(MachineBasicBlock *MBB) {
FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::BasicBlock, getVTList(MVT::Other), 0, 0);
+ AddNodeIDNode(ID, ISD::BasicBlock, getVTList(EVT::Other), 0, 0);
ID.AddPointer(MBB);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
@@ -1095,7 +1095,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getValueType(MVT VT) {
+SDValue SelectionDAG::getValueType(EVT VT) {
if (VT.isSimple() && (unsigned)VT.getSimpleVT() >= ValueTypeNodes.size())
ValueTypeNodes.resize(VT.getSimpleVT()+1);
@@ -1109,7 +1109,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getExternalSymbol(const char *Sym, MVT VT) {
+SDValue SelectionDAG::getExternalSymbol(const char *Sym, EVT VT) {
SDNode *&N = ExternalSymbols[Sym];
if (N) return SDValue(N, 0);
N = NodeAllocator.Allocate<ExternalSymbolSDNode>();
@@ -1118,7 +1118,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, MVT VT,
+SDValue SelectionDAG::getTargetExternalSymbol(const char *Sym, EVT VT,
unsigned char TargetFlags) {
SDNode *&N =
TargetExternalSymbols[std::pair<std::string,unsigned char>(Sym,
@@ -1157,7 +1157,7 @@
}
}
-SDValue SelectionDAG::getVectorShuffle(MVT VT, DebugLoc dl, SDValue N1,
+SDValue SelectionDAG::getVectorShuffle(EVT VT, DebugLoc dl, SDValue N1,
SDValue N2, const int *Mask) {
assert(N1.getValueType() == N2.getValueType() && "Invalid VECTOR_SHUFFLE");
assert(VT.isVector() && N1.getValueType().isVector() &&
@@ -1247,7 +1247,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getConvertRndSat(MVT VT, DebugLoc dl,
+SDValue SelectionDAG::getConvertRndSat(EVT VT, DebugLoc dl,
SDValue Val, SDValue DTy,
SDValue STy, SDValue Rnd, SDValue Sat,
ISD::CvtCode Code) {
@@ -1269,7 +1269,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getRegister(unsigned RegNo, MVT VT) {
+SDValue SelectionDAG::getRegister(unsigned RegNo, EVT VT) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::Register, getVTList(VT), 0, 0);
ID.AddInteger(RegNo);
@@ -1298,7 +1298,7 @@
unsigned LabelID) {
FoldingSetNodeID ID;
SDValue Ops[] = { Root };
- AddNodeIDNode(ID, Opcode, getVTList(MVT::Other), &Ops[0], 1);
+ AddNodeIDNode(ID, Opcode, getVTList(EVT::Other), &Ops[0], 1);
ID.AddInteger(LabelID);
void *IP = 0;
if (SDNode *E = CSEMap.FindNodeOrInsertPos(ID, IP))
@@ -1315,7 +1315,7 @@
"SrcValue is not a pointer?");
FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(MVT::Other), 0, 0);
+ AddNodeIDNode(ID, ISD::SRCVALUE, getVTList(EVT::Other), 0, 0);
ID.AddPointer(V);
void *IP = 0;
@@ -1337,7 +1337,7 @@
#endif
FoldingSetNodeID ID;
- AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(MVT::Other), 0, 0);
+ AddNodeIDNode(ID, ISD::MEMOPERAND, getVTList(EVT::Other), 0, 0);
MO.Profile(ID);
void *IP = 0;
@@ -1354,8 +1354,8 @@
/// getShiftAmountOperand - Return the specified value casted to
/// the target's desired shift amount type.
SDValue SelectionDAG::getShiftAmountOperand(SDValue Op) {
- MVT OpTy = Op.getValueType();
- MVT ShTy = TLI.getShiftAmountTy();
+ EVT OpTy = Op.getValueType();
+ EVT ShTy = TLI.getShiftAmountTy();
if (OpTy == ShTy || OpTy.isVector()) return Op;
ISD::NodeType Opcode = OpTy.bitsGT(ShTy) ? ISD::TRUNCATE : ISD::ZERO_EXTEND;
@@ -1364,10 +1364,10 @@
/// CreateStackTemporary - Create a stack temporary, suitable for holding the
/// specified value type.
-SDValue SelectionDAG::CreateStackTemporary(MVT VT, unsigned minAlign) {
+SDValue SelectionDAG::CreateStackTemporary(EVT VT, unsigned minAlign) {
MachineFrameInfo *FrameInfo = getMachineFunction().getFrameInfo();
unsigned ByteSize = VT.getStoreSizeInBits()/8;
- const Type *Ty = VT.getTypeForMVT();
+ const Type *Ty = VT.getTypeForEVT();
unsigned StackAlign =
std::max((unsigned)TLI.getTargetData()->getPrefTypeAlignment(Ty), minAlign);
@@ -1377,11 +1377,11 @@
/// CreateStackTemporary - Create a stack temporary suitable for holding
/// either of the specified value types.
-SDValue SelectionDAG::CreateStackTemporary(MVT VT1, MVT VT2) {
+SDValue SelectionDAG::CreateStackTemporary(EVT VT1, EVT VT2) {
unsigned Bytes = std::max(VT1.getStoreSizeInBits(),
VT2.getStoreSizeInBits())/8;
- const Type *Ty1 = VT1.getTypeForMVT();
- const Type *Ty2 = VT2.getTypeForMVT();
+ const Type *Ty1 = VT1.getTypeForEVT();
+ const Type *Ty2 = VT2.getTypeForEVT();
const TargetData *TD = TLI.getTargetData();
unsigned Align = std::max(TD->getPrefTypeAlignment(Ty1),
TD->getPrefTypeAlignment(Ty2));
@@ -1391,7 +1391,7 @@
return getFrameIndex(FrameIdx, TLI.getPointerTy());
}
-SDValue SelectionDAG::FoldSetCC(MVT VT, SDValue N1,
+SDValue SelectionDAG::FoldSetCC(EVT VT, SDValue N1,
SDValue N2, ISD::CondCode Cond, DebugLoc dl) {
// These setcc operations always fold.
switch (Cond) {
@@ -1438,7 +1438,7 @@
if (ConstantFPSDNode *N1C = dyn_cast<ConstantFPSDNode>(N1.getNode())) {
if (ConstantFPSDNode *N2C = dyn_cast<ConstantFPSDNode>(N2.getNode())) {
// No compile time operations on this type yet.
- if (N1C->getValueType(0) == MVT::ppcf128)
+ if (N1C->getValueType(0) == EVT::ppcf128)
return SDValue();
APFloat::cmpResult R = N1C->getValueAPF().compare(N2C->getValueAPF());
@@ -1727,7 +1727,7 @@
}
return;
case ISD::SIGN_EXTEND_INREG: {
- MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
+ EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
unsigned EBits = EVT.getSizeInBits();
// Sign extension. Compute the demanded bits in the result that are not
@@ -1772,14 +1772,14 @@
case ISD::LOAD: {
if (ISD::isZEXTLoad(Op.getNode())) {
LoadSDNode *LD = cast<LoadSDNode>(Op);
- MVT VT = LD->getMemoryVT();
+ EVT VT = LD->getMemoryVT();
unsigned MemBits = VT.getSizeInBits();
KnownZero |= APInt::getHighBitsSet(BitWidth, BitWidth - MemBits) & Mask;
}
return;
}
case ISD::ZERO_EXTEND: {
- MVT InVT = Op.getOperand(0).getValueType();
+ EVT InVT = Op.getOperand(0).getValueType();
unsigned InBits = InVT.getSizeInBits();
APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask;
APInt InMask = Mask;
@@ -1793,7 +1793,7 @@
return;
}
case ISD::SIGN_EXTEND: {
- MVT InVT = Op.getOperand(0).getValueType();
+ EVT InVT = Op.getOperand(0).getValueType();
unsigned InBits = InVT.getSizeInBits();
APInt InSignBit = APInt::getSignBit(InBits);
APInt NewBits = APInt::getHighBitsSet(BitWidth, BitWidth - InBits) & Mask;
@@ -1834,7 +1834,7 @@
return;
}
case ISD::ANY_EXTEND: {
- MVT InVT = Op.getOperand(0).getValueType();
+ EVT InVT = Op.getOperand(0).getValueType();
unsigned InBits = InVT.getSizeInBits();
APInt InMask = Mask;
InMask.trunc(InBits);
@@ -1846,7 +1846,7 @@
return;
}
case ISD::TRUNCATE: {
- MVT InVT = Op.getOperand(0).getValueType();
+ EVT InVT = Op.getOperand(0).getValueType();
unsigned InBits = InVT.getSizeInBits();
APInt InMask = Mask;
InMask.zext(InBits);
@@ -1859,7 +1859,7 @@
break;
}
case ISD::AssertZext: {
- MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
+ EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
APInt InMask = APInt::getLowBitsSet(BitWidth, VT.getSizeInBits());
ComputeMaskedBits(Op.getOperand(0), Mask & InMask, KnownZero,
KnownOne, Depth+1);
@@ -1978,7 +1978,7 @@
/// information. For example, immediately after an "SRA X, 2", we know that
/// the top 3 bits are all equal to each other, so we return 3.
unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const{
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
assert(VT.isInteger() && "Invalid VT!");
unsigned VTBits = VT.getSizeInBits();
unsigned Tmp, Tmp2;
@@ -2213,7 +2213,7 @@
/// element of the result of the vector shuffle.
SDValue SelectionDAG::getShuffleScalarElt(const ShuffleVectorSDNode *N,
unsigned i) {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
if (N->getMaskElt(i) < 0)
return getUNDEF(VT.getVectorElementType());
@@ -2224,7 +2224,7 @@
if (V.getOpcode() == ISD::BIT_CONVERT) {
V = V.getOperand(0);
- MVT VVT = V.getValueType();
+ EVT VVT = V.getValueType();
if (!VVT.isVector() || VVT.getVectorNumElements() != (unsigned)NumElems)
return SDValue();
}
@@ -2241,7 +2241,7 @@
/// getNode - Gets or creates the specified node.
///
-SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT) {
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, getVTList(VT), 0, 0);
void *IP = 0;
@@ -2259,7 +2259,7 @@
}
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
- MVT VT, SDValue Operand) {
+ EVT VT, SDValue Operand) {
// Constant fold unary operations with an integer constant operand.
if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Operand.getNode())) {
const APInt &Val = C->getAPIntValue();
@@ -2276,7 +2276,7 @@
case ISD::SINT_TO_FP: {
const uint64_t zero[] = {0, 0};
// No compile time operations on this type.
- if (VT==MVT::ppcf128)
+ if (VT==EVT::ppcf128)
break;
APFloat apf = APFloat(APInt(BitWidth, 2, zero));
(void)apf.convertFromAPInt(Val,
@@ -2285,9 +2285,9 @@
return getConstantFP(apf, VT);
}
case ISD::BIT_CONVERT:
- if (VT == MVT::f32 && C->getValueType(0) == MVT::i32)
+ if (VT == EVT::f32 && C->getValueType(0) == EVT::i32)
return getConstantFP(Val.bitsToFloat(), VT);
- else if (VT == MVT::f64 && C->getValueType(0) == MVT::i64)
+ else if (VT == EVT::f64 && C->getValueType(0) == EVT::i64)
return getConstantFP(Val.bitsToDouble(), VT);
break;
case ISD::BSWAP:
@@ -2304,7 +2304,7 @@
// Constant fold unary operations with a floating point constant operand.
if (ConstantFPSDNode *C = dyn_cast<ConstantFPSDNode>(Operand.getNode())) {
APFloat V = C->getValueAPF(); // make copy
- if (VT != MVT::ppcf128 && Operand.getValueType() != MVT::ppcf128) {
+ if (VT != EVT::ppcf128 && Operand.getValueType() != EVT::ppcf128) {
switch (Opcode) {
case ISD::FNEG:
V.changeSign();
@@ -2317,7 +2317,7 @@
bool ignored;
// This can return overflow, underflow, or inexact; we don't care.
// FIXME need to be more flexible about rounding mode.
- (void)V.convert(*MVTToAPFloatSemantics(VT),
+ (void)V.convert(*EVTToAPFloatSemantics(VT),
APFloat::rmNearestTiesToEven, &ignored);
return getConstantFP(V, VT);
}
@@ -2336,9 +2336,9 @@
return getConstant(api, VT);
}
case ISD::BIT_CONVERT:
- if (VT == MVT::i32 && C->getValueType(0) == MVT::f32)
+ if (VT == EVT::i32 && C->getValueType(0) == EVT::f32)
return getConstant((uint32_t)V.bitcastToAPInt().getZExtValue(), VT);
- else if (VT == MVT::i64 && C->getValueType(0) == MVT::f64)
+ else if (VT == EVT::i64 && C->getValueType(0) == EVT::f64)
return getConstant(V.bitcastToAPInt().getZExtValue(), VT);
break;
}
@@ -2449,7 +2449,7 @@
SDNode *N;
SDVTList VTs = getVTList(VT);
- if (VT != MVT::Flag) { // Don't CSE flag producing nodes
+ if (VT != EVT::Flag) { // Don't CSE flag producing nodes
FoldingSetNodeID ID;
SDValue Ops[1] = { Operand };
AddNodeIDNode(ID, Opcode, VTs, Ops, 1);
@@ -2472,7 +2472,7 @@
}
SDValue SelectionDAG::FoldConstantArithmetic(unsigned Opcode,
- MVT VT,
+ EVT VT,
ConstantSDNode *Cst1,
ConstantSDNode *Cst2) {
const APInt &C1 = Cst1->getAPIntValue(), &C2 = Cst2->getAPIntValue();
@@ -2507,15 +2507,15 @@
return SDValue();
}
-SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
SDValue N1, SDValue N2) {
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
ConstantSDNode *N2C = dyn_cast<ConstantSDNode>(N2.getNode());
switch (Opcode) {
default: break;
case ISD::TokenFactor:
- assert(VT == MVT::Other && N1.getValueType() == MVT::Other &&
- N2.getValueType() == MVT::Other && "Invalid token factor!");
+ assert(VT == EVT::Other && N1.getValueType() == EVT::Other &&
+ N2.getValueType() == EVT::Other && "Invalid token factor!");
// Fold trivial token factors.
if (N1.getOpcode() == ISD::EntryToken) return N2;
if (N2.getOpcode() == ISD::EntryToken) return N1;
@@ -2605,11 +2605,11 @@
// Always fold shifts of i1 values so the code generator doesn't need to
// handle them. Since we know the size of the shift has to be less than the
// size of the value, the shift/rotate count is guaranteed to be zero.
- if (VT == MVT::i1)
+ if (VT == EVT::i1)
return N1;
break;
case ISD::FP_ROUND_INREG: {
- MVT EVT = cast<VTSDNode>(N2)->getVT();
+ EVT EVT = cast<VTSDNode>(N2)->getVT();
assert(VT == N1.getValueType() && "Not an inreg round!");
assert(VT.isFloatingPoint() && EVT.isFloatingPoint() &&
"Cannot FP_ROUND_INREG integer types");
@@ -2626,7 +2626,7 @@
break;
case ISD::AssertSext:
case ISD::AssertZext: {
- MVT EVT = cast<VTSDNode>(N2)->getVT();
+ EVT EVT = cast<VTSDNode>(N2)->getVT();
assert(VT == N1.getValueType() && "Not an inreg extend!");
assert(VT.isInteger() && EVT.isInteger() &&
"Cannot *_EXTEND_INREG FP types");
@@ -2635,7 +2635,7 @@
break;
}
case ISD::SIGN_EXTEND_INREG: {
- MVT EVT = cast<VTSDNode>(N2)->getVT();
+ EVT EVT = cast<VTSDNode>(N2)->getVT();
assert(VT == N1.getValueType() && "Not an inreg extend!");
assert(VT.isInteger() && EVT.isInteger() &&
"Cannot *_EXTEND_INREG FP types");
@@ -2673,7 +2673,7 @@
// expanding large vector constants.
if (N2C && N1.getOpcode() == ISD::BUILD_VECTOR) {
SDValue Elt = N1.getOperand(N2C->getZExtValue());
- MVT VEltTy = N1.getValueType().getVectorElementType();
+ EVT VEltTy = N1.getValueType().getVectorElementType();
if (Elt.getValueType() != VEltTy) {
// If the vector element type is not legal, the BUILD_VECTOR operands
// are promoted and implicitly truncated. Make that explicit here.
@@ -2746,7 +2746,7 @@
// Cannonicalize constant to RHS if commutative
std::swap(N1CFP, N2CFP);
std::swap(N1, N2);
- } else if (N2CFP && VT != MVT::ppcf128) {
+ } else if (N2CFP && VT != EVT::ppcf128) {
APFloat V1 = N1CFP->getValueAPF(), V2 = N2CFP->getValueAPF();
APFloat::opStatus s;
switch (Opcode) {
@@ -2861,7 +2861,7 @@
// Memoize this node if possible.
SDNode *N;
SDVTList VTs = getVTList(VT);
- if (VT != MVT::Flag) {
+ if (VT != EVT::Flag) {
SDValue Ops[] = { N1, N2 };
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTs, Ops, 2);
@@ -2883,7 +2883,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
SDValue N1, SDValue N2, SDValue N3) {
// Perform various simplifications.
ConstantSDNode *N1C = dyn_cast<ConstantSDNode>(N1.getNode());
@@ -2920,7 +2920,7 @@
case ISD::BRCOND:
if (N2C) {
if (N2C->getZExtValue()) // Unconditional branch
- return getNode(ISD::BR, DL, MVT::Other, N1, N3);
+ return getNode(ISD::BR, DL, EVT::Other, N1, N3);
else
return N1; // Never-taken branch
}
@@ -2938,7 +2938,7 @@
// Memoize node if it doesn't produce a flag.
SDNode *N;
SDVTList VTs = getVTList(VT);
- if (VT != MVT::Flag) {
+ if (VT != EVT::Flag) {
SDValue Ops[] = { N1, N2, N3 };
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTs, Ops, 3);
@@ -2959,14 +2959,14 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
SDValue N1, SDValue N2, SDValue N3,
SDValue N4) {
SDValue Ops[] = { N1, N2, N3, N4 };
return getNode(Opcode, DL, VT, Ops, 4);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
SDValue N1, SDValue N2, SDValue N3,
SDValue N4, SDValue N5) {
SDValue Ops[] = { N1, N2, N3, N4, N5 };
@@ -2992,13 +2992,13 @@
ArgChains.push_back(SDValue(L, 1));
// Build a tokenfactor for all the chains.
- return getNode(ISD::TokenFactor, Chain.getDebugLoc(), MVT::Other,
+ return getNode(ISD::TokenFactor, Chain.getDebugLoc(), EVT::Other,
&ArgChains[0], ArgChains.size());
}
/// getMemsetValue - Vectorized representation of the memset value
/// operand.
-static SDValue getMemsetValue(SDValue Value, MVT VT, SelectionDAG &DAG,
+static SDValue getMemsetValue(SDValue Value, EVT VT, SelectionDAG &DAG,
DebugLoc dl) {
unsigned NumBits = VT.isVector() ?
VT.getVectorElementType().getSizeInBits() : VT.getSizeInBits();
@@ -3032,7 +3032,7 @@
/// getMemsetStringVal - Similar to getMemsetValue. Except this is only
/// used when a memcpy is turned into a memset when the source is a constant
/// string ptr.
-static SDValue getMemsetStringVal(MVT VT, DebugLoc dl, SelectionDAG &DAG,
+static SDValue getMemsetStringVal(EVT VT, DebugLoc dl, SelectionDAG &DAG,
const TargetLowering &TLI,
std::string &Str, unsigned Offset) {
// Handle vector with all elements zero.
@@ -3040,9 +3040,9 @@
if (VT.isInteger())
return DAG.getConstant(0, VT);
unsigned NumElts = VT.getVectorNumElements();
- MVT EltVT = (VT.getVectorElementType() == MVT::f32) ? MVT::i32 : MVT::i64;
+ EVT EltVT = (VT.getVectorElementType() == EVT::f32) ? EVT::i32 : EVT::i64;
return DAG.getNode(ISD::BIT_CONVERT, dl, VT,
- DAG.getConstant(0, MVT::getVectorVT(EltVT, NumElts)));
+ DAG.getConstant(0, EVT::getVectorVT(EltVT, NumElts)));
}
assert(!VT.isVector() && "Can't handle vector type here!");
@@ -3062,7 +3062,7 @@
///
static SDValue getMemBasePlusOffset(SDValue Base, unsigned Offset,
SelectionDAG &DAG) {
- MVT VT = Base.getValueType();
+ EVT VT = Base.getValueType();
return DAG.getNode(ISD::ADD, Base.getDebugLoc(),
VT, Base, DAG.getConstant(Offset, VT));
}
@@ -3094,7 +3094,7 @@
/// to replace the memset / memcpy is below the threshold. It also returns the
/// types of the sequence of memory ops to perform memset / memcpy.
static
-bool MeetsMaxMemopRequirement(std::vector<MVT> &MemOps,
+bool MeetsMaxMemopRequirement(std::vector<EVT> &MemOps,
SDValue Dst, SDValue Src,
unsigned Limit, uint64_t Size, unsigned &Align,
std::string &Str, bool &isSrcStr,
@@ -3103,23 +3103,23 @@
isSrcStr = isMemSrcFromString(Src, Str);
bool isSrcConst = isa<ConstantSDNode>(Src);
bool AllowUnalign = TLI.allowsUnalignedMemoryAccesses();
- MVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr, DAG);
- if (VT != MVT::iAny) {
+ EVT VT = TLI.getOptimalMemOpType(Size, Align, isSrcConst, isSrcStr, DAG);
+ if (VT != EVT::iAny) {
unsigned NewAlign = (unsigned)
- TLI.getTargetData()->getABITypeAlignment(VT.getTypeForMVT());
+ TLI.getTargetData()->getABITypeAlignment(VT.getTypeForEVT());
// If source is a string constant, this will require an unaligned load.
if (NewAlign > Align && (isSrcConst || AllowUnalign)) {
if (Dst.getOpcode() != ISD::FrameIndex) {
// Can't change destination alignment. It requires a unaligned store.
if (AllowUnalign)
- VT = MVT::iAny;
+ VT = EVT::iAny;
} else {
int FI = cast<FrameIndexSDNode>(Dst)->getIndex();
MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
if (MFI->isFixedObjectIndex(FI)) {
// Can't change destination alignment. It requires a unaligned store.
if (AllowUnalign)
- VT = MVT::iAny;
+ VT = EVT::iAny;
} else {
// Give the stack frame object a larger alignment if needed.
if (MFI->getObjectAlignment(FI) < NewAlign)
@@ -3130,21 +3130,21 @@
}
}
- if (VT == MVT::iAny) {
+ if (VT == EVT::iAny) {
if (AllowUnalign) {
- VT = MVT::i64;
+ VT = EVT::i64;
} else {
switch (Align & 7) {
- case 0: VT = MVT::i64; break;
- case 4: VT = MVT::i32; break;
- case 2: VT = MVT::i16; break;
- default: VT = MVT::i8; break;
+ case 0: VT = EVT::i64; break;
+ case 4: VT = EVT::i32; break;
+ case 2: VT = EVT::i16; break;
+ default: VT = EVT::i8; break;
}
}
- MVT LVT = MVT::i64;
+ EVT LVT = EVT::i64;
while (!TLI.isTypeLegal(LVT))
- LVT = (MVT::SimpleValueType)(LVT.getSimpleVT() - 1);
+ LVT = (EVT::SimpleValueType)(LVT.getSimpleVT() - 1);
assert(LVT.isInteger());
if (VT.bitsGT(LVT))
@@ -3157,14 +3157,14 @@
while (VTSize > Size) {
// For now, only use non-vector load / store's for the left-over pieces.
if (VT.isVector()) {
- VT = MVT::i64;
+ VT = EVT::i64;
while (!TLI.isTypeLegal(VT))
- VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1);
+ VT = (EVT::SimpleValueType)(VT.getSimpleVT() - 1);
VTSize = VT.getSizeInBits() / 8;
} else {
// This can result in a type that is not legal on the target, e.g.
// 1 or 2 bytes on PPC.
- VT = (MVT::SimpleValueType)(VT.getSimpleVT() - 1);
+ VT = (EVT::SimpleValueType)(VT.getSimpleVT() - 1);
VTSize >>= 1;
}
}
@@ -3188,7 +3188,7 @@
// Expand memcpy to a series of load and store ops if the size operand falls
// below a certain threshold.
- std::vector<MVT> MemOps;
+ std::vector<EVT> MemOps;
uint64_t Limit = -1ULL;
if (!AlwaysInline)
Limit = TLI.getMaxStoresPerMemcpy();
@@ -3205,7 +3205,7 @@
unsigned NumMemOps = MemOps.size();
uint64_t SrcOff = 0, DstOff = 0;
for (unsigned i = 0; i < NumMemOps; i++) {
- MVT VT = MemOps[i];
+ EVT VT = MemOps[i];
unsigned VTSize = VT.getSizeInBits() / 8;
SDValue Value, Store;
@@ -3225,7 +3225,7 @@
// thing to do is generate a LoadExt/StoreTrunc pair. These simplify
// to Load/Store if NVT==VT.
// FIXME does the case above also need this?
- MVT NVT = TLI.getTypeToTransformTo(VT);
+ EVT NVT = TLI.getTypeToTransformTo(VT);
assert(NVT.bitsGE(VT));
Value = DAG.getExtLoad(ISD::EXTLOAD, dl, NVT, Chain,
getMemBasePlusOffset(Src, SrcOff, DAG),
@@ -3239,7 +3239,7 @@
DstOff += VTSize;
}
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&OutChains[0], OutChains.size());
}
@@ -3253,7 +3253,7 @@
// Expand memmove to a series of load and store ops if the size operand falls
// below a certain threshold.
- std::vector<MVT> MemOps;
+ std::vector<EVT> MemOps;
uint64_t Limit = -1ULL;
if (!AlwaysInline)
Limit = TLI.getMaxStoresPerMemmove();
@@ -3271,7 +3271,7 @@
SmallVector<SDValue, 8> OutChains;
unsigned NumMemOps = MemOps.size();
for (unsigned i = 0; i < NumMemOps; i++) {
- MVT VT = MemOps[i];
+ EVT VT = MemOps[i];
unsigned VTSize = VT.getSizeInBits() / 8;
SDValue Value, Store;
@@ -3282,11 +3282,11 @@
LoadChains.push_back(Value.getValue(1));
SrcOff += VTSize;
}
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&LoadChains[0], LoadChains.size());
OutChains.clear();
for (unsigned i = 0; i < NumMemOps; i++) {
- MVT VT = MemOps[i];
+ EVT VT = MemOps[i];
unsigned VTSize = VT.getSizeInBits() / 8;
SDValue Value, Store;
@@ -3297,7 +3297,7 @@
DstOff += VTSize;
}
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&OutChains[0], OutChains.size());
}
@@ -3310,7 +3310,7 @@
// Expand memset to a series of load/store ops if the size operand
// falls below a certain threshold.
- std::vector<MVT> MemOps;
+ std::vector<EVT> MemOps;
std::string Str;
bool CopyFromStr;
if (!MeetsMaxMemopRequirement(MemOps, Dst, Src, TLI.getMaxStoresPerMemset(),
@@ -3322,7 +3322,7 @@
unsigned NumMemOps = MemOps.size();
for (unsigned i = 0; i < NumMemOps; i++) {
- MVT VT = MemOps[i];
+ EVT VT = MemOps[i];
unsigned VTSize = VT.getSizeInBits() / 8;
SDValue Value = getMemsetValue(Src, VT, DAG, dl);
SDValue Store = DAG.getStore(Chain, dl, Value,
@@ -3332,7 +3332,7 @@
DstOff += VTSize;
}
- return DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
+ return DAG.getNode(ISD::TokenFactor, dl, EVT::Other,
&OutChains[0], OutChains.size());
}
@@ -3477,10 +3477,10 @@
Entry.Node = Dst; Entry.Ty = IntPtrTy;
Args.push_back(Entry);
// Extend or truncate the argument to be an i32 value for the call.
- if (Src.getValueType().bitsGT(MVT::i32))
- Src = getNode(ISD::TRUNCATE, dl, MVT::i32, Src);
+ if (Src.getValueType().bitsGT(EVT::i32))
+ Src = getNode(ISD::TRUNCATE, dl, EVT::i32, Src);
else
- Src = getNode(ISD::ZERO_EXTEND, dl, MVT::i32, Src);
+ Src = getNode(ISD::ZERO_EXTEND, dl, EVT::i32, Src);
Entry.Node = Src; Entry.Ty = Type::Int32Ty; Entry.isSExt = true;
Args.push_back(Entry);
Entry.Node = Size; Entry.Ty = IntPtrTy; Entry.isSExt = false;
@@ -3496,7 +3496,7 @@
return CallResult.second;
}
-SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
+SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
SDValue Chain,
SDValue Ptr, SDValue Cmp,
SDValue Swp, const Value* PtrVal,
@@ -3504,12 +3504,12 @@
assert(Opcode == ISD::ATOMIC_CMP_SWAP && "Invalid Atomic Op");
assert(Cmp.getValueType() == Swp.getValueType() && "Invalid Atomic Op Types");
- MVT VT = Cmp.getValueType();
+ EVT VT = Cmp.getValueType();
if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getMVTAlignment(MemVT);
+ Alignment = getEVTAlignment(MemVT);
- SDVTList VTs = getVTList(VT, MVT::Other);
+ SDVTList VTs = getVTList(VT, EVT::Other);
FoldingSetNodeID ID;
ID.AddInteger(MemVT.getRawBits());
SDValue Ops[] = {Chain, Ptr, Cmp, Swp};
@@ -3525,7 +3525,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, MVT MemVT,
+SDValue SelectionDAG::getAtomic(unsigned Opcode, DebugLoc dl, EVT MemVT,
SDValue Chain,
SDValue Ptr, SDValue Val,
const Value* PtrVal,
@@ -3543,12 +3543,12 @@
Opcode == ISD::ATOMIC_SWAP) &&
"Invalid Atomic Op");
- MVT VT = Val.getValueType();
+ EVT VT = Val.getValueType();
if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getMVTAlignment(MemVT);
+ Alignment = getEVTAlignment(MemVT);
- SDVTList VTs = getVTList(VT, MVT::Other);
+ SDVTList VTs = getVTList(VT, EVT::Other);
FoldingSetNodeID ID;
ID.AddInteger(MemVT.getRawBits());
SDValue Ops[] = {Chain, Ptr, Val};
@@ -3571,7 +3571,7 @@
if (NumOps == 1)
return Ops[0];
- SmallVector<MVT, 4> VTs;
+ SmallVector<EVT, 4> VTs;
VTs.reserve(NumOps);
for (unsigned i = 0; i < NumOps; ++i)
VTs.push_back(Ops[i].getValueType());
@@ -3581,9 +3581,9 @@
SDValue
SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl,
- const MVT *VTs, unsigned NumVTs,
+ const EVT *VTs, unsigned NumVTs,
const SDValue *Ops, unsigned NumOps,
- MVT MemVT, const Value *srcValue, int SVOff,
+ EVT MemVT, const Value *srcValue, int SVOff,
unsigned Align, bool Vol,
bool ReadMem, bool WriteMem) {
return getMemIntrinsicNode(Opcode, dl, makeVTList(VTs, NumVTs), Ops, NumOps,
@@ -3594,12 +3594,12 @@
SDValue
SelectionDAG::getMemIntrinsicNode(unsigned Opcode, DebugLoc dl, SDVTList VTList,
const SDValue *Ops, unsigned NumOps,
- MVT MemVT, const Value *srcValue, int SVOff,
+ EVT MemVT, const Value *srcValue, int SVOff,
unsigned Align, bool Vol,
bool ReadMem, bool WriteMem) {
// Memoize the node unless it returns a flag.
MemIntrinsicSDNode *N;
- if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
+ if (VTList.VTs[VTList.NumVTs-1] != EVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
void *IP = 0;
@@ -3621,12 +3621,12 @@
SDValue
SelectionDAG::getLoad(ISD::MemIndexedMode AM, DebugLoc dl,
- ISD::LoadExtType ExtType, MVT VT, SDValue Chain,
+ ISD::LoadExtType ExtType, EVT VT, SDValue Chain,
SDValue Ptr, SDValue Offset,
- const Value *SV, int SVOffset, MVT EVT,
+ const Value *SV, int SVOffset, EVT EVT,
bool isVolatile, unsigned Alignment) {
if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getMVTAlignment(VT);
+ Alignment = getEVTAlignment(VT);
if (VT == EVT) {
ExtType = ISD::NON_EXTLOAD;
@@ -3651,7 +3651,7 @@
"Unindexed load with an offset!");
SDVTList VTs = Indexed ?
- getVTList(VT, Ptr.getValueType(), MVT::Other) : getVTList(VT, MVT::Other);
+ getVTList(VT, Ptr.getValueType(), EVT::Other) : getVTList(VT, EVT::Other);
SDValue Ops[] = { Chain, Ptr, Offset };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::LOAD, VTs, Ops, 3);
@@ -3668,7 +3668,7 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getLoad(MVT VT, DebugLoc dl,
+SDValue SelectionDAG::getLoad(EVT VT, DebugLoc dl,
SDValue Chain, SDValue Ptr,
const Value *SV, int SVOffset,
bool isVolatile, unsigned Alignment) {
@@ -3677,10 +3677,10 @@
SV, SVOffset, VT, isVolatile, Alignment);
}
-SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, MVT VT,
+SDValue SelectionDAG::getExtLoad(ISD::LoadExtType ExtType, DebugLoc dl, EVT VT,
SDValue Chain, SDValue Ptr,
const Value *SV,
- int SVOffset, MVT EVT,
+ int SVOffset, EVT EVT,
bool isVolatile, unsigned Alignment) {
SDValue Undef = getUNDEF(Ptr.getValueType());
return getLoad(ISD::UNINDEXED, dl, ExtType, VT, Chain, Ptr, Undef,
@@ -3702,12 +3702,12 @@
SDValue SelectionDAG::getStore(SDValue Chain, DebugLoc dl, SDValue Val,
SDValue Ptr, const Value *SV, int SVOffset,
bool isVolatile, unsigned Alignment) {
- MVT VT = Val.getValueType();
+ EVT VT = Val.getValueType();
if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getMVTAlignment(VT);
+ Alignment = getEVTAlignment(VT);
- SDVTList VTs = getVTList(MVT::Other);
+ SDVTList VTs = getVTList(EVT::Other);
SDValue Undef = getUNDEF(Ptr.getValueType());
SDValue Ops[] = { Chain, Val, Ptr, Undef };
FoldingSetNodeID ID;
@@ -3728,9 +3728,9 @@
SDValue SelectionDAG::getTruncStore(SDValue Chain, DebugLoc dl, SDValue Val,
SDValue Ptr, const Value *SV,
- int SVOffset, MVT SVT,
+ int SVOffset, EVT SVT,
bool isVolatile, unsigned Alignment) {
- MVT VT = Val.getValueType();
+ EVT VT = Val.getValueType();
if (VT == SVT)
return getStore(Chain, dl, Val, Ptr, SV, SVOffset, isVolatile, Alignment);
@@ -3740,9 +3740,9 @@
"Can't do FP-INT conversion!");
if (Alignment == 0) // Ensure that codegen never sees alignment 0
- Alignment = getMVTAlignment(VT);
+ Alignment = getEVTAlignment(VT);
- SDVTList VTs = getVTList(MVT::Other);
+ SDVTList VTs = getVTList(EVT::Other);
SDValue Undef = getUNDEF(Ptr.getValueType());
SDValue Ops[] = { Chain, Val, Ptr, Undef };
FoldingSetNodeID ID;
@@ -3767,7 +3767,7 @@
StoreSDNode *ST = cast<StoreSDNode>(OrigStore);
assert(ST->getOffset().getOpcode() == ISD::UNDEF &&
"Store is already a indexed store!");
- SDVTList VTs = getVTList(Base.getValueType(), MVT::Other);
+ SDVTList VTs = getVTList(Base.getValueType(), EVT::Other);
SDValue Ops[] = { ST->getChain(), ST->getValue(), Base, Offset };
FoldingSetNodeID ID;
AddNodeIDNode(ID, ISD::STORE, VTs, Ops, 4);
@@ -3786,14 +3786,14 @@
return SDValue(N, 0);
}
-SDValue SelectionDAG::getVAArg(MVT VT, DebugLoc dl,
+SDValue SelectionDAG::getVAArg(EVT VT, DebugLoc dl,
SDValue Chain, SDValue Ptr,
SDValue SV) {
SDValue Ops[] = { Chain, Ptr, SV };
- return getNode(ISD::VAARG, dl, getVTList(VT, MVT::Other), Ops, 3);
+ return getNode(ISD::VAARG, dl, getVTList(VT, EVT::Other), Ops, 3);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
const SDUse *Ops, unsigned NumOps) {
switch (NumOps) {
case 0: return getNode(Opcode, DL, VT);
@@ -3809,7 +3809,7 @@
return getNode(Opcode, DL, VT, &NewOps[0], NumOps);
}
-SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, MVT VT,
+SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL, EVT VT,
const SDValue *Ops, unsigned NumOps) {
switch (NumOps) {
case 0: return getNode(Opcode, DL, VT);
@@ -3843,7 +3843,7 @@
SDNode *N;
SDVTList VTs = getVTList(VT);
- if (VT != MVT::Flag) {
+ if (VT != EVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTs, Ops, NumOps);
void *IP = 0;
@@ -3867,14 +3867,14 @@
}
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
- const std::vector<MVT> &ResultTys,
+ const std::vector<EVT> &ResultTys,
const SDValue *Ops, unsigned NumOps) {
return getNode(Opcode, DL, getVTList(&ResultTys[0], ResultTys.size()),
Ops, NumOps);
}
SDValue SelectionDAG::getNode(unsigned Opcode, DebugLoc DL,
- const MVT *VTs, unsigned NumVTs,
+ const EVT *VTs, unsigned NumVTs,
const SDValue *Ops, unsigned NumOps) {
if (NumVTs == 1)
return getNode(Opcode, DL, VTs[0], Ops, NumOps);
@@ -3895,7 +3895,7 @@
case ISD::SRL_PARTS:
case ISD::SHL_PARTS:
if (N3.getOpcode() == ISD::SIGN_EXTEND_INREG &&
- cast<VTSDNode>(N3.getOperand(1))->getVT() != MVT::i1)
+ cast<VTSDNode>(N3.getOperand(1))->getVT() != EVT::i1)
return getNode(Opcode, DL, VT, N1, N2, N3.getOperand(0));
else if (N3.getOpcode() == ISD::AND)
if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(N3.getOperand(1))) {
@@ -3911,7 +3911,7 @@
// Memoize the node unless it returns a flag.
SDNode *N;
- if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
+ if (VTList.VTs[VTList.NumVTs-1] != EVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
void *IP = 0;
@@ -3989,17 +3989,17 @@
return getNode(Opcode, DL, VTList, Ops, 5);
}
-SDVTList SelectionDAG::getVTList(MVT VT) {
+SDVTList SelectionDAG::getVTList(EVT VT) {
return makeVTList(SDNode::getValueTypeList(VT), 1);
}
-SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2) {
+SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2) {
for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
E = VTList.rend(); I != E; ++I)
if (I->NumVTs == 2 && I->VTs[0] == VT1 && I->VTs[1] == VT2)
return *I;
- MVT *Array = Allocator.Allocate<MVT>(2);
+ EVT *Array = Allocator.Allocate<EVT>(2);
Array[0] = VT1;
Array[1] = VT2;
SDVTList Result = makeVTList(Array, 2);
@@ -4007,14 +4007,14 @@
return Result;
}
-SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3) {
+SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2, EVT VT3) {
for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
E = VTList.rend(); I != E; ++I)
if (I->NumVTs == 3 && I->VTs[0] == VT1 && I->VTs[1] == VT2 &&
I->VTs[2] == VT3)
return *I;
- MVT *Array = Allocator.Allocate<MVT>(3);
+ EVT *Array = Allocator.Allocate<EVT>(3);
Array[0] = VT1;
Array[1] = VT2;
Array[2] = VT3;
@@ -4023,14 +4023,14 @@
return Result;
}
-SDVTList SelectionDAG::getVTList(MVT VT1, MVT VT2, MVT VT3, MVT VT4) {
+SDVTList SelectionDAG::getVTList(EVT VT1, EVT VT2, EVT VT3, EVT VT4) {
for (std::vector<SDVTList>::reverse_iterator I = VTList.rbegin(),
E = VTList.rend(); I != E; ++I)
if (I->NumVTs == 4 && I->VTs[0] == VT1 && I->VTs[1] == VT2 &&
I->VTs[2] == VT3 && I->VTs[3] == VT4)
return *I;
- MVT *Array = Allocator.Allocate<MVT>(3);
+ EVT *Array = Allocator.Allocate<EVT>(3);
Array[0] = VT1;
Array[1] = VT2;
Array[2] = VT3;
@@ -4040,7 +4040,7 @@
return Result;
}
-SDVTList SelectionDAG::getVTList(const MVT *VTs, unsigned NumVTs) {
+SDVTList SelectionDAG::getVTList(const EVT *VTs, unsigned NumVTs) {
switch (NumVTs) {
case 0: llvm_unreachable("Cannot have nodes without results!");
case 1: return getVTList(VTs[0]);
@@ -4064,7 +4064,7 @@
return *I;
}
- MVT *Array = Allocator.Allocate<MVT>(NumVTs);
+ EVT *Array = Allocator.Allocate<EVT>(NumVTs);
std::copy(VTs, VTs+NumVTs, Array);
SDVTList Result = makeVTList(Array, NumVTs);
VTList.push_back(Result);
@@ -4206,20 +4206,20 @@
/// machine opcode.
///
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT) {
+ EVT VT) {
SDVTList VTs = getVTList(VT);
return SelectNodeTo(N, MachineOpc, VTs, 0, 0);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT, SDValue Op1) {
+ EVT VT, SDValue Op1) {
SDVTList VTs = getVTList(VT);
SDValue Ops[] = { Op1 };
return SelectNodeTo(N, MachineOpc, VTs, Ops, 1);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT, SDValue Op1,
+ EVT VT, SDValue Op1,
SDValue Op2) {
SDVTList VTs = getVTList(VT);
SDValue Ops[] = { Op1, Op2 };
@@ -4227,7 +4227,7 @@
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT, SDValue Op1,
+ EVT VT, SDValue Op1,
SDValue Op2, SDValue Op3) {
SDVTList VTs = getVTList(VT);
SDValue Ops[] = { Op1, Op2, Op3 };
@@ -4235,41 +4235,41 @@
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT, const SDValue *Ops,
+ EVT VT, const SDValue *Ops,
unsigned NumOps) {
SDVTList VTs = getVTList(VT);
return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT1, MVT VT2, const SDValue *Ops,
+ EVT VT1, EVT VT2, const SDValue *Ops,
unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2);
return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT1, MVT VT2) {
+ EVT VT1, EVT VT2) {
SDVTList VTs = getVTList(VT1, VT2);
return SelectNodeTo(N, MachineOpc, VTs, (SDValue *)0, 0);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT1, MVT VT2, MVT VT3,
+ EVT VT1, EVT VT2, EVT VT3,
const SDValue *Ops, unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT1, MVT VT2, MVT VT3, MVT VT4,
+ EVT VT1, EVT VT2, EVT VT3, EVT VT4,
const SDValue *Ops, unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2, VT3, VT4);
return SelectNodeTo(N, MachineOpc, VTs, Ops, NumOps);
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT1, MVT VT2,
+ EVT VT1, EVT VT2,
SDValue Op1) {
SDVTList VTs = getVTList(VT1, VT2);
SDValue Ops[] = { Op1 };
@@ -4277,7 +4277,7 @@
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT1, MVT VT2,
+ EVT VT1, EVT VT2,
SDValue Op1, SDValue Op2) {
SDVTList VTs = getVTList(VT1, VT2);
SDValue Ops[] = { Op1, Op2 };
@@ -4285,7 +4285,7 @@
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT1, MVT VT2,
+ EVT VT1, EVT VT2,
SDValue Op1, SDValue Op2,
SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2);
@@ -4294,7 +4294,7 @@
}
SDNode *SelectionDAG::SelectNodeTo(SDNode *N, unsigned MachineOpc,
- MVT VT1, MVT VT2, MVT VT3,
+ EVT VT1, EVT VT2, EVT VT3,
SDValue Op1, SDValue Op2,
SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
@@ -4309,20 +4309,20 @@
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT) {
+ EVT VT) {
SDVTList VTs = getVTList(VT);
return MorphNodeTo(N, Opc, VTs, 0, 0);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT, SDValue Op1) {
+ EVT VT, SDValue Op1) {
SDVTList VTs = getVTList(VT);
SDValue Ops[] = { Op1 };
return MorphNodeTo(N, Opc, VTs, Ops, 1);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT, SDValue Op1,
+ EVT VT, SDValue Op1,
SDValue Op2) {
SDVTList VTs = getVTList(VT);
SDValue Ops[] = { Op1, Op2 };
@@ -4330,7 +4330,7 @@
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT, SDValue Op1,
+ EVT VT, SDValue Op1,
SDValue Op2, SDValue Op3) {
SDVTList VTs = getVTList(VT);
SDValue Ops[] = { Op1, Op2, Op3 };
@@ -4338,34 +4338,34 @@
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT, const SDValue *Ops,
+ EVT VT, const SDValue *Ops,
unsigned NumOps) {
SDVTList VTs = getVTList(VT);
return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT1, MVT VT2, const SDValue *Ops,
+ EVT VT1, EVT VT2, const SDValue *Ops,
unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2);
return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT1, MVT VT2) {
+ EVT VT1, EVT VT2) {
SDVTList VTs = getVTList(VT1, VT2);
return MorphNodeTo(N, Opc, VTs, (SDValue *)0, 0);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT1, MVT VT2, MVT VT3,
+ EVT VT1, EVT VT2, EVT VT3,
const SDValue *Ops, unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
return MorphNodeTo(N, Opc, VTs, Ops, NumOps);
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT1, MVT VT2,
+ EVT VT1, EVT VT2,
SDValue Op1) {
SDVTList VTs = getVTList(VT1, VT2);
SDValue Ops[] = { Op1 };
@@ -4373,7 +4373,7 @@
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT1, MVT VT2,
+ EVT VT1, EVT VT2,
SDValue Op1, SDValue Op2) {
SDVTList VTs = getVTList(VT1, VT2);
SDValue Ops[] = { Op1, Op2 };
@@ -4381,7 +4381,7 @@
}
SDNode *SelectionDAG::MorphNodeTo(SDNode *N, unsigned Opc,
- MVT VT1, MVT VT2,
+ EVT VT1, EVT VT2,
SDValue Op1, SDValue Op2,
SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2);
@@ -4406,7 +4406,7 @@
unsigned NumOps) {
// If an identical node already exists, use it.
void *IP = 0;
- if (VTs.VTs[VTs.NumVTs-1] != MVT::Flag) {
+ if (VTs.VTs[VTs.NumVTs-1] != EVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opc, VTs, Ops, NumOps);
if (SDNode *ON = CSEMap.FindNodeOrInsertPos(ID, IP))
@@ -4478,54 +4478,54 @@
/// Note that getTargetNode returns the resultant node. If there is already a
/// node of the specified opcode and operands, it returns that node instead of
/// the current one.
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT) {
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT) {
return getNode(~Opcode, dl, VT).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT,
SDValue Op1) {
return getNode(~Opcode, dl, VT, Op1).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT,
SDValue Op1, SDValue Op2) {
return getNode(~Opcode, dl, VT, Op1, Op2).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT,
SDValue Op1, SDValue Op2,
SDValue Op3) {
return getNode(~Opcode, dl, VT, Op1, Op2, Op3).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT,
const SDValue *Ops, unsigned NumOps) {
return getNode(~Opcode, dl, VT, Ops, NumOps).getNode();
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
- MVT VT1, MVT VT2) {
+ EVT VT1, EVT VT2) {
SDVTList VTs = getVTList(VT1, VT2);
SDValue Op;
return getNode(~Opcode, dl, VTs, &Op, 0).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
- MVT VT2, SDValue Op1) {
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1,
+ EVT VT2, SDValue Op1) {
SDVTList VTs = getVTList(VT1, VT2);
return getNode(~Opcode, dl, VTs, &Op1, 1).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
- MVT VT2, SDValue Op1,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1,
+ EVT VT2, SDValue Op1,
SDValue Op2) {
SDVTList VTs = getVTList(VT1, VT2);
SDValue Ops[] = { Op1, Op2 };
return getNode(~Opcode, dl, VTs, Ops, 2).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
- MVT VT2, SDValue Op1,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1,
+ EVT VT2, SDValue Op1,
SDValue Op2, SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2);
SDValue Ops[] = { Op1, Op2, Op3 };
@@ -4533,14 +4533,14 @@
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
- MVT VT1, MVT VT2,
+ EVT VT1, EVT VT2,
const SDValue *Ops, unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2);
return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
- MVT VT1, MVT VT2, MVT VT3,
+ EVT VT1, EVT VT2, EVT VT3,
SDValue Op1, SDValue Op2) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
SDValue Ops[] = { Op1, Op2 };
@@ -4548,7 +4548,7 @@
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
- MVT VT1, MVT VT2, MVT VT3,
+ EVT VT1, EVT VT2, EVT VT3,
SDValue Op1, SDValue Op2,
SDValue Op3) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
@@ -4557,21 +4557,21 @@
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
- MVT VT1, MVT VT2, MVT VT3,
+ EVT VT1, EVT VT2, EVT VT3,
const SDValue *Ops, unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2, VT3);
return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
}
-SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, MVT VT1,
- MVT VT2, MVT VT3, MVT VT4,
+SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl, EVT VT1,
+ EVT VT2, EVT VT3, EVT VT4,
const SDValue *Ops, unsigned NumOps) {
SDVTList VTs = getVTList(VT1, VT2, VT3, VT4);
return getNode(~Opcode, dl, VTs, Ops, NumOps).getNode();
}
SDNode *SelectionDAG::getTargetNode(unsigned Opcode, DebugLoc dl,
- const std::vector<MVT> &ResultTys,
+ const std::vector<EVT> &ResultTys,
const SDValue *Ops, unsigned NumOps) {
return getNode(~Opcode, dl, ResultTys, Ops, NumOps).getNode();
}
@@ -4580,7 +4580,7 @@
/// else return NULL.
SDNode *SelectionDAG::getNodeIfExists(unsigned Opcode, SDVTList VTList,
const SDValue *Ops, unsigned NumOps) {
- if (VTList.VTs[VTList.NumVTs-1] != MVT::Flag) {
+ if (VTList.VTs[VTList.NumVTs-1] != EVT::Flag) {
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opcode, VTList, Ops, NumOps);
void *IP = 0;
@@ -4928,13 +4928,13 @@
}
GlobalAddressSDNode::GlobalAddressSDNode(unsigned Opc, const GlobalValue *GA,
- MVT VT, int64_t o, unsigned char TF)
+ EVT VT, int64_t o, unsigned char TF)
: SDNode(Opc, DebugLoc::getUnknownLoc(), getSDVTList(VT)),
Offset(o), TargetFlags(TF) {
TheGlobal = const_cast<GlobalValue*>(GA);
}
-MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, MVT memvt,
+MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs, EVT memvt,
const Value *srcValue, int SVO,
unsigned alignment, bool vol)
: SDNode(Opc, dl, VTs), MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) {
@@ -4946,7 +4946,7 @@
MemSDNode::MemSDNode(unsigned Opc, DebugLoc dl, SDVTList VTs,
const SDValue *Ops,
- unsigned NumOps, MVT memvt, const Value *srcValue,
+ unsigned NumOps, EVT memvt, const Value *srcValue,
int SVO, unsigned alignment, bool vol)
: SDNode(Opc, dl, VTs, Ops, NumOps),
MemoryVT(memvt), SrcValue(srcValue), SVOffset(SVO) {
@@ -4994,13 +4994,13 @@
AddNodeIDNode(ID, this);
}
-static ManagedStatic<std::set<MVT, MVT::compareRawBits> > EVTs;
-static MVT VTs[MVT::LAST_VALUETYPE];
+static ManagedStatic<std::set<EVT, EVT::compareRawBits> > EVTs;
+static EVT VTs[EVT::LAST_VALUETYPE];
static ManagedStatic<sys::SmartMutex<true> > VTMutex;
/// getValueTypeList - Return a pointer to the specified value type.
///
-const MVT *SDNode::getValueTypeList(MVT VT) {
+const EVT *SDNode::getValueTypeList(EVT VT) {
sys::SmartScopedLock<true> Lock(*VTMutex);
if (VT.isExtended()) {
return &(*EVTs->insert(VT).first);
@@ -5447,10 +5447,10 @@
for (unsigned i = 0, e = getNumValues(); i != e; ++i) {
if (i) OS << ",";
- if (getValueType(i) == MVT::Other)
+ if (getValueType(i) == EVT::Other)
OS << "ch";
else
- OS << getValueType(i).getMVTString();
+ OS << getValueType(i).getEVTString();
}
OS << " = " << getOperationName(G);
}
@@ -5541,7 +5541,7 @@
else
OS << "<null:" << M->MO.getOffset() << ">";
} else if (const VTSDNode *N = dyn_cast<VTSDNode>(this)) {
- OS << ":" << N->getVT().getMVTString();
+ OS << ":" << N->getVT().getEVTString();
}
else if (const LoadSDNode *LD = dyn_cast<LoadSDNode>(this)) {
const Value *SrcValue = LD->getSrcValue();
@@ -5561,7 +5561,7 @@
case ISD::ZEXTLOAD: OS << " <zext "; break;
}
if (doExt)
- OS << LD->getMemoryVT().getMVTString() << ">";
+ OS << LD->getMemoryVT().getEVTString() << ">";
const char *AM = getIndexedModeName(LD->getAddressingMode());
if (*AM)
@@ -5580,7 +5580,7 @@
OS << ":" << SrcOffset << ">";
if (ST->isTruncatingStore())
- OS << " <trunc " << ST->getMemoryVT().getMVTString() << ">";
+ OS << " <trunc " << ST->getMemoryVT().getEVTString() << ">";
const char *AM = getIndexedModeName(ST->getAddressingMode());
if (*AM)
@@ -5702,7 +5702,7 @@
unsigned &SplatBitSize,
bool &HasAnyUndefs,
unsigned MinSplatBits) {
- MVT VT = getValueType(0);
+ EVT VT = getValueType(0);
assert(VT.isVector() && "Expected a vector type");
unsigned sz = VT.getSizeInBits();
if (MinSplatBits > sz)
@@ -5760,7 +5760,7 @@
return true;
}
-bool ShuffleVectorSDNode::isSplatMask(const int *Mask, MVT VT) {
+bool ShuffleVectorSDNode::isSplatMask(const int *Mask, EVT VT) {
// Find the first non-undef value in the shuffle mask.
unsigned i, e;
for (i = 0, e = VT.getVectorNumElements(); i != e && Mask[i] < 0; ++i)
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
index 929740d..0180069 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp
@@ -106,14 +106,14 @@
}
/// ComputeValueVTs - Given an LLVM IR type, compute a sequence of
-/// MVTs that represent all the individual underlying
+/// EVTs that represent all the individual underlying
/// non-aggregate types that comprise it.
///
/// If Offsets is non-null, it points to a vector to be filled in
/// with the in-memory offsets of each of the individual values.
///
static void ComputeValueVTs(const TargetLowering &TLI, const Type *Ty,
- SmallVectorImpl<MVT> &ValueVTs,
+ SmallVectorImpl<EVT> &ValueVTs,
SmallVectorImpl<uint64_t> *Offsets = 0,
uint64_t StartingOffset = 0) {
// Given a struct type, recursively traverse the elements.
@@ -139,7 +139,7 @@
// Interpret void as zero return values.
if (Ty == Type::VoidTy)
return;
- // Base case: we can get an MVT for this LLVM IR type.
+ // Base case: we can get an EVT for this LLVM IR type.
ValueVTs.push_back(TLI.getValueType(Ty));
if (Offsets)
Offsets->push_back(StartingOffset);
@@ -163,7 +163,7 @@
/// ValueVTs - The value types of the values, which may not be legal, and
/// may need be promoted or synthesized from one or more registers.
///
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
/// RegVTs - The value types of the registers. This is the same size as
/// ValueVTs and it records, for each value, what the type of the assigned
@@ -174,7 +174,7 @@
/// getRegisterType member function, however when with physical registers
/// it is necessary to have a separate record of the types.
///
- SmallVector<MVT, 4> RegVTs;
+ SmallVector<EVT, 4> RegVTs;
/// Regs - This list holds the registers assigned to the values.
/// Each legal or promoted value requires one register, and each
@@ -186,21 +186,21 @@
RegsForValue(const TargetLowering &tli,
const SmallVector<unsigned, 4> ®s,
- MVT regvt, MVT valuevt)
+ EVT regvt, EVT valuevt)
: TLI(&tli), ValueVTs(1, valuevt), RegVTs(1, regvt), Regs(regs) {}
RegsForValue(const TargetLowering &tli,
const SmallVector<unsigned, 4> ®s,
- const SmallVector<MVT, 4> ®vts,
- const SmallVector<MVT, 4> &valuevts)
+ const SmallVector<EVT, 4> ®vts,
+ const SmallVector<EVT, 4> &valuevts)
: TLI(&tli), ValueVTs(valuevts), RegVTs(regvts), Regs(regs) {}
RegsForValue(const TargetLowering &tli,
unsigned Reg, const Type *Ty) : TLI(&tli) {
ComputeValueVTs(tli, Ty, ValueVTs);
for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
- MVT ValueVT = ValueVTs[Value];
+ EVT ValueVT = ValueVTs[Value];
unsigned NumRegs = TLI->getNumRegisters(ValueVT);
- MVT RegisterVT = TLI->getRegisterType(ValueVT);
+ EVT RegisterVT = TLI->getRegisterType(ValueVT);
for (unsigned i = 0; i != NumRegs; ++i)
Regs.push_back(Reg + i);
RegVTs.push_back(RegisterVT);
@@ -354,10 +354,10 @@
unsigned PHIReg = ValueMap[PN];
assert(PHIReg && "PHI node does not have an assigned virtual register!");
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, PN->getType(), ValueVTs);
for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
- MVT VT = ValueVTs[vti];
+ EVT VT = ValueVTs[vti];
unsigned NumRegisters = TLI.getNumRegisters(VT);
const TargetInstrInfo *TII = MF->getTarget().getInstrInfo();
for (unsigned i = 0; i != NumRegisters; ++i)
@@ -368,7 +368,7 @@
}
}
-unsigned FunctionLoweringInfo::MakeReg(MVT VT) {
+unsigned FunctionLoweringInfo::MakeReg(EVT VT) {
return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
}
@@ -380,13 +380,13 @@
/// will assign registers for each member or element.
///
unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) {
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, V->getType(), ValueVTs);
unsigned FirstReg = 0;
for (unsigned Value = 0, e = ValueVTs.size(); Value != e; ++Value) {
- MVT ValueVT = ValueVTs[Value];
- MVT RegisterVT = TLI.getRegisterType(ValueVT);
+ EVT ValueVT = ValueVTs[Value];
+ EVT RegisterVT = TLI.getRegisterType(ValueVT);
unsigned NumRegs = TLI.getNumRegisters(ValueVT);
for (unsigned i = 0; i != NumRegs; ++i) {
@@ -404,7 +404,7 @@
/// (ISD::AssertSext).
static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl,
const SDValue *Parts,
- unsigned NumParts, MVT PartVT, MVT ValueVT,
+ unsigned NumParts, EVT PartVT, EVT ValueVT,
ISD::NodeType AssertOp = ISD::DELETED_NODE) {
assert(NumParts > 0 && "No parts to assemble!");
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
@@ -420,11 +420,11 @@
unsigned RoundParts = NumParts & (NumParts - 1) ?
1 << Log2_32(NumParts) : NumParts;
unsigned RoundBits = PartBits * RoundParts;
- MVT RoundVT = RoundBits == ValueBits ?
- ValueVT : MVT::getIntegerVT(RoundBits);
+ EVT RoundVT = RoundBits == ValueBits ?
+ ValueVT : EVT::getIntegerVT(RoundBits);
SDValue Lo, Hi;
- MVT HalfVT = MVT::getIntegerVT(RoundBits/2);
+ EVT HalfVT = EVT::getIntegerVT(RoundBits/2);
if (RoundParts > 2) {
Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT);
@@ -441,7 +441,7 @@
if (RoundParts < NumParts) {
// Assemble the trailing non-power-of-2 part.
unsigned OddParts = NumParts - RoundParts;
- MVT OddVT = MVT::getIntegerVT(OddParts * PartBits);
+ EVT OddVT = EVT::getIntegerVT(OddParts * PartBits);
Hi = getCopyFromParts(DAG, dl,
Parts+RoundParts, OddParts, PartVT, OddVT);
@@ -449,7 +449,7 @@
Lo = Val;
if (TLI.isBigEndian())
std::swap(Lo, Hi);
- MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits);
+ EVT TotalVT = EVT::getIntegerVT(NumParts * PartBits);
Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi);
Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi,
DAG.getConstant(Lo.getValueType().getSizeInBits(),
@@ -459,7 +459,7 @@
}
} else if (ValueVT.isVector()) {
// Handle a multi-element vector.
- MVT IntermediateVT, RegisterVT;
+ EVT IntermediateVT, RegisterVT;
unsigned NumIntermediates;
unsigned NumRegs =
TLI.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
@@ -496,11 +496,11 @@
ValueVT, &Ops[0], NumIntermediates);
} else if (PartVT.isFloatingPoint()) {
// FP split into multiple FP parts (for ppcf128)
- assert(ValueVT == MVT(MVT::ppcf128) && PartVT == MVT(MVT::f64) &&
+ assert(ValueVT == EVT(EVT::ppcf128) && PartVT == EVT(EVT::f64) &&
"Unexpected split");
SDValue Lo, Hi;
- Lo = DAG.getNode(ISD::BIT_CONVERT, dl, MVT(MVT::f64), Parts[0]);
- Hi = DAG.getNode(ISD::BIT_CONVERT, dl, MVT(MVT::f64), Parts[1]);
+ Lo = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(EVT::f64), Parts[0]);
+ Hi = DAG.getNode(ISD::BIT_CONVERT, dl, EVT(EVT::f64), Parts[1]);
if (TLI.isBigEndian())
std::swap(Lo, Hi);
Val = DAG.getNode(ISD::BUILD_PAIR, dl, ValueVT, Lo, Hi);
@@ -508,7 +508,7 @@
// FP split into integer parts (soft fp)
assert(ValueVT.isFloatingPoint() && PartVT.isInteger() &&
!PartVT.isVector() && "Unexpected split");
- MVT IntVT = MVT::getIntegerVT(ValueVT.getSizeInBits());
+ EVT IntVT = EVT::getIntegerVT(ValueVT.getSizeInBits());
Val = getCopyFromParts(DAG, dl, Parts, NumParts, PartVT, IntVT);
}
}
@@ -565,11 +565,11 @@
/// split into legal parts. If the parts contain more bits than Val, then, for
/// integers, ExtendKind can be used to specify how to generate the extra bits.
static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val,
- SDValue *Parts, unsigned NumParts, MVT PartVT,
+ SDValue *Parts, unsigned NumParts, EVT PartVT,
ISD::NodeType ExtendKind = ISD::ANY_EXTEND) {
const TargetLowering &TLI = DAG.getTargetLoweringInfo();
- MVT PtrVT = TLI.getPointerTy();
- MVT ValueVT = Val.getValueType();
+ EVT PtrVT = TLI.getPointerTy();
+ EVT ValueVT = Val.getValueType();
unsigned PartBits = PartVT.getSizeInBits();
unsigned OrigNumParts = NumParts;
assert(TLI.isTypeLegal(PartVT) && "Copying to an illegal type!");
@@ -590,7 +590,7 @@
assert(NumParts == 1 && "Do not know what to promote to!");
Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val);
} else if (PartVT.isInteger() && ValueVT.isInteger()) {
- ValueVT = MVT::getIntegerVT(NumParts * PartBits);
+ ValueVT = EVT::getIntegerVT(NumParts * PartBits);
Val = DAG.getNode(ExtendKind, dl, ValueVT, Val);
} else {
llvm_unreachable("Unknown mismatch!");
@@ -602,7 +602,7 @@
} else if (NumParts * PartBits < ValueVT.getSizeInBits()) {
// If the parts cover less bits than value has, truncate the value.
if (PartVT.isInteger() && ValueVT.isInteger()) {
- ValueVT = MVT::getIntegerVT(NumParts * PartBits);
+ ValueVT = EVT::getIntegerVT(NumParts * PartBits);
Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
} else {
llvm_unreachable("Unknown mismatch!");
@@ -636,19 +636,19 @@
// The odd parts were reversed by getCopyToParts - unreverse them.
std::reverse(Parts + RoundParts, Parts + NumParts);
NumParts = RoundParts;
- ValueVT = MVT::getIntegerVT(NumParts * PartBits);
+ ValueVT = EVT::getIntegerVT(NumParts * PartBits);
Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val);
}
// The number of parts is a power of 2. Repeatedly bisect the value using
// EXTRACT_ELEMENT.
Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::getIntegerVT(ValueVT.getSizeInBits()),
+ EVT::getIntegerVT(ValueVT.getSizeInBits()),
Val);
for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) {
for (unsigned i = 0; i < NumParts; i += StepSize) {
unsigned ThisBits = StepSize * PartBits / 2;
- MVT ThisVT = MVT::getIntegerVT (ThisBits);
+ EVT ThisVT = EVT::getIntegerVT (ThisBits);
SDValue &Part0 = Parts[i];
SDValue &Part1 = Parts[i+StepSize/2];
@@ -694,7 +694,7 @@
}
// Handle a multi-element vector.
- MVT IntermediateVT, RegisterVT;
+ EVT IntermediateVT, RegisterVT;
unsigned NumIntermediates;
unsigned NumRegs = TLI
.getVectorTypeBreakdown(ValueVT, IntermediateVT, NumIntermediates,
@@ -774,7 +774,7 @@
}
// Otherwise, we have to make a token factor node.
- SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
+ SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
&PendingLoads[0], PendingLoads.size());
PendingLoads.clear();
DAG.setRoot(Root);
@@ -804,7 +804,7 @@
PendingExports.push_back(Root);
}
- Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
+ Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
&PendingExports[0],
PendingExports.size());
PendingExports.clear();
@@ -833,7 +833,7 @@
if (N.getNode()) return N;
if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(V))) {
- MVT VT = TLI.getValueType(V->getType(), true);
+ EVT VT = TLI.getValueType(V->getType(), true);
if (ConstantInt *CI = dyn_cast<ConstantInt>(C))
return N = DAG.getConstant(*CI, VT);
@@ -873,14 +873,14 @@
assert((isa<ConstantAggregateZero>(C) || isa<UndefValue>(C)) &&
"Unknown struct or array constant!");
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, C->getType(), ValueVTs);
unsigned NumElts = ValueVTs.size();
if (NumElts == 0)
return SDValue(); // empty struct
SmallVector<SDValue, 4> Constants(NumElts);
for (unsigned i = 0; i != NumElts; ++i) {
- MVT EltVT = ValueVTs[i];
+ EVT EltVT = ValueVTs[i];
if (isa<UndefValue>(C))
Constants[i] = DAG.getUNDEF(EltVT);
else if (EltVT.isFloatingPoint())
@@ -902,7 +902,7 @@
Ops.push_back(getValue(CP->getOperand(i)));
} else {
assert(isa<ConstantAggregateZero>(C) && "Unknown vector constant!");
- MVT EltVT = TLI.getValueType(VecTy->getElementType());
+ EVT EltVT = TLI.getValueType(VecTy->getElementType());
SDValue Op;
if (EltVT.isFloatingPoint())
@@ -939,14 +939,14 @@
SDValue Chain = getControlRoot();
SmallVector<ISD::OutputArg, 8> Outs;
for (unsigned i = 0, e = I.getNumOperands(); i != e; ++i) {
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, I.getOperand(i)->getType(), ValueVTs);
unsigned NumValues = ValueVTs.size();
if (NumValues == 0) continue;
SDValue RetOp = getValue(I.getOperand(i));
for (unsigned j = 0, f = NumValues; j != f; ++j) {
- MVT VT = ValueVTs[j];
+ EVT VT = ValueVTs[j];
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
@@ -961,13 +961,13 @@
// conventions. The frontend should mark functions whose return values
// require promoting with signext or zeroext attributes.
if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
- MVT MinVT = TLI.getRegisterType(MVT::i32);
+ EVT MinVT = TLI.getRegisterType(EVT::i32);
if (VT.bitsLT(MinVT))
VT = MinVT;
}
unsigned NumParts = TLI.getNumRegisters(VT);
- MVT PartVT = TLI.getRegisterType(VT);
+ EVT PartVT = TLI.getRegisterType(VT);
SmallVector<SDValue, 4> Parts(NumParts);
getCopyToParts(DAG, getCurDebugLoc(),
SDValue(RetOp.getNode(), RetOp.getResNo() + j),
@@ -995,7 +995,7 @@
Outs, getCurDebugLoc(), DAG);
// Verify that the target's LowerReturn behaved as expected.
- assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
+ assert(Chain.getNode() && Chain.getValueType() == EVT::Other &&
"LowerReturn didn't return a valid chain!");
// Update the DAG with the new chain value resulting from return lowering.
@@ -1250,7 +1250,7 @@
// If this is not a fall-through branch, emit the branch.
if (Succ0MBB != NextBlock)
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
- MVT::Other, getControlRoot(),
+ EVT::Other, getControlRoot(),
DAG.getBasicBlock(Succ0MBB)));
return;
}
@@ -1334,7 +1334,7 @@
SDValue True = DAG.getConstant(1, CondLHS.getValueType());
Cond = DAG.getNode(ISD::XOR, dl, CondLHS.getValueType(), CondLHS, True);
} else
- Cond = DAG.getSetCC(dl, MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
+ Cond = DAG.getSetCC(dl, EVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC);
} else {
assert(CB.CC == ISD::SETLE && "Can handle only LE ranges now");
@@ -1342,15 +1342,15 @@
const APInt& High = cast<ConstantInt>(CB.CmpRHS)->getValue();
SDValue CmpOp = getValue(CB.CmpMHS);
- MVT VT = CmpOp.getValueType();
+ EVT VT = CmpOp.getValueType();
if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) {
- Cond = DAG.getSetCC(dl, MVT::i1, CmpOp, DAG.getConstant(High, VT),
+ Cond = DAG.getSetCC(dl, EVT::i1, CmpOp, DAG.getConstant(High, VT),
ISD::SETLE);
} else {
SDValue SUB = DAG.getNode(ISD::SUB, dl,
VT, CmpOp, DAG.getConstant(Low, VT));
- Cond = DAG.getSetCC(dl, MVT::i1, SUB,
+ Cond = DAG.getSetCC(dl, EVT::i1, SUB,
DAG.getConstant(High-Low, VT), ISD::SETULE);
}
}
@@ -1374,7 +1374,7 @@
Cond = DAG.getNode(ISD::XOR, dl, Cond.getValueType(), Cond, True);
}
SDValue BrCond = DAG.getNode(ISD::BRCOND, dl,
- MVT::Other, getControlRoot(), Cond,
+ EVT::Other, getControlRoot(), Cond,
DAG.getBasicBlock(CB.TrueBB));
// If the branch was constant folded, fix up the CFG.
@@ -1389,7 +1389,7 @@
if (CB.FalseBB == NextBlock)
DAG.setRoot(BrCond);
else
- DAG.setRoot(DAG.getNode(ISD::BR, dl, MVT::Other, BrCond,
+ DAG.setRoot(DAG.getNode(ISD::BR, dl, EVT::Other, BrCond,
DAG.getBasicBlock(CB.FalseBB)));
}
}
@@ -1398,12 +1398,12 @@
void SelectionDAGLowering::visitJumpTable(JumpTable &JT) {
// Emit the code for the jump table
assert(JT.Reg != -1U && "Should lower JT Header first!");
- MVT PTy = TLI.getPointerTy();
+ EVT PTy = TLI.getPointerTy();
SDValue Index = DAG.getCopyFromReg(getControlRoot(), getCurDebugLoc(),
JT.Reg, PTy);
SDValue Table = DAG.getJumpTable(JT.JTI, PTy);
DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(),
- MVT::Other, Index.getValue(1),
+ EVT::Other, Index.getValue(1),
Table, Index));
}
@@ -1415,7 +1415,7 @@
// conditional branch to default mbb if the result is greater than the
// difference between smallest and largest cases.
SDValue SwitchOp = getValue(JTH.SValue);
- MVT VT = SwitchOp.getValueType();
+ EVT VT = SwitchOp.getValueType();
SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
DAG.getConstant(JTH.First, VT));
@@ -1452,13 +1452,13 @@
NextBlock = BBI;
SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
- MVT::Other, CopyTo, CMP,
+ EVT::Other, CopyTo, CMP,
DAG.getBasicBlock(JT.Default));
if (JT.MBB == NextBlock)
DAG.setRoot(BrCond);
else
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond,
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, BrCond,
DAG.getBasicBlock(JT.MBB)));
}
@@ -1467,7 +1467,7 @@
void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) {
// Subtract the minimum value
SDValue SwitchOp = getValue(B.SValue);
- MVT VT = SwitchOp.getValueType();
+ EVT VT = SwitchOp.getValueType();
SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp,
DAG.getConstant(B.First, VT));
@@ -1502,13 +1502,13 @@
CurMBB->addSuccessor(MBB);
SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
- MVT::Other, CopyTo, RangeCmp,
+ EVT::Other, CopyTo, RangeCmp,
DAG.getBasicBlock(B.Default));
if (MBB == NextBlock)
DAG.setRoot(BrRange);
else
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo,
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, CopyTo,
DAG.getBasicBlock(MBB)));
}
@@ -1537,7 +1537,7 @@
CurMBB->addSuccessor(NextMBB);
SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(),
- MVT::Other, getControlRoot(),
+ EVT::Other, getControlRoot(),
AndCmp, DAG.getBasicBlock(B.TargetBB));
// Set NextBlock to be the MBB immediately after the current one, if any.
@@ -1550,7 +1550,7 @@
if (NextMBB == NextBlock)
DAG.setRoot(BrAnd);
else
- DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd,
+ DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), EVT::Other, BrAnd,
DAG.getBasicBlock(NextMBB)));
}
@@ -1575,7 +1575,7 @@
// Drop into normal successor.
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
- MVT::Other, getControlRoot(),
+ EVT::Other, getControlRoot(),
DAG.getBasicBlock(Return)));
}
@@ -1669,8 +1669,8 @@
static inline bool areJTsAllowed(const TargetLowering &TLI) {
return !DisableJumpTables &&
- (TLI.isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) ||
- TLI.isOperationLegalOrCustom(ISD::BRIND, MVT::Other));
+ (TLI.isOperationLegalOrCustom(ISD::BR_JT, EVT::Other) ||
+ TLI.isOperationLegalOrCustom(ISD::BRIND, EVT::Other));
}
static APInt ComputeRange(const APInt &First, const APInt &Last) {
@@ -1911,7 +1911,7 @@
CaseRecVector& WorkList,
Value* SV,
MachineBasicBlock* Default){
- MVT PTy = TLI.getPointerTy();
+ EVT PTy = TLI.getPointerTy();
unsigned IntPtrBits = PTy.getSizeInBits();
Case& FrontCase = *CR.Range.first;
@@ -2096,7 +2096,7 @@
CurMBB->addSuccessor(Default);
if (Default != NextBlock)
DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(),
- MVT::Other, getControlRoot(),
+ EVT::Other, getControlRoot(),
DAG.getBasicBlock(Default)));
return;
}
@@ -2188,8 +2188,8 @@
if (!isa<VectorType>(I.getType()) &&
Op2.getValueType() != TLI.getShiftAmountTy()) {
// If the operand is smaller than the shift count type, promote it.
- MVT PTy = TLI.getPointerTy();
- MVT STy = TLI.getShiftAmountTy();
+ EVT PTy = TLI.getPointerTy();
+ EVT STy = TLI.getShiftAmountTy();
if (STy.bitsGT(Op2.getValueType()))
Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(),
TLI.getShiftAmountTy(), Op2);
@@ -2226,7 +2226,7 @@
SDValue Op2 = getValue(I.getOperand(1));
ISD::CondCode Opcode = getICmpCondCode(predicate);
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Opcode));
}
@@ -2239,12 +2239,12 @@
SDValue Op1 = getValue(I.getOperand(0));
SDValue Op2 = getValue(I.getOperand(1));
ISD::CondCode Condition = getFCmpCondCode(predicate);
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getSetCC(getCurDebugLoc(), DestVT, Op1, Op2, Condition));
}
void SelectionDAGLowering::visitSelect(User &I) {
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, I.getType(), ValueVTs);
unsigned NumValues = ValueVTs.size();
if (NumValues != 0) {
@@ -2269,7 +2269,7 @@
void SelectionDAGLowering::visitTrunc(User &I) {
// TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest).
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
}
@@ -2277,7 +2277,7 @@
// ZExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
// ZExt also can't be a cast to bool for same reason. So, nothing much to do
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N));
}
@@ -2285,14 +2285,14 @@
// SExt cannot be a no-op cast because sizeof(src) < sizeof(dest).
// SExt also can't be a cast to bool for same reason. So, nothing much to do
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N));
}
void SelectionDAGLowering::visitFPTrunc(User &I) {
// FPTrunc is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(),
DestVT, N, DAG.getIntPtrConstant(0)));
}
@@ -2300,35 +2300,35 @@
void SelectionDAGLowering::visitFPExt(User &I){
// FPTrunc is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N));
}
void SelectionDAGLowering::visitFPToUI(User &I) {
// FPToUI is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N));
}
void SelectionDAGLowering::visitFPToSI(User &I) {
// FPToSI is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N));
}
void SelectionDAGLowering::visitUIToFP(User &I) {
// UIToFP is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N));
}
void SelectionDAGLowering::visitSIToFP(User &I){
// SIToFP is never a no-op cast, no need to check
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N));
}
@@ -2336,8 +2336,8 @@
// What to do depends on the size of the integer and the size of the pointer.
// We can either truncate, zero extend, or no-op, accordingly.
SDValue N = getValue(I.getOperand(0));
- MVT SrcVT = N.getValueType();
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT SrcVT = N.getValueType();
+ EVT DestVT = TLI.getValueType(I.getType());
SDValue Result;
if (DestVT.bitsLT(SrcVT))
Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N);
@@ -2351,8 +2351,8 @@
// What to do depends on the size of the integer and the size of the pointer.
// We can either truncate, zero extend, or no-op, accordingly.
SDValue N = getValue(I.getOperand(0));
- MVT SrcVT = N.getValueType();
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT SrcVT = N.getValueType();
+ EVT DestVT = TLI.getValueType(I.getType());
if (DestVT.bitsLT(SrcVT))
setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N));
else
@@ -2363,7 +2363,7 @@
void SelectionDAGLowering::visitBitCast(User &I) {
SDValue N = getValue(I.getOperand(0));
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
// BitCast assures us that source and destination are the same size so this
// is either a BIT_CONVERT or a no-op.
@@ -2424,8 +2424,8 @@
Mask.push_back(cast<ConstantInt>(MaskElts[i])->getSExtValue());
}
- MVT VT = TLI.getValueType(I.getType());
- MVT SrcVT = Src1.getValueType();
+ EVT VT = TLI.getValueType(I.getType());
+ EVT SrcVT = Src1.getValueType();
unsigned SrcNumElts = SrcVT.getVectorNumElements();
if (SrcNumElts == MaskNumElts) {
@@ -2559,8 +2559,8 @@
// We can't use either concat vectors or extract subvectors so fall back to
// replacing the shuffle with extract and build vector.
// to insert and build vector.
- MVT EltVT = VT.getVectorElementType();
- MVT PtrVT = TLI.getPointerTy();
+ EVT EltVT = VT.getVectorElementType();
+ EVT PtrVT = TLI.getPointerTy();
SmallVector<SDValue,8> Ops;
for (unsigned i = 0; i != MaskNumElts; ++i) {
if (Mask[i] < 0) {
@@ -2591,9 +2591,9 @@
unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
I.idx_begin(), I.idx_end());
- SmallVector<MVT, 4> AggValueVTs;
+ SmallVector<EVT, 4> AggValueVTs;
ComputeValueVTs(TLI, AggTy, AggValueVTs);
- SmallVector<MVT, 4> ValValueVTs;
+ SmallVector<EVT, 4> ValValueVTs;
ComputeValueVTs(TLI, ValTy, ValValueVTs);
unsigned NumAggValues = AggValueVTs.size();
@@ -2630,7 +2630,7 @@
unsigned LinearIndex = ComputeLinearIndex(TLI, AggTy,
I.idx_begin(), I.idx_end());
- SmallVector<MVT, 4> ValValueVTs;
+ SmallVector<EVT, 4> ValValueVTs;
ComputeValueVTs(TLI, ValTy, ValValueVTs);
unsigned NumValValues = ValValueVTs.size();
@@ -2675,12 +2675,12 @@
uint64_t Offs =
TD->getTypeAllocSize(Ty)*cast<ConstantInt>(CI)->getSExtValue();
SDValue OffsVal;
- MVT PTy = TLI.getPointerTy();
+ EVT PTy = TLI.getPointerTy();
unsigned PtrBits = PTy.getSizeInBits();
if (PtrBits < 64) {
OffsVal = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
TLI.getPointerTy(),
- DAG.getConstant(Offs, MVT::i64));
+ DAG.getConstant(Offs, EVT::i64));
} else
OffsVal = DAG.getIntPtrConstant(Offs);
N = DAG.getNode(ISD::ADD, getCurDebugLoc(), N.getValueType(), N,
@@ -2743,7 +2743,7 @@
- MVT IntPtr = TLI.getPointerTy();
+ EVT IntPtr = TLI.getPointerTy();
if (IntPtr.bitsLT(AllocSize.getValueType()))
AllocSize = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(),
IntPtr, AllocSize);
@@ -2770,7 +2770,7 @@
DAG.getIntPtrConstant(~(uint64_t)(StackAlign-1)));
SDValue Ops[] = { getRoot(), AllocSize, DAG.getIntPtrConstant(Align) };
- SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), MVT::Other);
+ SDVTList VTs = DAG.getVTList(AllocSize.getValueType(), EVT::Other);
SDValue DSA = DAG.getNode(ISD::DYNAMIC_STACKALLOC, getCurDebugLoc(),
VTs, Ops, 3);
setValue(&I, DSA);
@@ -2789,7 +2789,7 @@
bool isVolatile = I.isVolatile();
unsigned Alignment = I.getAlignment();
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
SmallVector<uint64_t, 4> Offsets;
ComputeValueVTs(TLI, Ty, ValueVTs, &Offsets);
unsigned NumValues = ValueVTs.size();
@@ -2812,7 +2812,7 @@
SmallVector<SDValue, 4> Values(NumValues);
SmallVector<SDValue, 4> Chains(NumValues);
- MVT PtrVT = Ptr.getValueType();
+ EVT PtrVT = Ptr.getValueType();
for (unsigned i = 0; i != NumValues; ++i) {
SDValue L = DAG.getLoad(ValueVTs[i], getCurDebugLoc(), Root,
DAG.getNode(ISD::ADD, getCurDebugLoc(),
@@ -2826,7 +2826,7 @@
if (!ConstantMemory) {
SDValue Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
- MVT::Other,
+ EVT::Other,
&Chains[0], NumValues);
if (isVolatile)
DAG.setRoot(Chain);
@@ -2844,7 +2844,7 @@
Value *SrcV = I.getOperand(0);
Value *PtrV = I.getOperand(1);
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
SmallVector<uint64_t, 4> Offsets;
ComputeValueVTs(TLI, SrcV->getType(), ValueVTs, &Offsets);
unsigned NumValues = ValueVTs.size();
@@ -2859,7 +2859,7 @@
SDValue Root = getRoot();
SmallVector<SDValue, 4> Chains(NumValues);
- MVT PtrVT = Ptr.getValueType();
+ EVT PtrVT = Ptr.getValueType();
bool isVolatile = I.isVolatile();
unsigned Alignment = I.getAlignment();
for (unsigned i = 0; i != NumValues; ++i)
@@ -2872,7 +2872,7 @@
isVolatile, Alignment);
DAG.setRoot(DAG.getNode(ISD::TokenFactor, getCurDebugLoc(),
- MVT::Other, &Chains[0], NumValues));
+ EVT::Other, &Chains[0], NumValues));
}
/// visitTargetIntrinsic - Lower a call of a target intrinsic to an INTRINSIC
@@ -2909,7 +2909,7 @@
Ops.push_back(Op);
}
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, I.getType(), ValueVTs);
#ifndef NDEBUG
for (unsigned Val = 0, E = ValueVTs.size(); Val != E; ++Val) {
@@ -2918,7 +2918,7 @@
}
#endif // NDEBUG
if (HasChain)
- ValueVTs.push_back(MVT::Other);
+ ValueVTs.push_back(EVT::Other);
SDVTList VTs = DAG.getVTList(ValueVTs.data(), ValueVTs.size());
@@ -2951,7 +2951,7 @@
}
if (I.getType() != Type::VoidTy) {
if (const VectorType *PTy = dyn_cast<VectorType>(I.getType())) {
- MVT VT = TLI.getValueType(PTy);
+ EVT VT = TLI.getValueType(PTy);
Result = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), VT, Result);
}
setValue(&I, Result);
@@ -3033,11 +3033,11 @@
/// where Op is the hexidecimal representation of floating point value.
static SDValue
GetSignificand(SelectionDAG &DAG, SDValue Op, DebugLoc dl) {
- SDValue t1 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
- DAG.getConstant(0x007fffff, MVT::i32));
- SDValue t2 = DAG.getNode(ISD::OR, dl, MVT::i32, t1,
- DAG.getConstant(0x3f800000, MVT::i32));
- return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t2);
+ SDValue t1 = DAG.getNode(ISD::AND, dl, EVT::i32, Op,
+ DAG.getConstant(0x007fffff, EVT::i32));
+ SDValue t2 = DAG.getNode(ISD::OR, dl, EVT::i32, t1,
+ DAG.getConstant(0x3f800000, EVT::i32));
+ return DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t2);
}
/// GetExponent - Get the exponent:
@@ -3048,19 +3048,19 @@
static SDValue
GetExponent(SelectionDAG &DAG, SDValue Op, const TargetLowering &TLI,
DebugLoc dl) {
- SDValue t0 = DAG.getNode(ISD::AND, dl, MVT::i32, Op,
- DAG.getConstant(0x7f800000, MVT::i32));
- SDValue t1 = DAG.getNode(ISD::SRL, dl, MVT::i32, t0,
+ SDValue t0 = DAG.getNode(ISD::AND, dl, EVT::i32, Op,
+ DAG.getConstant(0x7f800000, EVT::i32));
+ SDValue t1 = DAG.getNode(ISD::SRL, dl, EVT::i32, t0,
DAG.getConstant(23, TLI.getPointerTy()));
- SDValue t2 = DAG.getNode(ISD::SUB, dl, MVT::i32, t1,
- DAG.getConstant(127, MVT::i32));
- return DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, t2);
+ SDValue t2 = DAG.getNode(ISD::SUB, dl, EVT::i32, t1,
+ DAG.getConstant(127, EVT::i32));
+ return DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, t2);
}
/// getF32Constant - Get 32-bit floating point constant.
static SDValue
getF32Constant(SelectionDAG &DAG, unsigned Flt) {
- return DAG.getConstantFP(APFloat(APInt(32, Flt)), MVT::f32);
+ return DAG.getConstantFP(APFloat(APInt(32, Flt)), EVT::f32);
}
/// Inlined utility function to implement binary input atomic intrinsics for
@@ -3087,7 +3087,7 @@
SDValue Op1 = getValue(I.getOperand(1));
SDValue Op2 = getValue(I.getOperand(2));
- SDVTList VTs = DAG.getVTList(Op1.getValueType(), MVT::i1);
+ SDVTList VTs = DAG.getVTList(Op1.getValueType(), EVT::i1);
SDValue Result = DAG.getNode(Op, getCurDebugLoc(), VTs, Op1, Op2);
setValue(&I, Result);
@@ -3101,7 +3101,7 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
@@ -3110,16 +3110,16 @@
//
// #define LOG2OFe 1.4426950f
// IntegerPartOfX = ((int32_t)(X * LOG2OFe));
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, Op,
getF32Constant(DAG, 0x3fb8aa3b));
- SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
+ SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, t0);
// FractionalPartOfX = (X * LOG2OFe) - (float)IntegerPartOfX;
- SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
- SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
+ SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
+ SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0, t1);
// IntegerPartOfX <<= 23;
- IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
+ IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
DAG.getConstant(23, TLI.getPointerTy()));
if (LimitFloatPrecision <= 6) {
@@ -3130,20 +3130,20 @@
// (0.735607626f + 0.252464424f * x) * x;
//
// error 0.0144103317, which is 6 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3e814304));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f3c50c8));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f7f5e7e));
- SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t5);
+ SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,EVT::i32, t5);
// Add the exponent into the result in integer domain.
- SDValue t6 = DAG.getNode(ISD::ADD, dl, MVT::i32,
+ SDValue t6 = DAG.getNode(ISD::ADD, dl, EVT::i32,
TwoToFracPartOfX, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t6);
+ result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t6);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3153,23 +3153,23 @@
// (0.224338339f + 0.792043434e-1f * x) * x) * x;
//
// 0.000107046256 error, which is 13 to 14 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3da235e3));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3e65b8f3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f324b07));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3f7ff8fd));
- SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,MVT::i32, t7);
+ SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,EVT::i32, t7);
// Add the exponent into the result in integer domain.
- SDValue t8 = DAG.getNode(ISD::ADD, dl, MVT::i32,
+ SDValue t8 = DAG.getNode(ISD::ADD, dl, EVT::i32,
TwoToFracPartOfX, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t8);
+ result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t8);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3182,33 +3182,33 @@
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
//
// error 2.47208000*10^(-7), which is better than 18 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3924b03e));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3ab24b87));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3c1d8c17));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3d634a1d));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
getF32Constant(DAG, 0x3e75fe14));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
- SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
+ SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
getF32Constant(DAG, 0x3f317234));
- SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
- SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
+ SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
+ SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
getF32Constant(DAG, 0x3f800000));
SDValue TwoToFracPartOfX = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::i32, t13);
+ EVT::i32, t13);
// Add the exponent into the result in integer domain.
- SDValue t14 = DAG.getNode(ISD::ADD, dl, MVT::i32,
+ SDValue t14 = DAG.getNode(ISD::ADD, dl, EVT::i32,
TwoToFracPartOfX, IntegerPartOfX);
- result = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::f32, t14);
+ result = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::f32, t14);
}
} else {
// No special expansion.
@@ -3227,14 +3227,14 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
+ SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
// Scale the exponent by log(2) [0.69314718f].
SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
- SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
+ SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, EVT::f32, Exp,
getF32Constant(DAG, 0x3f317218));
// Get the significand and build it into a floating-point number with
@@ -3249,16 +3249,16 @@
// (1.4034025f - 0.23903021f * x) * x;
//
// error 0.0034276066, which is better than 8 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbe74c456));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3fb3a2b1));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f949a29));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, LogOfMantissa);
+ EVT::f32, LogOfExponent, LogOfMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3269,22 +3269,22 @@
// (0.44717955f - 0.56570851e-1f * x) * x) * x) * x;
//
// error 0.000061011436, which is 14 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbd67b6d6));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3ee4f4b8));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3fbc278b));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x40348e95));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3fdef31a));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, LogOfMantissa);
+ EVT::f32, LogOfExponent, LogOfMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3297,28 +3297,28 @@
// (0.19073739f - 0.17809712e-1f * x) * x) * x) * x) * x)*x;
//
// error 0.0000023660568, which is better than 18 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbc91e5ac));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3e4350aa));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f60d3e3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x4011cdf0));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
getF32Constant(DAG, 0x406cfd1c));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
getF32Constant(DAG, 0x408797cb));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
- SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
+ SDValue LogOfMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t10,
getF32Constant(DAG, 0x4006dcab));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, LogOfMantissa);
+ EVT::f32, LogOfExponent, LogOfMantissa);
}
} else {
// No special expansion.
@@ -3337,10 +3337,10 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
+ SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
// Get the exponent.
SDValue LogOfExponent = GetExponent(DAG, Op1, TLI, dl);
@@ -3357,16 +3357,16 @@
// Log2ofMantissa = -1.6749035f + (2.0246817f - .34484768f * x) * x;
//
// error 0.0049451742, which is more than 7 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbeb08fe0));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x40019463));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3fd6633d));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, Log2ofMantissa);
+ EVT::f32, LogOfExponent, Log2ofMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3377,22 +3377,22 @@
// (.645142248f - 0.816157886e-1f * x) * x) * x) * x;
//
// error 0.0000876136000, which is better than 13 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbda7262e));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3f25280b));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x4007b923));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x40823e2f));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
getF32Constant(DAG, 0x4020d29c));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, Log2ofMantissa);
+ EVT::f32, LogOfExponent, Log2ofMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3406,28 +3406,28 @@
// 0.25691327e-1f * x) * x) * x) * x) * x) * x;
//
// error 0.0000018516, which is better than 18 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbcd2769e));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3e8ce0b9));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3fa22ae7));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x40525723));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t6,
getF32Constant(DAG, 0x40aaf200));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
getF32Constant(DAG, 0x40c39dad));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
- SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
+ SDValue Log2ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t10,
getF32Constant(DAG, 0x4042902c));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, Log2ofMantissa);
+ EVT::f32, LogOfExponent, Log2ofMantissa);
}
} else {
// No special expansion.
@@ -3446,14 +3446,14 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, Op);
+ SDValue Op1 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, Op);
// Scale the exponent by log10(2) [0.30102999f].
SDValue Exp = GetExponent(DAG, Op1, TLI, dl);
- SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, MVT::f32, Exp,
+ SDValue LogOfExponent = DAG.getNode(ISD::FMUL, dl, EVT::f32, Exp,
getF32Constant(DAG, 0x3e9a209a));
// Get the significand and build it into a floating-point number with
@@ -3468,16 +3468,16 @@
// (0.60948995f - 0.10380950f * x) * x;
//
// error 0.0014886165, which is 6 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0xbdd49a13));
- SDValue t1 = DAG.getNode(ISD::FADD, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FADD, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3f1c0789));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f011300));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, Log10ofMantissa);
+ EVT::f32, LogOfExponent, Log10ofMantissa);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3487,19 +3487,19 @@
// (-0.31664806f + 0.47637168e-1f * x) * x) * x;
//
// error 0.00019228036, which is better than 12 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3d431f31));
- SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3ea21fb2));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f6ae232));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f25f7c3));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, Log10ofMantissa);
+ EVT::f32, LogOfExponent, Log10ofMantissa);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3511,25 +3511,25 @@
// (-0.12539807f + 0.13508273e-1f * x) * x) * x) * x) * x;
//
// error 0.0000037995730, which is better than 18 bits
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3c5d51ce));
- SDValue t1 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0,
+ SDValue t1 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0,
getF32Constant(DAG, 0x3e00685a));
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t1, X);
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t1, X);
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3efb6798));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FSUB, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FSUB, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f88d192));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3fc4316c));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
- SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, MVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
+ SDValue Log10ofMantissa = DAG.getNode(ISD::FSUB, dl, EVT::f32, t8,
getF32Constant(DAG, 0x3f57ce70));
result = DAG.getNode(ISD::FADD, dl,
- MVT::f32, LogOfExponent, Log10ofMantissa);
+ EVT::f32, LogOfExponent, Log10ofMantissa);
}
} else {
// No special expansion.
@@ -3548,18 +3548,18 @@
SDValue result;
DebugLoc dl = getCurDebugLoc();
- if (getValue(I.getOperand(1)).getValueType() == MVT::f32 &&
+ if (getValue(I.getOperand(1)).getValueType() == EVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
SDValue Op = getValue(I.getOperand(1));
- SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, Op);
+ SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, Op);
// FractionalPartOfX = x - (float)IntegerPartOfX;
- SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
- SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, Op, t1);
+ SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
+ SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, Op, t1);
// IntegerPartOfX <<= 23;
- IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
+ IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
DAG.getConstant(23, TLI.getPointerTy()));
if (LimitFloatPrecision <= 6) {
@@ -3570,19 +3570,19 @@
// (0.735607626f + 0.252464424f * x) * x;
//
// error 0.0144103317, which is 6 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3e814304));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f3c50c8));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f7f5e7e));
- SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
+ SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t5);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, EVT::i32, t6, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::f32, TwoToFractionalPartOfX);
+ EVT::f32, TwoToFractionalPartOfX);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3592,22 +3592,22 @@
// (0.224338339f + 0.792043434e-1f * x) * x) * x;
//
// error 0.000107046256, which is 13 to 14 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3da235e3));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3e65b8f3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f324b07));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3f7ff8fd));
- SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
+ SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t7);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, EVT::i32, t8, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::f32, TwoToFractionalPartOfX);
+ EVT::f32, TwoToFractionalPartOfX);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3619,31 +3619,31 @@
// (0.961591928e-2f +
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
// error 2.47208000*10^(-7), which is better than 18 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3924b03e));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3ab24b87));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3c1d8c17));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3d634a1d));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
getF32Constant(DAG, 0x3e75fe14));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
- SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
+ SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
getF32Constant(DAG, 0x3f317234));
- SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
- SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
+ SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
+ SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
getF32Constant(DAG, 0x3f800000));
- SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
+ SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t13);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, EVT::i32, t14, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::f32, TwoToFractionalPartOfX);
+ EVT::f32, TwoToFractionalPartOfX);
}
} else {
// No special expansion.
@@ -3664,8 +3664,8 @@
DebugLoc dl = getCurDebugLoc();
bool IsExp10 = false;
- if (getValue(Val).getValueType() == MVT::f32 &&
- getValue(I.getOperand(2)).getValueType() == MVT::f32 &&
+ if (getValue(Val).getValueType() == EVT::f32 &&
+ getValue(I.getOperand(2)).getValueType() == EVT::f32 &&
LimitFloatPrecision > 0 && LimitFloatPrecision <= 18) {
if (Constant *C = const_cast<Constant*>(dyn_cast<Constant>(Val))) {
if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
@@ -3683,16 +3683,16 @@
//
// #define LOG2OF10 3.3219281f
// IntegerPartOfX = (int32_t)(x * LOG2OF10);
- SDValue t0 = DAG.getNode(ISD::FMUL, dl, MVT::f32, Op,
+ SDValue t0 = DAG.getNode(ISD::FMUL, dl, EVT::f32, Op,
getF32Constant(DAG, 0x40549a78));
- SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, MVT::i32, t0);
+ SDValue IntegerPartOfX = DAG.getNode(ISD::FP_TO_SINT, dl, EVT::i32, t0);
// FractionalPartOfX = x - (float)IntegerPartOfX;
- SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, MVT::f32, IntegerPartOfX);
- SDValue X = DAG.getNode(ISD::FSUB, dl, MVT::f32, t0, t1);
+ SDValue t1 = DAG.getNode(ISD::SINT_TO_FP, dl, EVT::f32, IntegerPartOfX);
+ SDValue X = DAG.getNode(ISD::FSUB, dl, EVT::f32, t0, t1);
// IntegerPartOfX <<= 23;
- IntegerPartOfX = DAG.getNode(ISD::SHL, dl, MVT::i32, IntegerPartOfX,
+ IntegerPartOfX = DAG.getNode(ISD::SHL, dl, EVT::i32, IntegerPartOfX,
DAG.getConstant(23, TLI.getPointerTy()));
if (LimitFloatPrecision <= 6) {
@@ -3703,19 +3703,19 @@
// (0.735607626f + 0.252464424f * x) * x;
//
// error 0.0144103317, which is 6 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3e814304));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3f3c50c8));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f7f5e7e));
- SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t5);
+ SDValue t6 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t5);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, MVT::i32, t6, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, EVT::i32, t6, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::f32, TwoToFractionalPartOfX);
+ EVT::f32, TwoToFractionalPartOfX);
} else if (LimitFloatPrecision > 6 && LimitFloatPrecision <= 12) {
// For floating-point precision of 12:
//
@@ -3725,22 +3725,22 @@
// (0.224338339f + 0.792043434e-1f * x) * x) * x;
//
// error 0.000107046256, which is 13 to 14 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3da235e3));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3e65b8f3));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3f324b07));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3f7ff8fd));
- SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t7);
+ SDValue t8 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t7);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, MVT::i32, t8, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, EVT::i32, t8, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::f32, TwoToFractionalPartOfX);
+ EVT::f32, TwoToFractionalPartOfX);
} else { // LimitFloatPrecision > 12 && LimitFloatPrecision <= 18
// For floating-point precision of 18:
//
@@ -3752,31 +3752,31 @@
// (0.961591928e-2f +
// (0.136028312e-2f + 0.157059148e-3f *x)*x)*x)*x)*x)*x;
// error 2.47208000*10^(-7), which is better than 18 bits
- SDValue t2 = DAG.getNode(ISD::FMUL, dl, MVT::f32, X,
+ SDValue t2 = DAG.getNode(ISD::FMUL, dl, EVT::f32, X,
getF32Constant(DAG, 0x3924b03e));
- SDValue t3 = DAG.getNode(ISD::FADD, dl, MVT::f32, t2,
+ SDValue t3 = DAG.getNode(ISD::FADD, dl, EVT::f32, t2,
getF32Constant(DAG, 0x3ab24b87));
- SDValue t4 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t3, X);
- SDValue t5 = DAG.getNode(ISD::FADD, dl, MVT::f32, t4,
+ SDValue t4 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t3, X);
+ SDValue t5 = DAG.getNode(ISD::FADD, dl, EVT::f32, t4,
getF32Constant(DAG, 0x3c1d8c17));
- SDValue t6 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t5, X);
- SDValue t7 = DAG.getNode(ISD::FADD, dl, MVT::f32, t6,
+ SDValue t6 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t5, X);
+ SDValue t7 = DAG.getNode(ISD::FADD, dl, EVT::f32, t6,
getF32Constant(DAG, 0x3d634a1d));
- SDValue t8 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t7, X);
- SDValue t9 = DAG.getNode(ISD::FADD, dl, MVT::f32, t8,
+ SDValue t8 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t7, X);
+ SDValue t9 = DAG.getNode(ISD::FADD, dl, EVT::f32, t8,
getF32Constant(DAG, 0x3e75fe14));
- SDValue t10 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t9, X);
- SDValue t11 = DAG.getNode(ISD::FADD, dl, MVT::f32, t10,
+ SDValue t10 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t9, X);
+ SDValue t11 = DAG.getNode(ISD::FADD, dl, EVT::f32, t10,
getF32Constant(DAG, 0x3f317234));
- SDValue t12 = DAG.getNode(ISD::FMUL, dl, MVT::f32, t11, X);
- SDValue t13 = DAG.getNode(ISD::FADD, dl, MVT::f32, t12,
+ SDValue t12 = DAG.getNode(ISD::FMUL, dl, EVT::f32, t11, X);
+ SDValue t13 = DAG.getNode(ISD::FADD, dl, EVT::f32, t12,
getF32Constant(DAG, 0x3f800000));
- SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::i32, t13);
+ SDValue t14 = DAG.getNode(ISD::BIT_CONVERT, dl, EVT::i32, t13);
SDValue TwoToFractionalPartOfX =
- DAG.getNode(ISD::ADD, dl, MVT::i32, t14, IntegerPartOfX);
+ DAG.getNode(ISD::ADD, dl, EVT::i32, t14, IntegerPartOfX);
result = DAG.getNode(ISD::BIT_CONVERT, dl,
- MVT::f32, TwoToFractionalPartOfX);
+ EVT::f32, TwoToFractionalPartOfX);
}
} else {
// No special expansion.
@@ -3973,14 +3973,14 @@
return 0;
Value *Variable = DI.getVariable();
- DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, MVT::Other, getRoot(),
+ DAG.setRoot(DAG.getNode(ISD::DECLARE, dl, EVT::Other, getRoot(),
getValue(DI.getAddress()), getValue(Variable)));
return 0;
}
case Intrinsic::eh_exception: {
// Insert the EXCEPTIONADDR instruction.
assert(CurMBB->isLandingPad() &&"Call to eh.exception not in landing pad!");
- SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
+ SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), EVT::Other);
SDValue Ops[1];
Ops[0] = DAG.getRoot();
SDValue Op = DAG.getNode(ISD::EXCEPTIONADDR, dl, VTs, Ops, 1);
@@ -3992,8 +3992,8 @@
case Intrinsic::eh_selector_i32:
case Intrinsic::eh_selector_i64: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
- MVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
- MVT::i32 : MVT::i64);
+ EVT VT = (Intrinsic == Intrinsic::eh_selector_i32 ?
+ EVT::i32 : EVT::i64);
if (MMI) {
if (CurMBB->isLandingPad())
@@ -4008,7 +4008,7 @@
}
// Insert the EHSELECTION instruction.
- SDVTList VTs = DAG.getVTList(VT, MVT::Other);
+ SDVTList VTs = DAG.getVTList(VT, EVT::Other);
SDValue Ops[2];
Ops[0] = getValue(I.getOperand(1));
Ops[1] = getRoot();
@@ -4025,8 +4025,8 @@
case Intrinsic::eh_typeid_for_i32:
case Intrinsic::eh_typeid_for_i64: {
MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
- MVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
- MVT::i32 : MVT::i64);
+ EVT VT = (Intrinsic == Intrinsic::eh_typeid_for_i32 ?
+ EVT::i32 : EVT::i64);
if (MMI) {
// Find the type id for the given typeinfo.
@@ -4047,7 +4047,7 @@
if (MachineModuleInfo *MMI = DAG.getMachineModuleInfo()) {
MMI->setCallsEHReturn(true);
DAG.setRoot(DAG.getNode(ISD::EH_RETURN, dl,
- MVT::Other,
+ EVT::Other,
getControlRoot(),
getValue(I.getOperand(1)),
getValue(I.getOperand(2))));
@@ -4064,7 +4064,7 @@
return 0;
case Intrinsic::eh_dwarf_cfa: {
- MVT VT = getValue(I.getOperand(1)).getValueType();
+ EVT VT = getValue(I.getOperand(1)).getValueType();
SDValue CfaArg;
if (VT.bitsGT(TLI.getPointerTy()))
CfaArg = DAG.getNode(ISD::TRUNCATE, dl,
@@ -4109,7 +4109,7 @@
case Intrinsic::convertus: Code = ISD::CVT_US; break;
case Intrinsic::convertuu: Code = ISD::CVT_UU; break;
}
- MVT DestVT = TLI.getValueType(I.getType());
+ EVT DestVT = TLI.getValueType(I.getType());
Value* Op1 = I.getOperand(1);
setValue(&I, DAG.getConvertRndSat(DestVT, getCurDebugLoc(), getValue(Op1),
DAG.getValueType(DestVT),
@@ -4161,13 +4161,13 @@
return 0;
case Intrinsic::pcmarker: {
SDValue Tmp = getValue(I.getOperand(1));
- DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, MVT::Other, getRoot(), Tmp));
+ DAG.setRoot(DAG.getNode(ISD::PCMARKER, dl, EVT::Other, getRoot(), Tmp));
return 0;
}
case Intrinsic::readcyclecounter: {
SDValue Op = getRoot();
SDValue Tmp = DAG.getNode(ISD::READCYCLECOUNTER, dl,
- DAG.getVTList(MVT::i64, MVT::Other),
+ DAG.getVTList(EVT::i64, EVT::Other),
&Op, 1);
setValue(&I, Tmp);
DAG.setRoot(Tmp.getValue(1));
@@ -4180,21 +4180,21 @@
return 0;
case Intrinsic::cttz: {
SDValue Arg = getValue(I.getOperand(1));
- MVT Ty = Arg.getValueType();
+ EVT Ty = Arg.getValueType();
SDValue result = DAG.getNode(ISD::CTTZ, dl, Ty, Arg);
setValue(&I, result);
return 0;
}
case Intrinsic::ctlz: {
SDValue Arg = getValue(I.getOperand(1));
- MVT Ty = Arg.getValueType();
+ EVT Ty = Arg.getValueType();
SDValue result = DAG.getNode(ISD::CTLZ, dl, Ty, Arg);
setValue(&I, result);
return 0;
}
case Intrinsic::ctpop: {
SDValue Arg = getValue(I.getOperand(1));
- MVT Ty = Arg.getValueType();
+ EVT Ty = Arg.getValueType();
SDValue result = DAG.getNode(ISD::CTPOP, dl, Ty, Arg);
setValue(&I, result);
return 0;
@@ -4202,21 +4202,21 @@
case Intrinsic::stacksave: {
SDValue Op = getRoot();
SDValue Tmp = DAG.getNode(ISD::STACKSAVE, dl,
- DAG.getVTList(TLI.getPointerTy(), MVT::Other), &Op, 1);
+ DAG.getVTList(TLI.getPointerTy(), EVT::Other), &Op, 1);
setValue(&I, Tmp);
DAG.setRoot(Tmp.getValue(1));
return 0;
}
case Intrinsic::stackrestore: {
SDValue Tmp = getValue(I.getOperand(1));
- DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, MVT::Other, getRoot(), Tmp));
+ DAG.setRoot(DAG.getNode(ISD::STACKRESTORE, dl, EVT::Other, getRoot(), Tmp));
return 0;
}
case Intrinsic::stackprotector: {
// Emit code into the DAG to store the stack guard onto the stack.
MachineFunction &MF = DAG.getMachineFunction();
MachineFrameInfo *MFI = MF.getFrameInfo();
- MVT PtrTy = TLI.getPointerTy();
+ EVT PtrTy = TLI.getPointerTy();
SDValue Src = getValue(I.getOperand(1)); // The guard's value.
AllocaInst *Slot = cast<AllocaInst>(I.getOperand(2));
@@ -4250,7 +4250,7 @@
Ops[5] = DAG.getSrcValue(F);
SDValue Tmp = DAG.getNode(ISD::TRAMPOLINE, dl,
- DAG.getVTList(TLI.getPointerTy(), MVT::Other),
+ DAG.getVTList(TLI.getPointerTy(), EVT::Other),
Ops, 6);
setValue(&I, Tmp);
@@ -4274,12 +4274,12 @@
return 0;
case Intrinsic::flt_rounds: {
- setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, MVT::i32));
+ setValue(&I, DAG.getNode(ISD::FLT_ROUNDS_, dl, EVT::i32));
return 0;
}
case Intrinsic::trap: {
- DAG.setRoot(DAG.getNode(ISD::TRAP, dl,MVT::Other, getRoot()));
+ DAG.setRoot(DAG.getNode(ISD::TRAP, dl,EVT::Other, getRoot()));
return 0;
}
@@ -4302,7 +4302,7 @@
Ops[1] = getValue(I.getOperand(1));
Ops[2] = getValue(I.getOperand(2));
Ops[3] = getValue(I.getOperand(3));
- DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, MVT::Other, &Ops[0], 4));
+ DAG.setRoot(DAG.getNode(ISD::PREFETCH, dl, EVT::Other, &Ops[0], 4));
return 0;
}
@@ -4312,7 +4312,7 @@
for (int x = 1; x < 6; ++x)
Ops[x] = getValue(I.getOperand(x));
- DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, MVT::Other, &Ops[0], 6));
+ DAG.setRoot(DAG.getNode(ISD::MEMBARRIER, dl, EVT::Other, &Ops[0], 6));
return 0;
}
case Intrinsic::atomic_cmp_swap: {
@@ -4599,9 +4599,9 @@
SmallVector<SDValue, 8> Parts;
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
// Copy the legal parts from the registers.
- MVT ValueVT = ValueVTs[Value];
+ EVT ValueVT = ValueVTs[Value];
unsigned NumRegs = TLI->getNumRegisters(ValueVT);
- MVT RegisterVT = RegVTs[Value];
+ EVT RegisterVT = RegVTs[Value];
Parts.resize(NumRegs);
for (unsigned i = 0; i != NumRegs; ++i) {
@@ -4630,25 +4630,25 @@
// FIXME: We capture more information than the dag can represent. For
// now, just use the tightest assertzext/assertsext possible.
bool isSExt = true;
- MVT FromVT(MVT::Other);
+ EVT FromVT(EVT::Other);
if (NumSignBits == RegSize)
- isSExt = true, FromVT = MVT::i1; // ASSERT SEXT 1
+ isSExt = true, FromVT = EVT::i1; // ASSERT SEXT 1
else if (NumZeroBits >= RegSize-1)
- isSExt = false, FromVT = MVT::i1; // ASSERT ZEXT 1
+ isSExt = false, FromVT = EVT::i1; // ASSERT ZEXT 1
else if (NumSignBits > RegSize-8)
- isSExt = true, FromVT = MVT::i8; // ASSERT SEXT 8
+ isSExt = true, FromVT = EVT::i8; // ASSERT SEXT 8
else if (NumZeroBits >= RegSize-8)
- isSExt = false, FromVT = MVT::i8; // ASSERT ZEXT 8
+ isSExt = false, FromVT = EVT::i8; // ASSERT ZEXT 8
else if (NumSignBits > RegSize-16)
- isSExt = true, FromVT = MVT::i16; // ASSERT SEXT 16
+ isSExt = true, FromVT = EVT::i16; // ASSERT SEXT 16
else if (NumZeroBits >= RegSize-16)
- isSExt = false, FromVT = MVT::i16; // ASSERT ZEXT 16
+ isSExt = false, FromVT = EVT::i16; // ASSERT ZEXT 16
else if (NumSignBits > RegSize-32)
- isSExt = true, FromVT = MVT::i32; // ASSERT SEXT 32
+ isSExt = true, FromVT = EVT::i32; // ASSERT SEXT 32
else if (NumZeroBits >= RegSize-32)
- isSExt = false, FromVT = MVT::i32; // ASSERT ZEXT 32
+ isSExt = false, FromVT = EVT::i32; // ASSERT ZEXT 32
- if (FromVT != MVT::Other) {
+ if (FromVT != EVT::Other) {
P = DAG.getNode(isSExt ? ISD::AssertSext : ISD::AssertZext, dl,
RegisterVT, P, DAG.getValueType(FromVT));
@@ -4680,9 +4680,9 @@
unsigned NumRegs = Regs.size();
SmallVector<SDValue, 8> Parts(NumRegs);
for (unsigned Value = 0, Part = 0, e = ValueVTs.size(); Value != e; ++Value) {
- MVT ValueVT = ValueVTs[Value];
+ EVT ValueVT = ValueVTs[Value];
unsigned NumParts = TLI->getNumRegisters(ValueVT);
- MVT RegisterVT = RegVTs[Value];
+ EVT RegisterVT = RegVTs[Value];
getCopyToParts(DAG, dl, Val.getValue(Val.getResNo() + Value),
&Parts[Part], NumParts, RegisterVT);
@@ -4715,7 +4715,7 @@
// = op c3, ..., f2
Chain = Chains[NumRegs-1];
else
- Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Chains[0], NumRegs);
+ Chain = DAG.getNode(ISD::TokenFactor, dl, EVT::Other, &Chains[0], NumRegs);
}
/// AddInlineAsmOperands - Add this value to the specified inlineasm node
@@ -4725,7 +4725,7 @@
bool HasMatching,unsigned MatchingIdx,
SelectionDAG &DAG,
std::vector<SDValue> &Ops) const {
- MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
+ EVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
assert(Regs.size() < (1 << 13) && "Too many inline asm outputs!");
unsigned Flag = Code | (Regs.size() << 3);
if (HasMatching)
@@ -4733,7 +4733,7 @@
Ops.push_back(DAG.getTargetConstant(Flag, IntPtrTy));
for (unsigned Value = 0, Reg = 0, e = ValueVTs.size(); Value != e; ++Value) {
unsigned NumRegs = TLI->getNumRegisters(ValueVTs[Value]);
- MVT RegisterVT = RegVTs[Value];
+ EVT RegisterVT = RegVTs[Value];
for (unsigned i = 0; i != NumRegs; ++i) {
assert(Reg < Regs.size() && "Mismatch in # registers expected");
Ops.push_back(DAG.getRegister(Regs[Reg++], RegisterVT));
@@ -4748,11 +4748,11 @@
isAllocatableRegister(unsigned Reg, MachineFunction &MF,
const TargetLowering &TLI,
const TargetRegisterInfo *TRI) {
- MVT FoundVT = MVT::Other;
+ EVT FoundVT = EVT::Other;
const TargetRegisterClass *FoundRC = 0;
for (TargetRegisterInfo::regclass_iterator RCI = TRI->regclass_begin(),
E = TRI->regclass_end(); RCI != E; ++RCI) {
- MVT ThisVT = MVT::Other;
+ EVT ThisVT = EVT::Other;
const TargetRegisterClass *RC = *RCI;
// If none of the the value types for this register class are valid, we
@@ -4763,14 +4763,14 @@
// If we have already found this register in a different register class,
// choose the one with the largest VT specified. For example, on
// PowerPC, we favor f64 register classes over f32.
- if (FoundVT == MVT::Other || FoundVT.bitsLT(*I)) {
+ if (FoundVT == EVT::Other || FoundVT.bitsLT(*I)) {
ThisVT = *I;
break;
}
}
}
- if (ThisVT == MVT::Other) continue;
+ if (ThisVT == EVT::Other) continue;
// NOTE: This isn't ideal. In particular, this might allocate the
// frame pointer in functions that need it (due to them not being taken
@@ -4825,12 +4825,12 @@
}
}
- /// getCallOperandValMVT - Return the MVT of the Value* that this operand
+ /// getCallOperandValEVT - Return the EVT of the Value* that this operand
/// corresponds to. If there is no Value* for this operand, it returns
- /// MVT::Other.
- MVT getCallOperandValMVT(const TargetLowering &TLI,
+ /// EVT::Other.
+ EVT getCallOperandValEVT(const TargetLowering &TLI,
const TargetData *TD) const {
- if (CallOperandVal == 0) return MVT::Other;
+ if (CallOperandVal == 0) return EVT::Other;
if (isa<BasicBlock>(CallOperandVal))
return TLI.getPointerTy();
@@ -4923,16 +4923,16 @@
OpInfo.ConstraintVT);
unsigned NumRegs = 1;
- if (OpInfo.ConstraintVT != MVT::Other) {
+ if (OpInfo.ConstraintVT != EVT::Other) {
// If this is a FP input in an integer register (or visa versa) insert a bit
// cast of the input value. More generally, handle any case where the input
// value disagrees with the register class we plan to stick this in.
if (OpInfo.Type == InlineAsm::isInput &&
PhysReg.second && !PhysReg.second->hasType(OpInfo.ConstraintVT)) {
- // Try to convert to the first MVT that the reg class contains. If the
+ // Try to convert to the first EVT that the reg class contains. If the
// types are identical size, use a bitcast to convert (e.g. two differing
// vector types).
- MVT RegVT = *PhysReg.second->vt_begin();
+ EVT RegVT = *PhysReg.second->vt_begin();
if (RegVT.getSizeInBits() == OpInfo.ConstraintVT.getSizeInBits()) {
OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
RegVT, OpInfo.CallOperand);
@@ -4942,7 +4942,7 @@
// bitcast to the corresponding integer type. This turns an f64 value
// into i64, which can be passed with two i32 values on a 32-bit
// machine.
- RegVT = MVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
+ RegVT = EVT::getIntegerVT(OpInfo.ConstraintVT.getSizeInBits());
OpInfo.CallOperand = DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(),
RegVT, OpInfo.CallOperand);
OpInfo.ConstraintVT = RegVT;
@@ -4952,14 +4952,14 @@
NumRegs = TLI.getNumRegisters(OpInfo.ConstraintVT);
}
- MVT RegVT;
- MVT ValueVT = OpInfo.ConstraintVT;
+ EVT RegVT;
+ EVT ValueVT = OpInfo.ConstraintVT;
// If this is a constraint for a specific physical register, like {r17},
// assign it now.
if (unsigned AssignedReg = PhysReg.first) {
const TargetRegisterClass *RC = PhysReg.second;
- if (OpInfo.ConstraintVT == MVT::Other)
+ if (OpInfo.ConstraintVT == EVT::Other)
ValueVT = *RC->vt_begin();
// Get the actual register value type. This is important, because the user
@@ -4993,7 +4993,7 @@
// for this reference.
if (const TargetRegisterClass *RC = PhysReg.second) {
RegVT = *RC->vt_begin();
- if (OpInfo.ConstraintVT == MVT::Other)
+ if (OpInfo.ConstraintVT == EVT::Other)
ValueVT = RegVT;
// Create the appropriate number of virtual registers.
@@ -5107,7 +5107,7 @@
ConstraintOperands.push_back(SDISelAsmOperandInfo(ConstraintInfos[i]));
SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
- MVT OpVT = MVT::Other;
+ EVT OpVT = EVT::Other;
// Compute the value type for each operand.
switch (OpInfo.Type) {
@@ -5149,7 +5149,7 @@
OpInfo.CallOperand = getValue(OpInfo.CallOperandVal);
}
- OpVT = OpInfo.getCallOperandValMVT(TLI, TD);
+ OpVT = OpInfo.getCallOperandValEVT(TLI, TD);
}
OpInfo.ConstraintVT = OpVT;
@@ -5243,7 +5243,7 @@
std::vector<SDValue> AsmNodeOperands;
AsmNodeOperands.push_back(SDValue()); // reserve space for input chain
AsmNodeOperands.push_back(
- DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), MVT::Other));
+ DAG.getTargetExternalSymbol(IA->getAsmString().c_str(), EVT::Other));
// Loop over all of the inputs, copying the operand values into the
@@ -5336,7 +5336,7 @@
RegsForValue MatchedRegs;
MatchedRegs.TLI = &TLI;
MatchedRegs.ValueVTs.push_back(InOperandVal.getValueType());
- MVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
+ EVT RegVT = AsmNodeOperands[CurOp+1].getValueType();
MatchedRegs.RegVTs.push_back(RegVT);
MachineRegisterInfo &RegInfo = DAG.getMachineFunction().getRegInfo();
for (unsigned i = 0, e = InlineAsm::getNumOperandRegisters(OpFlag);
@@ -5431,7 +5431,7 @@
if (Flag.getNode()) AsmNodeOperands.push_back(Flag);
Chain = DAG.getNode(ISD::INLINEASM, getCurDebugLoc(),
- DAG.getVTList(MVT::Other, MVT::Flag),
+ DAG.getVTList(EVT::Other, EVT::Flag),
&AsmNodeOperands[0], AsmNodeOperands.size());
Flag = Chain.getValue(1);
@@ -5443,7 +5443,7 @@
// FIXME: Why don't we do this for inline asms with MRVs?
if (CS.getType()->isSingleValueType() && CS.getType()->isSized()) {
- MVT ResultType = TLI.getValueType(CS.getType());
+ EVT ResultType = TLI.getValueType(CS.getType());
// If any of the results of the inline asm is a vector, it may have the
// wrong width/num elts. This can happen for register classes that can
@@ -5492,7 +5492,7 @@
getValue(StoresToEmit[i].second),
StoresToEmit[i].second, 0));
if (!OutChains.empty())
- Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other,
+ Chain = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), EVT::Other,
&OutChains[0], OutChains.size());
DAG.setRoot(Chain);
}
@@ -5509,13 +5509,13 @@
uint64_t ElementSize = TD->getTypeAllocSize(I.getType()->getElementType());
if (ElementSize != 1) {
// Src is always 32-bits, make sure the constant fits.
- assert(Src.getValueType() == MVT::i32);
+ assert(Src.getValueType() == EVT::i32);
ElementSize = (uint32_t)ElementSize;
Src = DAG.getNode(ISD::MUL, getCurDebugLoc(), Src.getValueType(),
Src, DAG.getConstant(ElementSize, Src.getValueType()));
}
- MVT IntPtr = TLI.getPointerTy();
+ EVT IntPtr = TLI.getPointerTy();
if (IntPtr.bitsLT(Src.getValueType()))
Src = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), IntPtr, Src);
@@ -5548,7 +5548,7 @@
Entry.Node = getValue(I.getOperand(0));
Entry.Ty = TLI.getTargetData()->getIntPtrType();
Args.push_back(Entry);
- MVT IntPtr = TLI.getPointerTy();
+ EVT IntPtr = TLI.getPointerTy();
bool isTailCall = PerformTailCallOpt &&
isInTailCallPosition(&I, Attribute::None, TLI);
std::pair<SDValue,SDValue> Result =
@@ -5563,7 +5563,7 @@
void SelectionDAGLowering::visitVAStart(CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VASTART, getCurDebugLoc(),
- MVT::Other, getRoot(),
+ EVT::Other, getRoot(),
getValue(I.getOperand(1)),
DAG.getSrcValue(I.getOperand(1))));
}
@@ -5578,14 +5578,14 @@
void SelectionDAGLowering::visitVAEnd(CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VAEND, getCurDebugLoc(),
- MVT::Other, getRoot(),
+ EVT::Other, getRoot(),
getValue(I.getOperand(1)),
DAG.getSrcValue(I.getOperand(1))));
}
void SelectionDAGLowering::visitVACopy(CallInst &I) {
DAG.setRoot(DAG.getNode(ISD::VACOPY, getCurDebugLoc(),
- MVT::Other, getRoot(),
+ EVT::Other, getRoot(),
getValue(I.getOperand(1)),
getValue(I.getOperand(2)),
DAG.getSrcValue(I.getOperand(1)),
@@ -5611,12 +5611,12 @@
// Handle all of the outgoing arguments.
SmallVector<ISD::OutputArg, 32> Outs;
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(*this, Args[i].Ty, ValueVTs);
for (unsigned Value = 0, NumValues = ValueVTs.size();
Value != NumValues; ++Value) {
- MVT VT = ValueVTs[Value];
- const Type *ArgTy = VT.getTypeForMVT();
+ EVT VT = ValueVTs[Value];
+ const Type *ArgTy = VT.getTypeForEVT();
SDValue Op = SDValue(Args[i].Node.getNode(),
Args[i].Node.getResNo() + Value);
ISD::ArgFlagsTy Flags;
@@ -5648,7 +5648,7 @@
Flags.setNest();
Flags.setOrigAlign(OriginalAlignment);
- MVT PartVT = getRegisterType(VT);
+ EVT PartVT = getRegisterType(VT);
unsigned NumParts = getNumRegisters(VT);
SmallVector<SDValue, 4> Parts(NumParts);
ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
@@ -5675,11 +5675,11 @@
// Handle the incoming return values from the call.
SmallVector<ISD::InputArg, 32> Ins;
- SmallVector<MVT, 4> RetTys;
+ SmallVector<EVT, 4> RetTys;
ComputeValueVTs(*this, RetTy, RetTys);
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
- MVT VT = RetTys[I];
- MVT RegisterVT = getRegisterType(VT);
+ EVT VT = RetTys[I];
+ EVT RegisterVT = getRegisterType(VT);
unsigned NumRegs = getNumRegisters(VT);
for (unsigned i = 0; i != NumRegs; ++i) {
ISD::InputArg MyFlags;
@@ -5706,7 +5706,7 @@
Outs, Ins, dl, DAG, InVals);
// Verify that the target's LowerCall behaved as expected.
- assert(Chain.getNode() && Chain.getValueType() == MVT::Other &&
+ assert(Chain.getNode() && Chain.getValueType() == EVT::Other &&
"LowerCall didn't return a valid chain!");
assert((!isTailCall || InVals.empty()) &&
"LowerCall emitted a return value for a tail call!");
@@ -5738,8 +5738,8 @@
SmallVector<SDValue, 4> ReturnValues;
unsigned CurReg = 0;
for (unsigned I = 0, E = RetTys.size(); I != E; ++I) {
- MVT VT = RetTys[I];
- MVT RegisterVT = getRegisterType(VT);
+ EVT VT = RetTys[I];
+ EVT RegisterVT = getRegisterType(VT);
unsigned NumRegs = getNumRegisters(VT);
SDValue ReturnValue =
@@ -5805,13 +5805,13 @@
unsigned Idx = 1;
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end();
I != E; ++I, ++Idx) {
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, I->getType(), ValueVTs);
bool isArgValueUsed = !I->use_empty();
for (unsigned Value = 0, NumValues = ValueVTs.size();
Value != NumValues; ++Value) {
- MVT VT = ValueVTs[Value];
- const Type *ArgTy = VT.getTypeForMVT();
+ EVT VT = ValueVTs[Value];
+ const Type *ArgTy = VT.getTypeForEVT();
ISD::ArgFlagsTy Flags;
unsigned OriginalAlignment =
TD->getABITypeAlignment(ArgTy);
@@ -5841,7 +5841,7 @@
Flags.setNest();
Flags.setOrigAlign(OriginalAlignment);
- MVT RegisterVT = TLI.getRegisterType(VT);
+ EVT RegisterVT = TLI.getRegisterType(VT);
unsigned NumRegs = TLI.getNumRegisters(VT);
for (unsigned i = 0; i != NumRegs; ++i) {
ISD::InputArg MyFlags(Flags, RegisterVT, isArgValueUsed);
@@ -5862,7 +5862,7 @@
dl, DAG, InVals);
// Verify that the target's LowerFormalArguments behaved as expected.
- assert(NewRoot.getNode() && NewRoot.getValueType() == MVT::Other &&
+ assert(NewRoot.getNode() && NewRoot.getValueType() == EVT::Other &&
"LowerFormalArguments didn't return a valid chain!");
assert(InVals.size() == Ins.size() &&
"LowerFormalArguments didn't emit the correct number of values!");
@@ -5882,12 +5882,12 @@
for (Function::arg_iterator I = F.arg_begin(), E = F.arg_end(); I != E;
++I, ++Idx) {
SmallVector<SDValue, 4> ArgValues;
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, I->getType(), ValueVTs);
unsigned NumValues = ValueVTs.size();
for (unsigned Value = 0; Value != NumValues; ++Value) {
- MVT VT = ValueVTs[Value];
- MVT PartVT = TLI.getRegisterType(VT);
+ EVT VT = ValueVTs[Value];
+ EVT PartVT = TLI.getRegisterType(VT);
unsigned NumParts = TLI.getNumRegisters(VT);
if (!I->use_empty()) {
@@ -5975,10 +5975,10 @@
// Remember that this register needs to added to the machine PHI node as
// the input for this MBB.
- SmallVector<MVT, 4> ValueVTs;
+ SmallVector<EVT, 4> ValueVTs;
ComputeValueVTs(TLI, PN->getType(), ValueVTs);
for (unsigned vti = 0, vte = ValueVTs.size(); vti != vte; ++vti) {
- MVT VT = ValueVTs[vti];
+ EVT VT = ValueVTs[vti];
unsigned NumRegisters = TLI.getNumRegisters(VT);
for (unsigned i = 0, e = NumRegisters; i != e; ++i)
SDL->PHINodesToUpdate.push_back(std::make_pair(MBBI++, Reg+i));
@@ -6029,10 +6029,10 @@
// own moves. Second, this check is necessary becuase FastISel doesn't
// use CreateRegForValue to create registers, so it always creates
// exactly one register for each non-void instruction.
- MVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
- if (VT == MVT::Other || !TLI.isTypeLegal(VT)) {
- // Promote MVT::i1.
- if (VT == MVT::i1)
+ EVT VT = TLI.getValueType(PN->getType(), /*AllowUnknown=*/true);
+ if (VT == EVT::Other || !TLI.isTypeLegal(VT)) {
+ // Promote EVT::i1.
+ if (VT == EVT::i1)
VT = TLI.getTypeToTransformTo(VT);
else {
SDL->PHINodesToUpdate.resize(OrigNumPHINodesToUpdate);
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
index 379ced9..9a079d6 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.h
@@ -117,7 +117,7 @@
SmallSet<Instruction*, 8> CatchInfoFound;
#endif
- unsigned MakeReg(MVT VT);
+ unsigned MakeReg(EVT VT);
/// isExportedInst - Return true if the specified value is an instruction
/// exported from its block.
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index b02fbea..97bb3b3 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -283,7 +283,7 @@
delete FuncInfo;
}
-unsigned SelectionDAGISel::MakeReg(MVT VT) {
+unsigned SelectionDAGISel::MakeReg(EVT VT) {
return RegInfo->createVirtualRegister(TLI.getRegClassFor(VT));
}
@@ -421,7 +421,7 @@
// Otherwise, add all chain operands to the worklist.
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i)
- if (N->getOperand(i).getValueType() == MVT::Other)
+ if (N->getOperand(i).getValueType() == EVT::Other)
Worklist.push_back(N->getOperand(i).getNode());
// If this is a CopyToReg with a vreg dest, process it.
@@ -434,7 +434,7 @@
// Ignore non-scalar or non-integer values.
SDValue Src = N->getOperand(2);
- MVT SrcVT = Src.getValueType();
+ EVT SrcVT = Src.getValueType();
if (!SrcVT.isInteger() || SrcVT.isVector())
continue;
@@ -1098,7 +1098,7 @@
Ops.push_back(InOps[1]); // input asm string.
unsigned i = 2, e = InOps.size();
- if (InOps[e-1].getValueType() == MVT::Flag)
+ if (InOps[e-1].getValueType() == EVT::Flag)
--e; // Don't process a flag operand if it is here.
while (i != e) {
@@ -1119,7 +1119,7 @@
}
// Add this to the output node.
- MVT IntPtrTy = TLI.getPointerTy();
+ EVT IntPtrTy = TLI.getPointerTy();
Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size()<< 3),
IntPtrTy));
Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
@@ -1132,7 +1132,7 @@
Ops.push_back(InOps.back());
}
-/// findFlagUse - Return use of MVT::Flag value produced by the specified
+/// findFlagUse - Return use of EVT::Flag value produced by the specified
/// SDNode.
///
static SDNode *findFlagUse(SDNode *N) {
@@ -1235,8 +1235,8 @@
// Fold. But since Fold and FU are flagged together, this will create
// a cycle in the scheduling graph.
- MVT VT = Root->getValueType(Root->getNumValues()-1);
- while (VT == MVT::Flag) {
+ EVT VT = Root->getValueType(Root->getNumValues()-1);
+ while (VT == EVT::Flag) {
SDNode *FU = findFlagUse(Root);
if (FU == NULL)
break;
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index 386d732..ef45110 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
@@ -44,7 +44,7 @@
}
static std::string getEdgeDestLabel(const void *Node, unsigned i) {
- return ((const SDNode *) Node)->getValueType(i).getMVTString();
+ return ((const SDNode *) Node)->getValueType(i).getEVTString();
}
/// edgeTargetsEdgeSource - This method returns true if this outgoing edge
@@ -84,10 +84,10 @@
template<typename EdgeIter>
static std::string getEdgeAttributes(const void *Node, EdgeIter EI) {
SDValue Op = EI.getNode()->getOperand(EI.getOperand());
- MVT VT = Op.getValueType();
- if (VT == MVT::Flag)
+ EVT VT = Op.getValueType();
+ if (VT == EVT::Flag)
return "color=red,style=bold";
- else if (VT == MVT::Other)
+ else if (VT == EVT::Other)
return "color=blue,style=dashed";
return "";
}
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 7d7afb2..c7ddf0a 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -249,9 +249,9 @@
/// getFPEXT - Return the FPEXT_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
-RTLIB::Libcall RTLIB::getFPEXT(MVT OpVT, MVT RetVT) {
- if (OpVT == MVT::f32) {
- if (RetVT == MVT::f64)
+RTLIB::Libcall RTLIB::getFPEXT(EVT OpVT, EVT RetVT) {
+ if (OpVT == EVT::f32) {
+ if (RetVT == EVT::f64)
return FPEXT_F32_F64;
}
return UNKNOWN_LIBCALL;
@@ -259,18 +259,18 @@
/// getFPROUND - Return the FPROUND_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
-RTLIB::Libcall RTLIB::getFPROUND(MVT OpVT, MVT RetVT) {
- if (RetVT == MVT::f32) {
- if (OpVT == MVT::f64)
+RTLIB::Libcall RTLIB::getFPROUND(EVT OpVT, EVT RetVT) {
+ if (RetVT == EVT::f32) {
+ if (OpVT == EVT::f64)
return FPROUND_F64_F32;
- if (OpVT == MVT::f80)
+ if (OpVT == EVT::f80)
return FPROUND_F80_F32;
- if (OpVT == MVT::ppcf128)
+ if (OpVT == EVT::ppcf128)
return FPROUND_PPCF128_F32;
- } else if (RetVT == MVT::f64) {
- if (OpVT == MVT::f80)
+ } else if (RetVT == EVT::f64) {
+ if (OpVT == EVT::f80)
return FPROUND_F80_F64;
- if (OpVT == MVT::ppcf128)
+ if (OpVT == EVT::ppcf128)
return FPROUND_PPCF128_F64;
}
return UNKNOWN_LIBCALL;
@@ -278,38 +278,38 @@
/// getFPTOSINT - Return the FPTOSINT_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
-RTLIB::Libcall RTLIB::getFPTOSINT(MVT OpVT, MVT RetVT) {
- if (OpVT == MVT::f32) {
- if (RetVT == MVT::i8)
+RTLIB::Libcall RTLIB::getFPTOSINT(EVT OpVT, EVT RetVT) {
+ if (OpVT == EVT::f32) {
+ if (RetVT == EVT::i8)
return FPTOSINT_F32_I8;
- if (RetVT == MVT::i16)
+ if (RetVT == EVT::i16)
return FPTOSINT_F32_I16;
- if (RetVT == MVT::i32)
+ if (RetVT == EVT::i32)
return FPTOSINT_F32_I32;
- if (RetVT == MVT::i64)
+ if (RetVT == EVT::i64)
return FPTOSINT_F32_I64;
- if (RetVT == MVT::i128)
+ if (RetVT == EVT::i128)
return FPTOSINT_F32_I128;
- } else if (OpVT == MVT::f64) {
- if (RetVT == MVT::i32)
+ } else if (OpVT == EVT::f64) {
+ if (RetVT == EVT::i32)
return FPTOSINT_F64_I32;
- if (RetVT == MVT::i64)
+ if (RetVT == EVT::i64)
return FPTOSINT_F64_I64;
- if (RetVT == MVT::i128)
+ if (RetVT == EVT::i128)
return FPTOSINT_F64_I128;
- } else if (OpVT == MVT::f80) {
- if (RetVT == MVT::i32)
+ } else if (OpVT == EVT::f80) {
+ if (RetVT == EVT::i32)
return FPTOSINT_F80_I32;
- if (RetVT == MVT::i64)
+ if (RetVT == EVT::i64)
return FPTOSINT_F80_I64;
- if (RetVT == MVT::i128)
+ if (RetVT == EVT::i128)
return FPTOSINT_F80_I128;
- } else if (OpVT == MVT::ppcf128) {
- if (RetVT == MVT::i32)
+ } else if (OpVT == EVT::ppcf128) {
+ if (RetVT == EVT::i32)
return FPTOSINT_PPCF128_I32;
- if (RetVT == MVT::i64)
+ if (RetVT == EVT::i64)
return FPTOSINT_PPCF128_I64;
- if (RetVT == MVT::i128)
+ if (RetVT == EVT::i128)
return FPTOSINT_PPCF128_I128;
}
return UNKNOWN_LIBCALL;
@@ -317,38 +317,38 @@
/// getFPTOUINT - Return the FPTOUINT_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
-RTLIB::Libcall RTLIB::getFPTOUINT(MVT OpVT, MVT RetVT) {
- if (OpVT == MVT::f32) {
- if (RetVT == MVT::i8)
+RTLIB::Libcall RTLIB::getFPTOUINT(EVT OpVT, EVT RetVT) {
+ if (OpVT == EVT::f32) {
+ if (RetVT == EVT::i8)
return FPTOUINT_F32_I8;
- if (RetVT == MVT::i16)
+ if (RetVT == EVT::i16)
return FPTOUINT_F32_I16;
- if (RetVT == MVT::i32)
+ if (RetVT == EVT::i32)
return FPTOUINT_F32_I32;
- if (RetVT == MVT::i64)
+ if (RetVT == EVT::i64)
return FPTOUINT_F32_I64;
- if (RetVT == MVT::i128)
+ if (RetVT == EVT::i128)
return FPTOUINT_F32_I128;
- } else if (OpVT == MVT::f64) {
- if (RetVT == MVT::i32)
+ } else if (OpVT == EVT::f64) {
+ if (RetVT == EVT::i32)
return FPTOUINT_F64_I32;
- if (RetVT == MVT::i64)
+ if (RetVT == EVT::i64)
return FPTOUINT_F64_I64;
- if (RetVT == MVT::i128)
+ if (RetVT == EVT::i128)
return FPTOUINT_F64_I128;
- } else if (OpVT == MVT::f80) {
- if (RetVT == MVT::i32)
+ } else if (OpVT == EVT::f80) {
+ if (RetVT == EVT::i32)
return FPTOUINT_F80_I32;
- if (RetVT == MVT::i64)
+ if (RetVT == EVT::i64)
return FPTOUINT_F80_I64;
- if (RetVT == MVT::i128)
+ if (RetVT == EVT::i128)
return FPTOUINT_F80_I128;
- } else if (OpVT == MVT::ppcf128) {
- if (RetVT == MVT::i32)
+ } else if (OpVT == EVT::ppcf128) {
+ if (RetVT == EVT::i32)
return FPTOUINT_PPCF128_I32;
- if (RetVT == MVT::i64)
+ if (RetVT == EVT::i64)
return FPTOUINT_PPCF128_I64;
- if (RetVT == MVT::i128)
+ if (RetVT == EVT::i128)
return FPTOUINT_PPCF128_I128;
}
return UNKNOWN_LIBCALL;
@@ -356,33 +356,33 @@
/// getSINTTOFP - Return the SINTTOFP_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
-RTLIB::Libcall RTLIB::getSINTTOFP(MVT OpVT, MVT RetVT) {
- if (OpVT == MVT::i32) {
- if (RetVT == MVT::f32)
+RTLIB::Libcall RTLIB::getSINTTOFP(EVT OpVT, EVT RetVT) {
+ if (OpVT == EVT::i32) {
+ if (RetVT == EVT::f32)
return SINTTOFP_I32_F32;
- else if (RetVT == MVT::f64)
+ else if (RetVT == EVT::f64)
return SINTTOFP_I32_F64;
- else if (RetVT == MVT::f80)
+ else if (RetVT == EVT::f80)
return SINTTOFP_I32_F80;
- else if (RetVT == MVT::ppcf128)
+ else if (RetVT == EVT::ppcf128)
return SINTTOFP_I32_PPCF128;
- } else if (OpVT == MVT::i64) {
- if (RetVT == MVT::f32)
+ } else if (OpVT == EVT::i64) {
+ if (RetVT == EVT::f32)
return SINTTOFP_I64_F32;
- else if (RetVT == MVT::f64)
+ else if (RetVT == EVT::f64)
return SINTTOFP_I64_F64;
- else if (RetVT == MVT::f80)
+ else if (RetVT == EVT::f80)
return SINTTOFP_I64_F80;
- else if (RetVT == MVT::ppcf128)
+ else if (RetVT == EVT::ppcf128)
return SINTTOFP_I64_PPCF128;
- } else if (OpVT == MVT::i128) {
- if (RetVT == MVT::f32)
+ } else if (OpVT == EVT::i128) {
+ if (RetVT == EVT::f32)
return SINTTOFP_I128_F32;
- else if (RetVT == MVT::f64)
+ else if (RetVT == EVT::f64)
return SINTTOFP_I128_F64;
- else if (RetVT == MVT::f80)
+ else if (RetVT == EVT::f80)
return SINTTOFP_I128_F80;
- else if (RetVT == MVT::ppcf128)
+ else if (RetVT == EVT::ppcf128)
return SINTTOFP_I128_PPCF128;
}
return UNKNOWN_LIBCALL;
@@ -390,33 +390,33 @@
/// getUINTTOFP - Return the UINTTOFP_*_* value for the given types, or
/// UNKNOWN_LIBCALL if there is none.
-RTLIB::Libcall RTLIB::getUINTTOFP(MVT OpVT, MVT RetVT) {
- if (OpVT == MVT::i32) {
- if (RetVT == MVT::f32)
+RTLIB::Libcall RTLIB::getUINTTOFP(EVT OpVT, EVT RetVT) {
+ if (OpVT == EVT::i32) {
+ if (RetVT == EVT::f32)
return UINTTOFP_I32_F32;
- else if (RetVT == MVT::f64)
+ else if (RetVT == EVT::f64)
return UINTTOFP_I32_F64;
- else if (RetVT == MVT::f80)
+ else if (RetVT == EVT::f80)
return UINTTOFP_I32_F80;
- else if (RetVT == MVT::ppcf128)
+ else if (RetVT == EVT::ppcf128)
return UINTTOFP_I32_PPCF128;
- } else if (OpVT == MVT::i64) {
- if (RetVT == MVT::f32)
+ } else if (OpVT == EVT::i64) {
+ if (RetVT == EVT::f32)
return UINTTOFP_I64_F32;
- else if (RetVT == MVT::f64)
+ else if (RetVT == EVT::f64)
return UINTTOFP_I64_F64;
- else if (RetVT == MVT::f80)
+ else if (RetVT == EVT::f80)
return UINTTOFP_I64_F80;
- else if (RetVT == MVT::ppcf128)
+ else if (RetVT == EVT::ppcf128)
return UINTTOFP_I64_PPCF128;
- } else if (OpVT == MVT::i128) {
- if (RetVT == MVT::f32)
+ } else if (OpVT == EVT::i128) {
+ if (RetVT == EVT::f32)
return UINTTOFP_I128_F32;
- else if (RetVT == MVT::f64)
+ else if (RetVT == EVT::f64)
return UINTTOFP_I128_F64;
- else if (RetVT == MVT::f80)
+ else if (RetVT == EVT::f80)
return UINTTOFP_I128_F80;
- else if (RetVT == MVT::ppcf128)
+ else if (RetVT == EVT::ppcf128)
return UINTTOFP_I128_PPCF128;
}
return UNKNOWN_LIBCALL;
@@ -456,48 +456,48 @@
memset(CondCodeActions, 0, sizeof(CondCodeActions));
// Set default actions for various operations.
- for (unsigned VT = 0; VT != (unsigned)MVT::LAST_VALUETYPE; ++VT) {
+ for (unsigned VT = 0; VT != (unsigned)EVT::LAST_VALUETYPE; ++VT) {
// Default all indexed load / store to expand.
for (unsigned IM = (unsigned)ISD::PRE_INC;
IM != (unsigned)ISD::LAST_INDEXED_MODE; ++IM) {
- setIndexedLoadAction(IM, (MVT::SimpleValueType)VT, Expand);
- setIndexedStoreAction(IM, (MVT::SimpleValueType)VT, Expand);
+ setIndexedLoadAction(IM, (EVT::SimpleValueType)VT, Expand);
+ setIndexedStoreAction(IM, (EVT::SimpleValueType)VT, Expand);
}
// These operations default to expand.
- setOperationAction(ISD::FGETSIGN, (MVT::SimpleValueType)VT, Expand);
- setOperationAction(ISD::CONCAT_VECTORS, (MVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::FGETSIGN, (EVT::SimpleValueType)VT, Expand);
+ setOperationAction(ISD::CONCAT_VECTORS, (EVT::SimpleValueType)VT, Expand);
}
// Most targets ignore the @llvm.prefetch intrinsic.
- setOperationAction(ISD::PREFETCH, MVT::Other, Expand);
+ setOperationAction(ISD::PREFETCH, EVT::Other, Expand);
// ConstantFP nodes default to expand. Targets can either change this to
// Legal, in which case all fp constants are legal, or use addLegalFPImmediate
// to optimize expansions for certain constants.
- setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
- setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
- setOperationAction(ISD::ConstantFP, MVT::f80, Expand);
+ setOperationAction(ISD::ConstantFP, EVT::f32, Expand);
+ setOperationAction(ISD::ConstantFP, EVT::f64, Expand);
+ setOperationAction(ISD::ConstantFP, EVT::f80, Expand);
// These library functions default to expand.
- setOperationAction(ISD::FLOG , MVT::f64, Expand);
- setOperationAction(ISD::FLOG2, MVT::f64, Expand);
- setOperationAction(ISD::FLOG10,MVT::f64, Expand);
- setOperationAction(ISD::FEXP , MVT::f64, Expand);
- setOperationAction(ISD::FEXP2, MVT::f64, Expand);
- setOperationAction(ISD::FLOG , MVT::f32, Expand);
- setOperationAction(ISD::FLOG2, MVT::f32, Expand);
- setOperationAction(ISD::FLOG10,MVT::f32, Expand);
- setOperationAction(ISD::FEXP , MVT::f32, Expand);
- setOperationAction(ISD::FEXP2, MVT::f32, Expand);
+ setOperationAction(ISD::FLOG , EVT::f64, Expand);
+ setOperationAction(ISD::FLOG2, EVT::f64, Expand);
+ setOperationAction(ISD::FLOG10,EVT::f64, Expand);
+ setOperationAction(ISD::FEXP , EVT::f64, Expand);
+ setOperationAction(ISD::FEXP2, EVT::f64, Expand);
+ setOperationAction(ISD::FLOG , EVT::f32, Expand);
+ setOperationAction(ISD::FLOG2, EVT::f32, Expand);
+ setOperationAction(ISD::FLOG10,EVT::f32, Expand);
+ setOperationAction(ISD::FEXP , EVT::f32, Expand);
+ setOperationAction(ISD::FEXP2, EVT::f32, Expand);
// Default ISD::TRAP to expand (which turns it into abort).
- setOperationAction(ISD::TRAP, MVT::Other, Expand);
+ setOperationAction(ISD::TRAP, EVT::Other, Expand);
IsLittleEndian = TD->isLittleEndian();
UsesGlobalOffsetTable = false;
ShiftAmountTy = PointerTy = getValueType(TD->getIntPtrType()).getSimpleVT();
- memset(RegClassForVT, 0,MVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
+ memset(RegClassForVT, 0,EVT::LAST_VALUETYPE*sizeof(TargetRegisterClass*));
memset(TargetDAGCombineArray, 0, array_lengthof(TargetDAGCombineArray));
maxStoresPerMemset = maxStoresPerMemcpy = maxStoresPerMemmove = 8;
allowUnalignedMemoryAccesses = false;
@@ -524,7 +524,7 @@
// Tell Legalize whether the assembler supports DEBUG_LOC.
const TargetAsmInfo *TASM = TM.getTargetAsmInfo();
if (!TASM || !TASM->hasDotLocAndDotFile())
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, EVT::Other, Expand);
}
TargetLowering::~TargetLowering() {
@@ -534,31 +534,31 @@
/// computeRegisterProperties - Once all of the register classes are added,
/// this allows us to compute derived properties we expose.
void TargetLowering::computeRegisterProperties() {
- assert(MVT::LAST_VALUETYPE <= MVT::MAX_ALLOWED_VALUETYPE &&
+ assert(EVT::LAST_VALUETYPE <= EVT::MAX_ALLOWED_VALUETYPE &&
"Too many value types for ValueTypeActions to hold!");
// Everything defaults to needing one register.
- for (unsigned i = 0; i != MVT::LAST_VALUETYPE; ++i) {
+ for (unsigned i = 0; i != EVT::LAST_VALUETYPE; ++i) {
NumRegistersForVT[i] = 1;
- RegisterTypeForVT[i] = TransformToType[i] = (MVT::SimpleValueType)i;
+ RegisterTypeForVT[i] = TransformToType[i] = (EVT::SimpleValueType)i;
}
// ...except isVoid, which doesn't need any registers.
- NumRegistersForVT[MVT::isVoid] = 0;
+ NumRegistersForVT[EVT::isVoid] = 0;
// Find the largest integer register class.
- unsigned LargestIntReg = MVT::LAST_INTEGER_VALUETYPE;
+ unsigned LargestIntReg = EVT::LAST_INTEGER_VALUETYPE;
for (; RegClassForVT[LargestIntReg] == 0; --LargestIntReg)
- assert(LargestIntReg != MVT::i1 && "No integer registers defined!");
+ assert(LargestIntReg != EVT::i1 && "No integer registers defined!");
// Every integer value type larger than this largest register takes twice as
// many registers to represent as the previous ValueType.
for (unsigned ExpandedReg = LargestIntReg + 1; ; ++ExpandedReg) {
- MVT EVT = (MVT::SimpleValueType)ExpandedReg;
+ EVT EVT = (EVT::SimpleValueType)ExpandedReg;
if (!EVT.isInteger())
break;
NumRegistersForVT[ExpandedReg] = 2*NumRegistersForVT[ExpandedReg-1];
- RegisterTypeForVT[ExpandedReg] = (MVT::SimpleValueType)LargestIntReg;
- TransformToType[ExpandedReg] = (MVT::SimpleValueType)(ExpandedReg - 1);
+ RegisterTypeForVT[ExpandedReg] = (EVT::SimpleValueType)LargestIntReg;
+ TransformToType[ExpandedReg] = (EVT::SimpleValueType)(ExpandedReg - 1);
ValueTypeActions.setTypeAction(EVT, Expand);
}
@@ -566,56 +566,56 @@
// register to see which ones need promotion.
unsigned LegalIntReg = LargestIntReg;
for (unsigned IntReg = LargestIntReg - 1;
- IntReg >= (unsigned)MVT::i1; --IntReg) {
- MVT IVT = (MVT::SimpleValueType)IntReg;
+ IntReg >= (unsigned)EVT::i1; --IntReg) {
+ EVT IVT = (EVT::SimpleValueType)IntReg;
if (isTypeLegal(IVT)) {
LegalIntReg = IntReg;
} else {
RegisterTypeForVT[IntReg] = TransformToType[IntReg] =
- (MVT::SimpleValueType)LegalIntReg;
+ (EVT::SimpleValueType)LegalIntReg;
ValueTypeActions.setTypeAction(IVT, Promote);
}
}
// ppcf128 type is really two f64's.
- if (!isTypeLegal(MVT::ppcf128)) {
- NumRegistersForVT[MVT::ppcf128] = 2*NumRegistersForVT[MVT::f64];
- RegisterTypeForVT[MVT::ppcf128] = MVT::f64;
- TransformToType[MVT::ppcf128] = MVT::f64;
- ValueTypeActions.setTypeAction(MVT::ppcf128, Expand);
+ if (!isTypeLegal(EVT::ppcf128)) {
+ NumRegistersForVT[EVT::ppcf128] = 2*NumRegistersForVT[EVT::f64];
+ RegisterTypeForVT[EVT::ppcf128] = EVT::f64;
+ TransformToType[EVT::ppcf128] = EVT::f64;
+ ValueTypeActions.setTypeAction(EVT::ppcf128, Expand);
}
// Decide how to handle f64. If the target does not have native f64 support,
// expand it to i64 and we will be generating soft float library calls.
- if (!isTypeLegal(MVT::f64)) {
- NumRegistersForVT[MVT::f64] = NumRegistersForVT[MVT::i64];
- RegisterTypeForVT[MVT::f64] = RegisterTypeForVT[MVT::i64];
- TransformToType[MVT::f64] = MVT::i64;
- ValueTypeActions.setTypeAction(MVT::f64, Expand);
+ if (!isTypeLegal(EVT::f64)) {
+ NumRegistersForVT[EVT::f64] = NumRegistersForVT[EVT::i64];
+ RegisterTypeForVT[EVT::f64] = RegisterTypeForVT[EVT::i64];
+ TransformToType[EVT::f64] = EVT::i64;
+ ValueTypeActions.setTypeAction(EVT::f64, Expand);
}
// Decide how to handle f32. If the target does not have native support for
// f32, promote it to f64 if it is legal. Otherwise, expand it to i32.
- if (!isTypeLegal(MVT::f32)) {
- if (isTypeLegal(MVT::f64)) {
- NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::f64];
- RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::f64];
- TransformToType[MVT::f32] = MVT::f64;
- ValueTypeActions.setTypeAction(MVT::f32, Promote);
+ if (!isTypeLegal(EVT::f32)) {
+ if (isTypeLegal(EVT::f64)) {
+ NumRegistersForVT[EVT::f32] = NumRegistersForVT[EVT::f64];
+ RegisterTypeForVT[EVT::f32] = RegisterTypeForVT[EVT::f64];
+ TransformToType[EVT::f32] = EVT::f64;
+ ValueTypeActions.setTypeAction(EVT::f32, Promote);
} else {
- NumRegistersForVT[MVT::f32] = NumRegistersForVT[MVT::i32];
- RegisterTypeForVT[MVT::f32] = RegisterTypeForVT[MVT::i32];
- TransformToType[MVT::f32] = MVT::i32;
- ValueTypeActions.setTypeAction(MVT::f32, Expand);
+ NumRegistersForVT[EVT::f32] = NumRegistersForVT[EVT::i32];
+ RegisterTypeForVT[EVT::f32] = RegisterTypeForVT[EVT::i32];
+ TransformToType[EVT::f32] = EVT::i32;
+ ValueTypeActions.setTypeAction(EVT::f32, Expand);
}
}
// Loop over all of the vector value types to see which need transformations.
- for (unsigned i = MVT::FIRST_VECTOR_VALUETYPE;
- i <= (unsigned)MVT::LAST_VECTOR_VALUETYPE; ++i) {
- MVT VT = (MVT::SimpleValueType)i;
+ for (unsigned i = EVT::FIRST_VECTOR_VALUETYPE;
+ i <= (unsigned)EVT::LAST_VECTOR_VALUETYPE; ++i) {
+ EVT VT = (EVT::SimpleValueType)i;
if (!isTypeLegal(VT)) {
- MVT IntermediateVT, RegisterVT;
+ EVT IntermediateVT, RegisterVT;
unsigned NumIntermediates;
NumRegistersForVT[i] =
getVectorTypeBreakdown(VT,
@@ -625,10 +625,10 @@
// Determine if there is a legal wider type.
bool IsLegalWiderType = false;
- MVT EltVT = VT.getVectorElementType();
+ EVT EltVT = VT.getVectorElementType();
unsigned NElts = VT.getVectorNumElements();
- for (unsigned nVT = i+1; nVT <= MVT::LAST_VECTOR_VALUETYPE; ++nVT) {
- MVT SVT = (MVT::SimpleValueType)nVT;
+ for (unsigned nVT = i+1; nVT <= EVT::LAST_VECTOR_VALUETYPE; ++nVT) {
+ EVT SVT = (EVT::SimpleValueType)nVT;
if (isTypeLegal(SVT) && SVT.getVectorElementType() == EltVT &&
SVT.getVectorNumElements() > NElts) {
TransformToType[i] = SVT;
@@ -638,10 +638,10 @@
}
}
if (!IsLegalWiderType) {
- MVT NVT = VT.getPow2VectorType();
+ EVT NVT = VT.getPow2VectorType();
if (NVT == VT) {
// Type is already a power of 2. The default action is to split.
- TransformToType[i] = MVT::Other;
+ TransformToType[i] = EVT::Other;
ValueTypeActions.setTypeAction(VT, Expand);
} else {
TransformToType[i] = NVT;
@@ -657,27 +657,27 @@
}
-MVT::SimpleValueType TargetLowering::getSetCCResultType(MVT VT) const {
+EVT::SimpleValueType TargetLowering::getSetCCResultType(EVT VT) const {
return getValueType(TD->getIntPtrType()).getSimpleVT();
}
/// getVectorTypeBreakdown - Vector types are broken down into some number of
-/// legal first class types. For example, MVT::v8f32 maps to 2 MVT::v4f32
-/// with Altivec or SSE1, or 8 promoted MVT::f64 values with the X86 FP stack.
-/// Similarly, MVT::v2i64 turns into 4 MVT::i32 values with both PPC and X86.
+/// legal first class types. For example, EVT::v8f32 maps to 2 EVT::v4f32
+/// with Altivec or SSE1, or 8 promoted EVT::f64 values with the X86 FP stack.
+/// Similarly, EVT::v2i64 turns into 4 EVT::i32 values with both PPC and X86.
///
/// This method returns the number of registers needed, and the VT for each
/// register. It also returns the VT and quantity of the intermediate values
/// before they are promoted/expanded.
///
-unsigned TargetLowering::getVectorTypeBreakdown(MVT VT,
- MVT &IntermediateVT,
+unsigned TargetLowering::getVectorTypeBreakdown(EVT VT,
+ EVT &IntermediateVT,
unsigned &NumIntermediates,
- MVT &RegisterVT) const {
+ EVT &RegisterVT) const {
// Figure out the right, legal destination reg to copy into.
unsigned NumElts = VT.getVectorNumElements();
- MVT EltTy = VT.getVectorElementType();
+ EVT EltTy = VT.getVectorElementType();
unsigned NumVectorRegs = 1;
@@ -690,19 +690,19 @@
// Divide the input until we get to a supported size. This will always
// end with a scalar if the target doesn't support vectors.
- while (NumElts > 1 && !isTypeLegal(MVT::getVectorVT(EltTy, NumElts))) {
+ while (NumElts > 1 && !isTypeLegal(EVT::getVectorVT(EltTy, NumElts))) {
NumElts >>= 1;
NumVectorRegs <<= 1;
}
NumIntermediates = NumVectorRegs;
- MVT NewVT = MVT::getVectorVT(EltTy, NumElts);
+ EVT NewVT = EVT::getVectorVT(EltTy, NumElts);
if (!isTypeLegal(NewVT))
NewVT = EltTy;
IntermediateVT = NewVT;
- MVT DestVT = getRegisterType(NewVT);
+ EVT DestVT = getRegisterType(NewVT);
RegisterVT = DestVT;
if (DestVT.bitsLT(NewVT)) {
// Value is expanded, e.g. i64 -> i16.
@@ -718,16 +718,16 @@
/// getWidenVectorType: given a vector type, returns the type to widen to
/// (e.g., v7i8 to v8i8). If the vector type is legal, it returns itself.
-/// If there is no vector type that we want to widen to, returns MVT::Other
+/// If there is no vector type that we want to widen to, returns EVT::Other
/// When and where to widen is target dependent based on the cost of
/// scalarizing vs using the wider vector type.
-MVT TargetLowering::getWidenVectorType(MVT VT) const {
+EVT TargetLowering::getWidenVectorType(EVT VT) const {
assert(VT.isVector());
if (isTypeLegal(VT))
return VT;
// Default is not to widen until moved to LegalizeTypes
- return MVT::Other;
+ return EVT::Other;
}
/// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
@@ -788,7 +788,7 @@
// if we can expand it to have all bits set, do it
if (C->getAPIntValue().intersects(~Demanded)) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue New = DAG.getNode(Op.getOpcode(), dl, VT, Op.getOperand(0),
DAG.getConstant(Demanded &
C->getAPIntValue(),
@@ -829,7 +829,7 @@
if (!isPowerOf2_32(SmallVTBits))
SmallVTBits = NextPowerOf2(SmallVTBits);
for (; SmallVTBits < BitWidth; SmallVTBits = NextPowerOf2(SmallVTBits)) {
- MVT SmallVT = MVT::getIntegerVT(SmallVTBits);
+ EVT SmallVT = EVT::getIntegerVT(SmallVTBits);
if (TLI.isTruncateFree(Op.getValueType(), SmallVT) &&
TLI.isZExtFree(SmallVT, Op.getValueType())) {
// We found a type with free casts.
@@ -1015,7 +1015,7 @@
// e.g. (X | C1) ^ C2 --> (X | C1) & ~C2 iff (C1&C2) == C2
if ((NewMask & (KnownZero|KnownOne)) == NewMask) { // all known
if ((KnownOne & KnownOne2) == KnownOne) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue ANDC = TLO.DAG.getConstant(~KnownOne & NewMask, VT);
return TLO.CombineTo(Op, TLO.DAG.getNode(ISD::AND, dl, VT,
Op.getOperand(0), ANDC));
@@ -1030,7 +1030,7 @@
// if we can expand it to have all bits set, do it
if (Expanded.isAllOnesValue()) {
if (Expanded != C->getAPIntValue()) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
SDValue New = TLO.DAG.getNode(Op.getOpcode(), dl,VT, Op.getOperand(0),
TLO.DAG.getConstant(Expanded, VT));
return TLO.CombineTo(Op, New);
@@ -1106,7 +1106,7 @@
SDValue NewSA =
TLO.DAG.getConstant(Diff, Op.getOperand(1).getValueType());
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
return TLO.CombineTo(Op, TLO.DAG.getNode(Opc, dl, VT,
InOp.getOperand(0), NewSA));
}
@@ -1123,7 +1123,7 @@
break;
case ISD::SRL:
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
unsigned ShAmt = SA->getZExtValue();
unsigned VTSize = VT.getSizeInBits();
SDValue InOp = Op.getOperand(0);
@@ -1175,7 +1175,7 @@
Op.getOperand(0), Op.getOperand(1)));
if (ConstantSDNode *SA = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
- MVT VT = Op.getValueType();
+ EVT VT = Op.getValueType();
unsigned ShAmt = SA->getZExtValue();
// If the shift count is an invalid immediate, don't do anything.
@@ -1212,7 +1212,7 @@
}
break;
case ISD::SIGN_EXTEND_INREG: {
- MVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
+ EVT EVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
// Sign extension. Compute the demanded bits in the result that are not
// present in the input.
@@ -1279,7 +1279,7 @@
break;
}
case ISD::SIGN_EXTEND: {
- MVT InVT = Op.getOperand(0).getValueType();
+ EVT InVT = Op.getOperand(0).getValueType();
unsigned InBits = InVT.getSizeInBits();
APInt InMask = APInt::getLowBitsSet(BitWidth, InBits);
APInt InSignBit = APInt::getBitsSet(BitWidth, InBits - 1, InBits);
@@ -1378,7 +1378,7 @@
break;
}
case ISD::AssertZext: {
- MVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
+ EVT VT = cast<VTSDNode>(Op.getOperand(1))->getVT();
APInt InMask = APInt::getLowBitsSet(BitWidth,
VT.getSizeInBits());
if (SimplifyDemandedBits(Op.getOperand(0), InMask & NewMask,
@@ -1392,9 +1392,9 @@
#if 0
// If this is an FP->Int bitcast and if the sign bit is the only thing that
// is demanded, turn this into a FGETSIGN.
- if (NewMask == MVT::getIntegerVTSignBit(Op.getValueType()) &&
- MVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
- !MVT::isVector(Op.getOperand(0).getValueType())) {
+ if (NewMask == EVT::getIntegerVTSignBit(Op.getValueType()) &&
+ EVT::isFloatingPoint(Op.getOperand(0).getValueType()) &&
+ !EVT::isVector(Op.getOperand(0).getValueType())) {
// Only do this xform if FGETSIGN is valid or if before legalize.
if (!TLO.AfterLegalize ||
isOperationLegal(ISD::FGETSIGN, Op.getValueType())) {
@@ -1499,7 +1499,7 @@
// to handle some common cases.
// Fall back to ComputeMaskedBits to catch other known cases.
- MVT OpVT = Val.getValueType();
+ EVT OpVT = Val.getValueType();
unsigned BitWidth = OpVT.getSizeInBits();
APInt Mask = APInt::getAllOnesValue(BitWidth);
APInt KnownZero, KnownOne;
@@ -1511,7 +1511,7 @@
/// SimplifySetCC - Try to simplify a setcc built with the specified operands
/// and cc. If it is unable to simplify it, return a null SDValue.
SDValue
-TargetLowering::SimplifySetCC(MVT VT, SDValue N0, SDValue N1,
+TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
ISD::CondCode Cond, bool foldBooleans,
DAGCombinerInfo &DCI, DebugLoc dl) const {
SelectionDAG &DAG = DCI.DAG;
@@ -1597,9 +1597,9 @@
}
}
if (bestWidth) {
- MVT newVT = MVT::getIntegerVT(bestWidth);
+ EVT newVT = EVT::getIntegerVT(bestWidth);
if (newVT.isRound()) {
- MVT PtrType = Lod->getOperand(1).getValueType();
+ EVT PtrType = Lod->getOperand(1).getValueType();
SDValue Ptr = Lod->getBasePtr();
if (bestOffset != 0)
Ptr = DAG.getNode(ISD::ADD, dl, PtrType, Lod->getBasePtr(),
@@ -1653,7 +1653,7 @@
case ISD::SETUGE:
case ISD::SETULT:
case ISD::SETULE: {
- MVT newVT = N0.getOperand(0).getValueType();
+ EVT newVT = N0.getOperand(0).getValueType();
if (DCI.isBeforeLegalizeOps() ||
(isOperationLegal(ISD::SETCC, newVT) &&
getCondCodeAction(Cond, newVT)==Legal))
@@ -1667,9 +1667,9 @@
}
} else if (N0.getOpcode() == ISD::SIGN_EXTEND_INREG &&
(Cond == ISD::SETEQ || Cond == ISD::SETNE)) {
- MVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
+ EVT ExtSrcTy = cast<VTSDNode>(N0.getOperand(1))->getVT();
unsigned ExtSrcTyBits = ExtSrcTy.getSizeInBits();
- MVT ExtDstTy = N0.getValueType();
+ EVT ExtDstTy = N0.getValueType();
unsigned ExtDstTyBits = ExtDstTy.getSizeInBits();
// If the extended part has any inconsistent bits, it cannot ever
@@ -1681,7 +1681,7 @@
return DAG.getConstant(Cond == ISD::SETNE, VT);
SDValue ZextOp;
- MVT Op0Ty = N0.getOperand(0).getValueType();
+ EVT Op0Ty = N0.getOperand(0).getValueType();
if (Op0Ty == ExtSrcTy) {
ZextOp = N0.getOperand(0);
} else {
@@ -1822,7 +1822,7 @@
VT == N0.getValueType() && N0.getOpcode() == ISD::AND)
if (ConstantSDNode *AndRHS =
dyn_cast<ConstantSDNode>(N0.getOperand(1))) {
- MVT ShiftTy = DCI.isBeforeLegalize() ?
+ EVT ShiftTy = DCI.isBeforeLegalize() ?
getPointerTy() : getShiftAmountTy();
if (Cond == ISD::SETNE && C1 == 0) {// (X & 8) != 0 --> (X & 8) >> 3
// Perform the xform if the AND RHS is a single bit.
@@ -2010,46 +2010,46 @@
// Fold away ALL boolean setcc's.
SDValue Temp;
- if (N0.getValueType() == MVT::i1 && foldBooleans) {
+ if (N0.getValueType() == EVT::i1 && foldBooleans) {
switch (Cond) {
default: llvm_unreachable("Unknown integer setcc!");
case ISD::SETEQ: // X == Y -> ~(X^Y)
- Temp = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
- N0 = DAG.getNOT(dl, Temp, MVT::i1);
+ Temp = DAG.getNode(ISD::XOR, dl, EVT::i1, N0, N1);
+ N0 = DAG.getNOT(dl, Temp, EVT::i1);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETNE: // X != Y --> (X^Y)
- N0 = DAG.getNode(ISD::XOR, dl, MVT::i1, N0, N1);
+ N0 = DAG.getNode(ISD::XOR, dl, EVT::i1, N0, N1);
break;
case ISD::SETGT: // X >s Y --> X == 0 & Y == 1 --> ~X & Y
case ISD::SETULT: // X <u Y --> X == 0 & Y == 1 --> ~X & Y
- Temp = DAG.getNOT(dl, N0, MVT::i1);
- N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N1, Temp);
+ Temp = DAG.getNOT(dl, N0, EVT::i1);
+ N0 = DAG.getNode(ISD::AND, dl, EVT::i1, N1, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETLT: // X <s Y --> X == 1 & Y == 0 --> ~Y & X
case ISD::SETUGT: // X >u Y --> X == 1 & Y == 0 --> ~Y & X
- Temp = DAG.getNOT(dl, N1, MVT::i1);
- N0 = DAG.getNode(ISD::AND, dl, MVT::i1, N0, Temp);
+ Temp = DAG.getNOT(dl, N1, EVT::i1);
+ N0 = DAG.getNode(ISD::AND, dl, EVT::i1, N0, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETULE: // X <=u Y --> X == 0 | Y == 1 --> ~X | Y
case ISD::SETGE: // X >=s Y --> X == 0 | Y == 1 --> ~X | Y
- Temp = DAG.getNOT(dl, N0, MVT::i1);
- N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N1, Temp);
+ Temp = DAG.getNOT(dl, N0, EVT::i1);
+ N0 = DAG.getNode(ISD::OR, dl, EVT::i1, N1, Temp);
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(Temp.getNode());
break;
case ISD::SETUGE: // X >=u Y --> X == 1 | Y == 0 --> ~Y | X
case ISD::SETLE: // X <=s Y --> X == 1 | Y == 0 --> ~Y | X
- Temp = DAG.getNOT(dl, N1, MVT::i1);
- N0 = DAG.getNode(ISD::OR, dl, MVT::i1, N0, Temp);
+ Temp = DAG.getNOT(dl, N1, EVT::i1);
+ N0 = DAG.getNode(ISD::OR, dl, EVT::i1, N0, Temp);
break;
}
- if (VT != MVT::i1) {
+ if (VT != EVT::i1) {
if (!DCI.isCalledByLegalizer())
DCI.AddToWorklist(N0.getNode());
// FIXME: If running after legalize, we probably can't do this.
@@ -2102,7 +2102,7 @@
const MachineFrameInfo *MFI) const {
if (LD->getChain() != Base->getChain())
return false;
- MVT VT = LD->getValueType(0);
+ EVT VT = LD->getValueType(0);
if (VT.getSizeInBits() / 8 != Bytes)
return false;
@@ -2183,7 +2183,7 @@
/// LowerXConstraint - try to replace an X constraint, which matches anything,
/// with another that has more specific requirements based on the type of the
/// corresponding operand.
-const char *TargetLowering::LowerXConstraint(MVT ConstraintVT) const{
+const char *TargetLowering::LowerXConstraint(EVT ConstraintVT) const{
if (ConstraintVT.isInteger())
return "r";
if (ConstraintVT.isFloatingPoint())
@@ -2245,7 +2245,7 @@
// now; without this it would get ZExt'd later in
// ScheduleDAGSDNodes::EmitNode, which is very generic.
Ops.push_back(DAG.getTargetConstant(C->getAPIntValue().getSExtValue(),
- MVT::i64));
+ EVT::i64));
return;
}
}
@@ -2256,14 +2256,14 @@
std::vector<unsigned> TargetLowering::
getRegClassForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const {
+ EVT VT) const {
return std::vector<unsigned>();
}
std::pair<unsigned, const TargetRegisterClass*> TargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint,
- MVT VT) const {
+ EVT VT) const {
if (Constraint[0] != '{')
return std::pair<unsigned, const TargetRegisterClass*>(0, 0);
assert(*(Constraint.end()-1) == '}' && "Not a brace enclosed constraint?");
@@ -2479,7 +2479,7 @@
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
SDValue TargetLowering::BuildSDIV(SDNode *N, SelectionDAG &DAG,
std::vector<SDNode*>* Created) const {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl= N->getDebugLoc();
// Check to see if we can do this.
@@ -2536,7 +2536,7 @@
/// <http://the.wall.riscom.net/books/proc/ppc/cwg/code2.html>
SDValue TargetLowering::BuildUDIV(SDNode *N, SelectionDAG &DAG,
std::vector<SDNode*>* Created) const {
- MVT VT = N->getValueType(0);
+ EVT VT = N->getValueType(0);
DebugLoc dl = N->getDebugLoc();
// Check to see if we can do this.