commit e56f9085b1e96f0cc302c678f1c00877676e455e
author Anton Korobeynikov <asl@math.spbu.ru> Sat Sep 12 22:21:08 2009 +0000
committer Anton Korobeynikov <asl@math.spbu.ru> Sat Sep 12 22:21:08 2009 +0000
tree ed09566598bc883994b9e25583f1fdf21459553c
parent 4acac62e8d0d90aac3368ae43bab7595c444fac0

Add QPR_VFP2 regclass and add copy_to_regclass nodes, where needed to
constraint the register usage.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@81635 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMBaseInstrInfo.cpp

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 9da847a..52af978 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -613,6 +613,7 @@
 
   if (DestRC != SrcRC) {
     // Allow DPR / DPR_VFP2 / DPR_8 cross-class copies
+    // Allow QPR / QPR_VFP2 cross-class copies
     if (DestRC == ARM::DPRRegisterClass) {
       if (SrcRC == ARM::DPR_VFP2RegisterClass ||
           SrcRC == ARM::DPR_8RegisterClass) {
@@ -628,6 +629,10 @@
           SrcRC == ARM::DPR_VFP2RegisterClass) {
       } else
         return false;
+    } else if ((DestRC == ARM::QPRRegisterClass &&
+                SrcRC == ARM::QPR_VFP2RegisterClass) ||
+               (DestRC == ARM::QPR_VFP2RegisterClass &&
+                SrcRC == ARM::QPRRegisterClass)) {
     } else
       return false;
   }
@@ -643,7 +648,8 @@
              (DestRC == ARM::DPR_8RegisterClass)) {
     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FCPYD), DestReg)
                    .addReg(SrcReg));
-  } else if (DestRC == ARM::QPRRegisterClass) {
+  } else if (DestRC == ARM::QPRRegisterClass ||
+             DestRC == ARM::QPR_VFP2RegisterClass) {
     BuildMI(MBB, I, DL, get(ARM::VMOVQ), DestReg).addReg(SrcReg);
   } else {
     return false;
@@ -674,7 +680,8 @@
                    .addReg(SrcReg, getKillRegState(isKill))
                    .addFrameIndex(FI).addImm(0));
   } else {
-    assert(RC == ARM::QPRRegisterClass && "Unknown regclass!");
+    assert((RC == ARM::QPRRegisterClass ||
+            RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
     // FIXME: Neon instructions should support predicates
     BuildMI(MBB, I, DL, get(ARM::VSTRQ)).addReg(SrcReg, getKillRegState(isKill))
       .addFrameIndex(FI).addImm(0);
@@ -700,7 +707,8 @@
     AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::FLDS), DestReg)
                    .addFrameIndex(FI).addImm(0));
   } else {
-    assert(RC == ARM::QPRRegisterClass && "Unknown regclass!");
+    assert((RC == ARM::QPRRegisterClass ||
+            RC == ARM::QPR_VFP2RegisterClass) && "Unknown regclass!");
     // FIXME: Neon instructions should support predicates
     BuildMI(MBB, I, DL, get(ARM::VLDRQ), DestReg).addFrameIndex(FI).addImm(0);
   }