Use tblgen'd VECTOR_SHUFFLE selection code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@26900 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 39f5446..7ddf8c0 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -927,22 +927,6 @@
switch (N->getOpcode()) {
default: break;
- case ISD::VECTOR_SHUFFLE:
- // FIXME: This should be autogenerated from the .td file, it is here for now
- // due to bugs in tblgen.
- if (Op.getOperand(1).getOpcode() == ISD::UNDEF &&
- (Op.getValueType() == MVT::v4f32 || Op.getValueType() == MVT::v4i32) &&
- PPC::isSplatShuffleMask(Op.getOperand(2).Val)) {
- SDOperand N0;
- Select(N0, N->getOperand(0));
-
- Result = CodeGenMap[Op] =
- SDOperand(CurDAG->getTargetNode(PPC::VSPLTW, MVT::v4f32,
- getI32Imm(PPC::getVSPLTImmediate(Op.getOperand(2).Val)),
- N0), 0);
- return;
- }
- assert(0 && "ILLEGAL VECTOR_SHUFFLE!");
case ISD::SETCC:
Result = SelectSETCC(Op);
return;
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 66e89dc..4817ec1 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -1034,9 +1034,8 @@
def VSPLTW : VXForm_1<652, (ops VRRC:$vD, u5imm:$UIMM, VRRC:$vB),
"vspltw $vD, $vB, $UIMM", VecPerm,
- [/*
- (set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
- VSPLT_shuffle_mask:$UIMM))*/]>;
+ [(set VRRC:$vD, (vector_shuffle (v4f32 VRRC:$vB), (undef),
+ VSPLT_shuffle_mask:$UIMM))]>;
// FIXME: ALSO ADD SUPPORT FOR v4i32!
// VX-Form Pseudo Instructions