commit e746186ed4f61bf5eba13112cb8419c95cf58e52
author Andrew Trick <atrick@apple.com> Wed Feb 15 23:34:15 2012 +0000
committer Andrew Trick <atrick@apple.com> Wed Feb 15 23:34:15 2012 +0000
tree a90122c3aa0af4512f76e363dbe5a2dd1f5bb93d
parent 426f21573219eeba8f6981d7ddb4f1d2445b6343

Fix library visibility problems with VLIWPacketizer.

The existing framework for postra scheduling is library local. We want to keep it that way. Soon we will have a more general MachineScheduler interface. At that time, various bits will be exposed to targets. In the meantime, the VLIWPacketizer wants to use ScheduleDAGInstrs directly, so it needs to wrapped in a PIMPL to avoid exposing it to the target interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150633 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/DFAPacketizer.cpp

diff --git a/lib/CodeGen/DFAPacketizer.cpp b/lib/CodeGen/DFAPacketizer.cpp
index 4ac3052..5c8feb1 100644
--- a/lib/CodeGen/DFAPacketizer.cpp
+++ b/lib/CodeGen/DFAPacketizer.cpp
@@ -103,15 +103,29 @@
 namespace {
 // DefaultVLIWScheduler - This class extends ScheduleDAGInstrs and overrides
 // Schedule method to build the dependence graph.
+//
+// ScheduleDAGInstrs has LLVM_LIBRARY_VISIBILITY so cannot be exposed to the
+// VLIWPacketizerImpl interface, even as an undefined pointer.
 class DefaultVLIWScheduler : public ScheduleDAGInstrs {
 public:
   DefaultVLIWScheduler(MachineFunction &MF, MachineLoopInfo &MLI,
-                   MachineDominatorTree &MDT, bool IsPostRA);
+                       MachineDominatorTree &MDT, bool IsPostRA);
   // Schedule - Actual scheduling work.
   void Schedule();
 };
 }
 
+namespace llvm {
+// Wrapper for holding library-local data types.
+class VLIWPacketizerImpl {
+public:
+  DefaultVLIWScheduler DAGBuilder;
+  VLIWPacketizerImpl(MachineFunction &MF, MachineLoopInfo &MLI,
+                     MachineDominatorTree &MDT, bool IsPostRA)
+    : DAGBuilder(MF, MLI, MDT, IsPostRA) {}
+};
+}
+
 DefaultVLIWScheduler::DefaultVLIWScheduler(
   MachineFunction &MF, MachineLoopInfo &MLI, MachineDominatorTree &MDT,
   bool IsPostRA) :
@@ -129,12 +143,12 @@
   bool IsPostRA) : TM(MF.getTarget()), MF(MF)  {
   TII = TM.getInstrInfo();
   ResourceTracker = TII->CreateTargetScheduleState(&TM, 0);
-  VLIWScheduler = new DefaultVLIWScheduler(MF, MLI, MDT, IsPostRA);
+  Impl = new VLIWPacketizerImpl(MF, MLI, MDT, IsPostRA);
 }
 
 // VLIWPacketizerList Dtor
 VLIWPacketizerList::~VLIWPacketizerList() {
-  delete VLIWScheduler;
+  delete Impl;
   delete ResourceTracker;
 }
 
@@ -181,11 +195,10 @@
 void VLIWPacketizerList::PacketizeMIs(MachineBasicBlock *MBB,
                                       MachineBasicBlock::iterator BeginItr,
                                       MachineBasicBlock::iterator EndItr) {
-  assert(VLIWScheduler && "VLIW Scheduler is not initialized!");
-  VLIWScheduler->Run(MBB, BeginItr, EndItr, MBB->size());
+  Impl->DAGBuilder.Run(MBB, BeginItr, EndItr, MBB->size());
 
   // Remember scheduling units.
-  SUnits = VLIWScheduler->SUnits;
+  SUnits = Impl->DAGBuilder.SUnits;
 
   // Generate MI -> SU map.
   std::map <MachineInstr*, SUnit*> MIToSUnit;