Disengage DEBUG_LOC from non-PPC targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24919 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index d76a89d..6d6aab6 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -622,18 +622,22 @@
case TargetLowering::Promote:
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Expand: {
- MachineDebugInfo &DebugInfo = DAG.getMachineFunction().getDebugInfo();
- std::vector<SDOperand> Ops;
- Ops.push_back(Tmp1); // chain
- Ops.push_back(Node->getOperand(1)); // line #
- Ops.push_back(Node->getOperand(2)); // col #
- const std::string &fname =
- cast<StringSDNode>(Node->getOperand(3))->getValue();
- const std::string &dirname =
- cast<StringSDNode>(Node->getOperand(4))->getValue();
- unsigned id = DebugInfo.RecordSource(fname, dirname);
- Ops.push_back(DAG.getConstant(id, MVT::i32)); // source file id
- Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
+ if (TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other)) {
+ MachineDebugInfo &DebugInfo = DAG.getMachineFunction().getDebugInfo();
+ std::vector<SDOperand> Ops;
+ Ops.push_back(Tmp1); // chain
+ Ops.push_back(Node->getOperand(1)); // line #
+ Ops.push_back(Node->getOperand(2)); // col #
+ const std::string &fname =
+ cast<StringSDNode>(Node->getOperand(3))->getValue();
+ const std::string &dirname =
+ cast<StringSDNode>(Node->getOperand(4))->getValue();
+ unsigned id = DebugInfo.RecordSource(fname, dirname);
+ Ops.push_back(DAG.getConstant(id, MVT::i32)); // source file id
+ Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
+ } else {
+ Result = Tmp1; // chain
+ }
Result = LegalizeOp(Result); // Relegalize new nodes.
break;
}
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 49977b2..c39f0cd 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -691,7 +691,7 @@
} else {
Ordering.push_back(NI);
}
-
+
// Iterate through all nodes that have been added
for (unsigned i = 0; i < Ordering.size(); i++) { // note: size() varies
// Visit all operands
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index e86e25bf..9b2fce2 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -102,6 +102,7 @@
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
addLegalFPImmediate(+0.0); //F31
addLegalFPImmediate(-0.0); //-F31
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index e7276d4..6bfa793 100644
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -74,6 +74,7 @@
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
//IA64 has these, but they are not implemented
setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index b071a08..7c2b38c 100644
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -102,6 +102,7 @@
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
computeRegisterProperties();
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index a4e8264..6f444d4 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -147,6 +147,11 @@
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
+
+ // We don't have line number support yet.
+ setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+
computeRegisterProperties();
}
diff --git a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
index a4e8264..6f444d4 100644
--- a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
+++ b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
@@ -147,6 +147,11 @@
setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
+
+ // We don't have line number support yet.
+ setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
+
computeRegisterProperties();
}
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 5e4fb41..61d3aee 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -126,6 +126,7 @@
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+ setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
if (X86ScalarSSE) {
// Set up the FP register classes.