Do not fold away subreg_to_reg if the source register has a sub-register index. That means the source register is taking a sub-register of a larger register. e.g. On x86
%RAX<def> = ...
%RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
The first def is defining RAX, not EAX so the top bits were not zero-extended.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67511 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp
index 9af276f..14acb71 100644
--- a/lib/CodeGen/LowerSubregs.cpp
+++ b/lib/CodeGen/LowerSubregs.cpp
@@ -165,11 +165,12 @@
unsigned DstReg = MI->getOperand(0).getReg();
unsigned InsReg = MI->getOperand(2).getReg();
- unsigned SubIdx = MI->getOperand(3).getImm();
+ unsigned InsSIdx = MI->getOperand(2).getSubReg();
+ unsigned SubIdx = MI->getOperand(3).getImm();
assert(SubIdx != 0 && "Invalid index for insert_subreg");
unsigned DstSubReg = TRI.getSubReg(DstReg, SubIdx);
-
+
assert(TargetRegisterInfo::isPhysicalRegister(DstReg) &&
"Insert destination must be in a physical register");
assert(TargetRegisterInfo::isPhysicalRegister(InsReg) &&
@@ -177,8 +178,13 @@
DOUT << "subreg: CONVERTING: " << *MI;
- if (DstSubReg == InsReg) {
+ if (DstSubReg == InsReg && InsSIdx == 0) {
// No need to insert an identify copy instruction.
+ // Watch out for case like this:
+ // %RAX<def> = ...
+ // %RAX<def> = SUBREG_TO_REG 0, %EAX:3<kill>, 3
+ // The first def is defining RAX, not EAX so the top bits were not
+ // zero extended.
DOUT << "subreg: eliminated!";
} else {
// Insert sub-register copy
diff --git a/test/CodeGen/X86/subreg-to-reg-2.ll b/test/CodeGen/X86/subreg-to-reg-2.ll
new file mode 100644
index 0000000..d0b40cd
--- /dev/null
+++ b/test/CodeGen/X86/subreg-to-reg-2.ll
@@ -0,0 +1,25 @@
+; RUN: llvm-as < %s | llc -mtriple=x86_64-apple-darwin | grep movl
+; rdar://6707985
+
+ %XXOO = type { %"struct.XXC::XXCC", i8*, %"struct.XXC::XXOO::$_71" }
+ %XXValue = type opaque
+ %"struct.XXC::ArrayStorage" = type { i32, i32, i32, i8*, i8*, [1 x %XXValue*] }
+ %"struct.XXC::XXArray" = type { %XXOO, i32, %"struct.XXC::ArrayStorage"* }
+ %"struct.XXC::XXCC" = type { i32 (...)**, i8* }
+ %"struct.XXC::XXOO::$_71" = type { [2 x %XXValue*] }
+
+define internal fastcc %XXValue* @t(i64* %out, %"struct.XXC::ArrayStorage"* %tmp9) nounwind {
+prologue:
+ %array = load %XXValue** inttoptr (i64 11111111 to %XXValue**) ; <%XXValue*> [#uses=0]
+ %index = load %XXValue** inttoptr (i64 22222222 to %XXValue**) ; <%XXValue*> [#uses=1]
+ %tmp = ptrtoint %XXValue* %index to i64 ; <i64> [#uses=2]
+ store i64 %tmp, i64* %out
+ %tmp6 = trunc i64 %tmp to i32 ; <i32> [#uses=1]
+ br label %bb5
+
+bb5: ; preds = %prologue
+ %tmp10 = zext i32 %tmp6 to i64 ; <i64> [#uses=1]
+ %tmp11 = getelementptr %"struct.XXC::ArrayStorage"* %tmp9, i64 0, i32 5, i64 %tmp10 ; <%XXValue**> [#uses=1]
+ %tmp12 = load %XXValue** %tmp11, align 8 ; <%XXValue*> [#uses=1]
+ ret %XXValue* %tmp12
+}