commit e887fdff72486ad0e83f402c8c105fa91fff1036
author Dan Gohman <gohman@apple.com> Mon Jul 07 18:00:37 2008 +0000
committer Dan Gohman <gohman@apple.com> Mon Jul 07 18:00:37 2008 +0000
tree 73e3b798b99c400100672ea206ea1db8eb84af5a
parent 775977b3450a99de8bcb039de2dcc55d614ac176

Add explicit keywords.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@53179 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMISelDAGToDAG.cpp

diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 34f6cb9..37d647b 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -44,7 +44,7 @@
   const ARMSubtarget *Subtarget;
 
 public:
-  ARMDAGToDAGISel(ARMTargetMachine &TM)
+  explicit ARMDAGToDAGISel(ARMTargetMachine &TM)
     : SelectionDAGISel(Lowering), Lowering(TM),
     Subtarget(&TM.getSubtarget<ARMSubtarget>()) {
   }

lib/Target/CellSPU/SPUISelDAGToDAG.cpp

diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index 6bc69ee..a672b13 100644
--- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -227,7 +227,7 @@
   unsigned GlobalBaseReg;
 
 public:
-  SPUDAGToDAGISel(SPUTargetMachine &tm) :
+  explicit SPUDAGToDAGISel(SPUTargetMachine &tm) :
     SelectionDAGISel(*tm.getTargetLowering()),
     TM(tm),
     SPUtli(*tm.getTargetLowering())

lib/Target/IA64/IA64ISelDAGToDAG.cpp

diff --git a/lib/Target/IA64/IA64ISelDAGToDAG.cpp b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
index dcd1fe2..85c10fe 100644
--- a/lib/Target/IA64/IA64ISelDAGToDAG.cpp
+++ b/lib/Target/IA64/IA64ISelDAGToDAG.cpp
@@ -40,7 +40,7 @@
     IA64TargetLowering IA64Lowering;
     unsigned GlobalBaseReg;
   public:
-    IA64DAGToDAGISel(IA64TargetMachine &TM)
+    explicit IA64DAGToDAGISel(IA64TargetMachine &TM)
       : SelectionDAGISel(IA64Lowering), IA64Lowering(*TM.getTargetLowering()) {}
     
     virtual bool runOnFunction(Function &Fn) {

lib/Target/Mips/MipsISelDAGToDAG.cpp

diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp
index 4822e01..c5d3abd 100644
--- a/lib/Target/Mips/MipsISelDAGToDAG.cpp
+++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp
@@ -61,7 +61,8 @@
   const MipsSubtarget &Subtarget;
  
 public:
-  MipsDAGToDAGISel(MipsTargetMachine &tm) : SelectionDAGISel(MipsLowering),
+  explicit MipsDAGToDAGISel(MipsTargetMachine &tm) :
+  SelectionDAGISel(MipsLowering),
   TM(tm), MipsLowering(*TM.getTargetLowering()), 
   Subtarget(tm.getSubtarget<MipsSubtarget>()) {}
   

lib/Target/PIC16/PIC16ISelDAGToDAG.cpp

diff --git a/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp b/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
index 325e71e..402566f 100644
--- a/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
+++ b/lib/Target/PIC16/PIC16ISelDAGToDAG.cpp
@@ -57,7 +57,7 @@
   PIC16TargetLowering PIC16Lowering;
 
 public:
-  PIC16DAGToDAGISel(PIC16TargetMachine &tm) : 
+  explicit PIC16DAGToDAGISel(PIC16TargetMachine &tm) : 
         SelectionDAGISel(PIC16Lowering),
         TM(tm), PIC16Lowering(*TM.getTargetLowering()) {}
   

lib/Target/PowerPC/PPCISelDAGToDAG.cpp

diff --git a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index 1dea2ee..09563c4 100644
--- a/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -45,7 +45,7 @@
     const PPCSubtarget &PPCSubTarget;
     unsigned GlobalBaseReg;
   public:
-    PPCDAGToDAGISel(PPCTargetMachine &tm)
+    explicit PPCDAGToDAGISel(PPCTargetMachine &tm)
       : SelectionDAGISel(PPCLowering), TM(tm),
         PPCLowering(*TM.getTargetLowering()),
         PPCSubTarget(*TM.getSubtargetImpl()) {}

lib/Target/Sparc/SparcISelDAGToDAG.cpp

diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 50690ca..df07d51 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -35,7 +35,7 @@
   /// make the right decision when generating code for different targets.
   const SparcSubtarget &Subtarget;
 public:
-  SparcDAGToDAGISel(TargetMachine &TM)
+  explicit SparcDAGToDAGISel(TargetMachine &TM)
     : SelectionDAGISel(Lowering), Lowering(TM),
       Subtarget(TM.getSubtarget<SparcSubtarget>()) {
   }