Add UDIV, SDIV, and a few variants of WR.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@12733 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index 21f8a65..db79597 100644
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -94,6 +94,10 @@
def UMULrr : F3_1<2, 0b001010, "umul">;
def SMULrr : F3_1<2, 0b001011, "smul">;
+// Section B.19 - Divide Instructions, p. 115
+def UDIVrr: F3_1<2, 0b001110, "udiv">;
+def SDIVrr: F3_1<2, 0b001111, "sdiv">;
+
// Section B.20 - SAVE and RESTORE, p. 117
def SAVErr : F3_1<2, 0b111100, "save">; // save r, r, r
def SAVEri : F3_2<2, 0b111100, "save">; // save r, i, r
@@ -114,3 +118,7 @@
def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
def JMPLri : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
+// Section B.29 - Write State Register Instructions, p. 133
+let rd = 0 in
+ def WRYrr : F3_1<2, 0b110000, "wr">; // Special case of WRASR
+def WRASRrr : F3_1<2, 0b110000, "wr">; // Special reg = reg ^ reg