commit e922c0201916e0b980ab3cfe91e1413e68d55647
author Owen Anderson <resistor@mac.com> Wed Jul 22 00:24:57 2009 +0000
committer Owen Anderson <resistor@mac.com> Wed Jul 22 00:24:57 2009 +0000
tree 663be741b84470d97945f01da459a3627af683fd
parent 7cf12c7efd37dc12c3ed536a3f4c373dddac2b85

Get rid of the Pass+Context magic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76702 91177308-0d34-0410-b5e6-96231b3b80d8

lib/CodeGen/SelectionDAG/CallingConvLower.cpp

diff --git a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
index 2f4db28..e43af82 100644
--- a/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
+++ b/lib/CodeGen/SelectionDAG/CallingConvLower.cpp
@@ -21,7 +21,7 @@
 using namespace llvm;
 
 CCState::CCState(unsigned CC, bool isVarArg, const TargetMachine &tm,
-                 SmallVector<CCValAssign, 16> &locs, LLVMContext *C)
+                 SmallVector<CCValAssign, 16> &locs, LLVMContext &C)
   : CallingConv(CC), IsVarArg(isVarArg), TM(tm),
     TRI(*TM.getRegisterInfo()), Locs(locs), Context(C) {
   // No stack is used.

lib/CodeGen/SelectionDAG/FastISel.cpp

diff --git a/lib/CodeGen/SelectionDAG/FastISel.cpp b/lib/CodeGen/SelectionDAG/FastISel.cpp
index d523e7f..547a7bf 100644
--- a/lib/CodeGen/SelectionDAG/FastISel.cpp
+++ b/lib/CodeGen/SelectionDAG/FastISel.cpp
@@ -92,7 +92,7 @@
   } else if (isa<ConstantPointerNull>(V)) {
     // Translate this as an integer zero so that it can be
     // local-CSE'd with actual integer zeros.
-    Reg = getRegForValue(Context->getNullValue(TD.getIntPtrType()));
+    Reg = getRegForValue(V->getContext().getNullValue(TD.getIntPtrType()));
   } else if (ConstantFP *CF = dyn_cast<ConstantFP>(V)) {
     Reg = FastEmit_f(VT, VT, ISD::ConstantFP, CF);
 
@@ -108,7 +108,8 @@
       if (isExact) {
         APInt IntVal(IntBitWidth, 2, x);
 
-        unsigned IntegerReg = getRegForValue(Context->getConstantInt(IntVal));
+        unsigned IntegerReg =
+          getRegForValue(V->getContext().getConstantInt(IntVal));
         if (IntegerReg != 0)
           Reg = FastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, IntegerReg);
       }
@@ -480,7 +481,7 @@
         UpdateValueMap(I, ResultReg);
       } else {
         unsigned ResultReg =
-          getRegForValue(Context->getNullValue(I->getType()));
+          getRegForValue(I->getContext().getNullValue(I->getType()));
         UpdateValueMap(I, ResultReg);
       }
       return true;
@@ -753,8 +754,7 @@
     TM(MF.getTarget()),
     TD(*TM.getTargetData()),
     TII(*TM.getInstrInfo()),
-    TLI(*TM.getTargetLowering()),
-    Context(mf.getFunction()->getContext()) {
+    TLI(*TM.getTargetLowering()) {
 }
 
 FastISel::~FastISel() {}

lib/CodeGen/SelectionDAG/SelectionDAG.cpp

diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 87ca13e..c2595bc 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -816,7 +816,7 @@
   MF = &mf;
   MMI = mmi;
   DW = dw;
-  Context = mf.getFunction()->getContext();  
+  Context = &mf.getFunction()->getContext();  
 }
 
 SelectionDAG::~SelectionDAG() {