Add a DAGCombine for subvector extracts to remove useless chains of
subvector inserts and extracts. Initial patch by Rackover, Zvi with
some tweak done by me.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@140204 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/X86/avx-vinsertf128.ll b/test/CodeGen/X86/avx-vinsertf128.ll
index 2b2f7e5..cda1331 100644
--- a/test/CodeGen/X86/avx-vinsertf128.ll
+++ b/test/CodeGen/X86/avx-vinsertf128.ll
@@ -37,3 +37,22 @@
ret void
}
+;; DAG Combine must remove useless vinsertf128 instructions
+
+; CHECK: DAGCombineA
+; CHECK-NOT: vinsertf128 $1
+define <4 x i32> @DAGCombineA(<4 x i32> %v1) nounwind readonly {
+ %1 = shufflevector <4 x i32> %v1, <4 x i32> undef, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
+ %2 = shufflevector <8 x i32> %1, <8 x i32> undef, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
+ ret <4 x i32> %2
+}
+
+; CHECK: DAGCombineB
+; CHECK: vpaddd %xmm
+; CHECK-NOT: vinsertf128 $1
+; CHECK: vpaddd %xmm
+define <8 x i32> @DAGCombineB(<8 x i32> %v1, <8 x i32> %v2) nounwind readonly {
+ %1 = add <8 x i32> %v1, %v2
+ %2 = add <8 x i32> %1, %v1
+ ret <8 x i32> %2
+}