Temporarily revert r68552. This was causing a failure in the self-hosting LLVM
builds.
--- Reverse-merging (from foreign repository) r68552 into '.':
U test/CodeGen/X86/tls8.ll
U test/CodeGen/X86/tls10.ll
U test/CodeGen/X86/tls2.ll
U test/CodeGen/X86/tls6.ll
U lib/Target/X86/X86Instr64bit.td
U lib/Target/X86/X86InstrSSE.td
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86RegisterInfo.cpp
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86CodeEmitter.cpp
U lib/Target/X86/X86FastISel.cpp
U lib/Target/X86/X86InstrInfo.h
U lib/Target/X86/X86ISelDAGToDAG.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp
U lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.h
U lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.h
U lib/Target/X86/X86ISelLowering.h
U lib/Target/X86/X86InstrInfo.cpp
U lib/Target/X86/X86InstrBuilder.h
U lib/Target/X86/X86RegisterInfo.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@68560 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 4d9e2be..dd7346a 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -1138,9 +1138,9 @@
assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
- NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
- .addReg(Dest, true, false, false, isDead),
- Src, isKill, 1);
+ NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
+ .addReg(Dest, true, false, false, isDead),
+ Src, isKill, 1);
break;
}
case X86::INC16r:
@@ -1157,9 +1157,9 @@
assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
: (is64Bit ? X86::LEA64_32r : X86::LEA32r);
- NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
- .addReg(Dest, true, false, false, isDead),
- Src, isKill, -1);
+ NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
+ .addReg(Dest, true, false, false, isDead),
+ Src, isKill, -1);
break;
}
case X86::DEC16r:
@@ -1200,18 +1200,18 @@
case X86::ADD64ri8:
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
if (MI->getOperand(2).isImm())
- NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
- .addReg(Dest, true, false, false, isDead),
- Src, isKill, MI->getOperand(2).getImm());
+ NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
+ .addReg(Dest, true, false, false, isDead),
+ Src, isKill, MI->getOperand(2).getImm());
break;
case X86::ADD32ri:
case X86::ADD32ri8:
assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
if (MI->getOperand(2).isImm()) {
unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
- NewMI = addLeaRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
- .addReg(Dest, true, false, false, isDead),
- Src, isKill, MI->getOperand(2).getImm());
+ NewMI = addRegOffset(BuildMI(MF, MI->getDebugLoc(), get(Opc))
+ .addReg(Dest, true, false, false, isDead),
+ Src, isKill, MI->getOperand(2).getImm());
}
break;
case X86::ADD16ri:
@@ -1959,7 +1959,7 @@
for (unsigned i = 0; i != NumAddrOps; ++i)
MIB.addOperand(MOs[i]);
if (NumAddrOps < 4) // FrameIndex only
- addOffset(MIB, 0);
+ MIB.addImm(1).addReg(0).addImm(0);
// Loop over the rest of the ri operands, converting them over.
unsigned NumOps = MI->getDesc().getNumOperands()-2;
@@ -1990,7 +1990,7 @@
for (unsigned i = 0; i != NumAddrOps; ++i)
MIB.addOperand(MOs[i]);
if (NumAddrOps < 4) // FrameIndex only
- addOffset(MIB, 0);
+ MIB.addImm(1).addReg(0).addImm(0);
} else {
MIB.addOperand(MO);
}
@@ -2008,7 +2008,7 @@
for (unsigned i = 0; i != NumAddrOps; ++i)
MIB.addOperand(MOs[i]);
if (NumAddrOps < 4) // FrameIndex only
- addOffset(MIB, 0);
+ MIB.addImm(1).addReg(0).addImm(0);
return MIB.addImm(0);
}
@@ -2164,7 +2164,7 @@
} else if (Ops.size() != 1)
return NULL;
- SmallVector<MachineOperand,X86AddrNumOperands> MOs;
+ SmallVector<MachineOperand,4> MOs;
if (LoadMI->getOpcode() == X86::V_SET0 ||
LoadMI->getOpcode() == X86::V_SETALLONES) {
// Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
@@ -2193,7 +2193,6 @@
MOs.push_back(MachineOperand::CreateImm(1));
MOs.push_back(MachineOperand::CreateReg(0, false));
MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
- MOs.push_back(MachineOperand::CreateReg(0, false));
} else {
// Folding a normal load. Just copy the load's address operands.
unsigned NumOps = LoadMI->getDesc().getNumOperands();
@@ -2883,6 +2882,11 @@
FinalSize += sizeConstant(X86InstrInfo::sizeOfImm(Desc));
break;
}
+ case X86::TLS_tp:
+ case X86::TLS_gs_ri:
+ FinalSize += 2;
+ FinalSize += sizeGlobalAddress(false);
+ break;
}
CurOp = NumOps;
break;