enable LSR by default on alpha
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24337 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaTargetMachine.cpp b/lib/Target/Alpha/AlphaTargetMachine.cpp
index f5bd484..3ee1300 100644
--- a/lib/Target/Alpha/AlphaTargetMachine.cpp
+++ b/lib/Target/Alpha/AlphaTargetMachine.cpp
@@ -29,9 +29,6 @@
}
namespace llvm {
- cl::opt<bool> EnableAlphaLSR("enable-lsr-for-alpha",
- cl::desc("Enable LSR for Alpha (beta option!)"),
- cl::Hidden);
cl::opt<bool> EnableAlphaDAG("enable-dag-isel-for-alpha",
cl::desc("Enable DAG ISEL for Alpha (beta option!)"),
cl::Hidden);
@@ -81,10 +78,7 @@
bool Fast) {
if (FileType != TargetMachine::AssemblyFile) return true;
- if (EnableAlphaLSR) {
- PM.add(createLoopStrengthReducePass());
- PM.add(createCFGSimplificationPass());
- }
+ PM.add(createLoopStrengthReducePass());
// FIXME: Implement efficient support for garbage collection intrinsics.
PM.add(createLowerGCPass());
@@ -98,6 +92,8 @@
// Make sure that no unreachable blocks are instruction selected.
PM.add(createUnreachableBlockEliminationPass());
+ PM.add(createCFGSimplificationPass());
+
if (EnableAlphaDAG)
PM.add(createAlphaISelDag(*this));
else