Remove a bunch more SparcV9 specific stuff
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28093 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/MachineInstr.cpp b/lib/CodeGen/MachineInstr.cpp
index 3d65dfd..367631c 100644
--- a/lib/CodeGen/MachineInstr.cpp
+++ b/lib/CodeGen/MachineInstr.cpp
@@ -141,7 +141,7 @@
void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
assert(i < getNumOperands()); // must be explicit op
- operands[i].opType = MachineOperand::MO_MachineRegister;
+ operands[i].opType = MachineOperand::MO_VirtualRegister;
operands[i].contents.value = NULL;
operands[i].extra.regNum = regNum;
}
@@ -187,9 +187,6 @@
if (MO.hasAllocatedReg())
OutputReg(OS, MO.getReg(), MRI);
break;
- case MachineOperand::MO_MachineRegister:
- OutputReg(OS, MO.getMachineRegNum(), MRI);
- break;
case MachineOperand::MO_SignExtendedImmed:
OS << (long)MO.getImmedValue();
break;
@@ -297,9 +294,6 @@
OutputValue(OS, MO.getVRegValue());
}
break;
- case MachineOperand::MO_MachineRegister:
- OutputReg(OS, MO.getMachineRegNum());
- break;
case MachineOperand::MO_SignExtendedImmed:
OS << (long)MO.getImmedValue();
break;
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index 3509b16..2b7b877 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -110,7 +110,7 @@
MI->addRegOperand(R->getReg(), MachineOperand::Use);
} else if (GlobalAddressSDNode *TGA =
dyn_cast<GlobalAddressSDNode>(Op)) {
- MI->addGlobalAddressOperand(TGA->getGlobal(), false, TGA->getOffset());
+ MI->addGlobalAddressOperand(TGA->getGlobal(), TGA->getOffset());
} else if (BasicBlockSDNode *BB =
dyn_cast<BasicBlockSDNode>(Op)) {
MI->addMachineBasicBlockOperand(BB->getBasicBlock());
@@ -143,7 +143,7 @@
MI->addConstantPoolIndexOperand(Idx, Offset);
} else if (ExternalSymbolSDNode *ES =
dyn_cast<ExternalSymbolSDNode>(Op)) {
- MI->addExternalSymbolOperand(ES->getSymbol(), false);
+ MI->addExternalSymbolOperand(ES->getSymbol());
} else {
assert(Op.getValueType() != MVT::Other &&
Op.getValueType() != MVT::Flag &&
@@ -296,7 +296,7 @@
// Add the asm string as an external symbol operand.
const char *AsmStr =
cast<ExternalSymbolSDNode>(Node->getOperand(1))->getSymbol();
- MI->addExternalSymbolOperand(AsmStr, false);
+ MI->addExternalSymbolOperand(AsmStr);
// Add all of the operand registers to the instruction.
for (unsigned i = 2; i != NumOps;) {
@@ -311,13 +311,13 @@
case 1: // Use of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MI->addMachineRegOperand(Reg, MachineOperand::Use);
+ MI->addRegOperand(Reg, MachineOperand::Use);
}
break;
case 2: // Def of register.
for (; NumVals; --NumVals, ++i) {
unsigned Reg = cast<RegisterSDNode>(Node->getOperand(i))->getReg();
- MI->addMachineRegOperand(Reg, MachineOperand::Def);
+ MI->addRegOperand(Reg, MachineOperand::Def);
}
break;
case 3: { // Immediate.
diff --git a/lib/Target/Alpha/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AlphaAsmPrinter.cpp
index 435e8e8..1e36067 100644
--- a/lib/Target/Alpha/AlphaAsmPrinter.cpp
+++ b/lib/Target/Alpha/AlphaAsmPrinter.cpp
@@ -77,7 +77,7 @@
void AlphaAsmPrinter::printOperand(const MachineInstr *MI, int opNum)
{
const MachineOperand &MO = MI->getOperand(opNum);
- if (MO.getType() == MachineOperand::MO_MachineRegister) {
+ if (MO.getType() == MachineOperand::MO_VirtualRegister) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else if (MO.isImmediate()) {
@@ -94,12 +94,6 @@
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
- if (Value *V = MO.getVRegValueOrNull()) {
- O << "<" << V->getName() << ">";
- return;
- }
- // FALLTHROUGH
- case MachineOperand::MO_MachineRegister:
O << RI.get(MO.getReg()).Name;
return;
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index 8f6310e..85c9da8 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -263,7 +263,8 @@
.addReg(Alpha::R29).addImm(curgpdist);
//evil const_cast until MO stuff setup to handle const
- BuildMI(MBB, MBBI, Alpha::ALTENT, 1).addGlobalAddress(const_cast<Function*>(MF.getFunction()), true);
+ BuildMI(MBB, MBBI, Alpha::ALTENT, 1)
+ .addGlobalAddress(const_cast<Function*>(MF.getFunction()));
// Get the number of bytes to allocate from the FrameInfo
long NumBytes = MFI->getStackSize();
diff --git a/lib/Target/IA64/IA64AsmPrinter.cpp b/lib/Target/IA64/IA64AsmPrinter.cpp
index 6895d32..087fcc3 100644
--- a/lib/Target/IA64/IA64AsmPrinter.cpp
+++ b/lib/Target/IA64/IA64AsmPrinter.cpp
@@ -66,7 +66,7 @@
// This method is used by the tablegen'erated instruction printer.
void printOperand(const MachineInstr *MI, unsigned OpNo){
const MachineOperand &MO = MI->getOperand(OpNo);
- if (MO.getType() == MachineOperand::MO_MachineRegister) {
+ if (MO.getType() == MachineOperand::MO_VirtualRegister) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
//XXX Bug Workaround: See note in Printer::doInitialization about %.
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
@@ -174,12 +174,6 @@
const MRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
- if (Value *V = MO.getVRegValueOrNull()) {
- O << "<" << V->getName() << ">";
- return;
- }
- // FALLTHROUGH
- case MachineOperand::MO_MachineRegister:
O << RI.get(MO.getReg()).Name;
return;
diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index 2cf10a2..e85ce9f 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -86,7 +86,7 @@
void printOperand(const MachineInstr *MI, unsigned OpNo) {
const MachineOperand &MO = MI->getOperand(OpNo);
- if (MO.getType() == MachineOperand::MO_MachineRegister) {
+ if (MO.getType() == MachineOperand::MO_VirtualRegister) {
assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else if (MO.isImmediate()) {
@@ -353,13 +353,6 @@
int new_symbol;
switch (MO.getType()) {
- case MachineOperand::MO_VirtualRegister:
- if (Value *V = MO.getVRegValueOrNull()) {
- O << "<" << V->getName() << ">";
- return;
- }
- // FALLTHROUGH
- case MachineOperand::MO_MachineRegister:
O << RI.get(MO.getReg()).Name;
return;
diff --git a/lib/Target/Sparc/SparcAsmPrinter.cpp b/lib/Target/Sparc/SparcAsmPrinter.cpp
index ced2b3d..2d81bbd 100644
--- a/lib/Target/Sparc/SparcAsmPrinter.cpp
+++ b/lib/Target/Sparc/SparcAsmPrinter.cpp
@@ -147,12 +147,6 @@
}
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
- if (Value *V = MO.getVRegValueOrNull()) {
- O << "<" << V->getName() << ">";
- break;
- }
- // FALLTHROUGH
- case MachineOperand::MO_MachineRegister:
if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
O << "%" << LowercaseString (RI.get(MO.getReg()).Name);
else
@@ -195,8 +189,7 @@
MachineOperand::MachineOperandType OpTy = MI->getOperand(opNum+1).getType();
- if ((OpTy == MachineOperand::MO_VirtualRegister ||
- OpTy == MachineOperand::MO_MachineRegister) &&
+ if (OpTy == MachineOperand::MO_VirtualRegister &&
MI->getOperand(opNum+1).getReg() == SP::G0)
return; // don't print "+%g0"
if ((OpTy == MachineOperand::MO_SignExtendedImmed ||
diff --git a/lib/Target/X86/X86ATTAsmPrinter.cpp b/lib/Target/X86/X86ATTAsmPrinter.cpp
index b7f5b6c..5283ddd 100755
--- a/lib/Target/X86/X86ATTAsmPrinter.cpp
+++ b/lib/Target/X86/X86ATTAsmPrinter.cpp
@@ -109,7 +109,6 @@
const MRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
- case MachineOperand::MO_MachineRegister:
assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) &&
"Virtual registers should not make it this far!");
O << '%';
diff --git a/lib/Target/X86/X86InstrBuilder.h b/lib/Target/X86/X86InstrBuilder.h
index 95d7f92..6a3c116 100644
--- a/lib/Target/X86/X86InstrBuilder.h
+++ b/lib/Target/X86/X86InstrBuilder.h
@@ -93,7 +93,7 @@
assert (0);
MIB.addZImm(AM.Scale).addReg(AM.IndexReg);
if (AM.GV)
- return MIB.addGlobalAddress(AM.GV, false, AM.Disp);
+ return MIB.addGlobalAddress(AM.GV, AM.Disp);
else
return MIB.addSImm(AM.Disp);
}
diff --git a/lib/Target/X86/X86IntelAsmPrinter.cpp b/lib/Target/X86/X86IntelAsmPrinter.cpp
index f3213b6..f9093da 100755
--- a/lib/Target/X86/X86IntelAsmPrinter.cpp
+++ b/lib/Target/X86/X86IntelAsmPrinter.cpp
@@ -115,12 +115,6 @@
const MRegisterInfo &RI = *TM.getRegisterInfo();
switch (MO.getType()) {
case MachineOperand::MO_VirtualRegister:
- if (Value *V = MO.getVRegValueOrNull()) {
- O << "<" << V->getName() << ">";
- return;
- }
- // FALLTHROUGH
- case MachineOperand::MO_MachineRegister:
if (MRegisterInfo::isPhysicalRegister(MO.getReg()))
O << RI.get(MO.getReg()).Name;
else
diff --git a/lib/Target/X86/X86IntelAsmPrinter.h b/lib/Target/X86/X86IntelAsmPrinter.h
index b408ea3..28ccfc9 100755
--- a/lib/Target/X86/X86IntelAsmPrinter.h
+++ b/lib/Target/X86/X86IntelAsmPrinter.h
@@ -37,8 +37,8 @@
void printOperand(const MachineInstr *MI, unsigned OpNo,
const char *Modifier = 0) {
const MachineOperand &MO = MI->getOperand(OpNo);
- if (MO.getType() == MachineOperand::MO_MachineRegister) {
- assert(MRegisterInfo::isPhysicalRegister(MO.getReg())&&"Not physref??");
+ if (MO.getType() == MachineOperand::MO_VirtualRegister) {
+ assert(MRegisterInfo::isPhysicalRegister(MO.getReg()) && "Not physreg??");
O << TM.getRegisterInfo()->get(MO.getReg()).Name;
} else {
printOp(MO, Modifier);
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 383529a..a9e345f 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -150,7 +150,7 @@
else if (MI->getOperand(1).isGlobalAddress())
return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
.addGlobalAddress(MI->getOperand(1).getGlobal(),
- false, MI->getOperand(1).getOffset());
+ MI->getOperand(1).getOffset());
else if (MI->getOperand(1).isJumpTableIndex())
return addFrameReference(BuildMI(Opcode, 5), FrameIndex)
.addJumpTableIndex(MI->getOperand(1).getJumpTableIndex());