Tighten test case a bit.
Ideally, we would match an S-register to its containing D-register, but that
requires arithmetic (divide by 2).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129756 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/test/CodeGen/ARM/fcopysign.ll b/test/CodeGen/ARM/fcopysign.ll
index 2b08b03..f241c26 100644
--- a/test/CodeGen/ARM/fcopysign.ll
+++ b/test/CodeGen/ARM/fcopysign.ll
@@ -45,7 +45,8 @@
entry:
; SOFT: test4:
; SOFT: vmov.f64 [[REG4:(d[0-9]+)]], #1.000000e+00
-; SOFT: vcvt.f32.f64 {{s[0-9]+}}, [[REG4]]
+; This S-reg must be the first sub-reg of the last D-reg on vbsl.
+; SOFT: vcvt.f32.f64 {{s1?[02468]}}, [[REG4]]
; SOFT: vshr.u64 [[REG4]], [[REG4]], #32
; SOFT: vmov.i32 [[REG5:(d[0-9]+)]], #0x80000000
; SOFT: vbsl [[REG5]], [[REG4]], {{d[0-9]+}}