Move ComputeMaskedBits, MaskedValueIsZero, and ComputeNumSignBits from
TargetLowering to SelectionDAG so that they have more convenient
access to the current DAG, in preparation for the ValueType routines
being changed from standalone functions to members of SelectionDAG for
the pre-legalize vector type changes.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@37704 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index bf07fc6..a1fe460 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -688,10 +688,10 @@
     // disjoint.
     uint64_t LHSKnownZero, LHSKnownOne;
     uint64_t RHSKnownZero, RHSKnownOne;
-    ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
+    DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
     
     if (LHSKnownZero) {
-      ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne);
+      DAG.ComputeMaskedBits(N.getOperand(1), ~0U, RHSKnownZero, RHSKnownOne);
       // If all of the bits are known zero on the LHS or RHS, the add won't
       // carry.
       if ((LHSKnownZero | RHSKnownZero) == ~0U) {
@@ -742,7 +742,7 @@
       // (for better address arithmetic) if the LHS and RHS of the OR are
       // provably disjoint.
       uint64_t LHSKnownZero, LHSKnownOne;
-      ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
+      DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
       if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
         // If all of the bits are known zero on the LHS or RHS, the add won't
         // carry.
@@ -850,7 +850,7 @@
       // (for better address arithmetic) if the LHS and RHS of the OR are
       // provably disjoint.
       uint64_t LHSKnownZero, LHSKnownOne;
-      ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
+      DAG.ComputeMaskedBits(N.getOperand(0), ~0U, LHSKnownZero, LHSKnownOne);
       if ((LHSKnownZero|~(unsigned)imm) == ~0U) {
         // If all of the bits are known zero on the LHS or RHS, the add won't
         // carry.
@@ -3235,6 +3235,7 @@
                                                        uint64_t Mask,
                                                        uint64_t &KnownZero, 
                                                        uint64_t &KnownOne,
+                                                       const SelectionDAG &DAG,
                                                        unsigned Depth) const {
   KnownZero = 0;
   KnownOne = 0;