Moved the MachOWriter and ELFWriter out of the Target/* files. Placed the
definition of it into the CodeGen library. This is so that a backend doesn't
necessarily add in these writers if it doesn't use them (like in the lli
program).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@34034 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPC.h b/lib/Target/PowerPC/PPC.h
index bfaa874..9327f30 100644
--- a/lib/Target/PowerPC/PPC.h
+++ b/lib/Target/PowerPC/PPC.h
@@ -33,8 +33,6 @@
PPCTargetMachine &TM);
FunctionPass *createPPCCodeEmitterPass(PPCTargetMachine &TM,
MachineCodeEmitter &MCE);
-void addPPCMachOObjectWriterPass(FunctionPassManager &FPM, std::ostream &o,
- PPCTargetMachine &tm);
} // end namespace llvm;
// Defines symbolic names for PowerPC registers. This defines a mapping from
diff --git a/lib/Target/PowerPC/PPCMachOWriterInfo.cpp b/lib/Target/PowerPC/PPCMachOWriterInfo.cpp
index 7b5c4fe..e2c2ceb 100644
--- a/lib/Target/PowerPC/PPCMachOWriterInfo.cpp
+++ b/lib/Target/PowerPC/PPCMachOWriterInfo.cpp
@@ -2,8 +2,9 @@
//
// The LLVM Compiler Infrastructure
//
-// This file was developed by Bill Wendling and is distributed under the
-// University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file was developed by Nate Begeman and Bill Wendling and is distributed
+// under the University of Illinois Open Source License. See LICENSE.TXT for
+// details.
//
//===----------------------------------------------------------------------===//
//
@@ -25,7 +26,6 @@
HDR_CPU_SUBTYPE_POWERPC_ALL) {}
PPCMachOWriterInfo::~PPCMachOWriterInfo() {}
-
/// GetTargetRelocation - For the MachineRelocation MR, convert it to one or
/// more PowerPC MachORelocation(s), add the new relocations to the
/// MachOSection, and rewrite the instruction at the section offset if required
diff --git a/lib/Target/PowerPC/PPCTargetMachine.cpp b/lib/Target/PowerPC/PPCTargetMachine.cpp
index f23b022..99c4aa1 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.cpp
+++ b/lib/Target/PowerPC/PPCTargetMachine.cpp
@@ -129,16 +129,6 @@
return false;
}
-bool PPCTargetMachine::addObjectWriter(FunctionPassManager &PM, bool Fast,
- std::ostream &Out) {
- // FIXME: until the macho writer is 100% functional, diable this by default.
- return true;
-
- // FIXME: support PPC ELF files at some point
- addPPCMachOObjectWriterPass(PM, Out, *this);
- return false;
-}
-
bool PPCTargetMachine::addCodeEmitter(FunctionPassManager &PM, bool Fast,
MachineCodeEmitter &MCE) {
// The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
@@ -161,3 +151,9 @@
return false;
}
+bool PPCTargetMachine::addSimpleCodeEmitter(FunctionPassManager &PM, bool Fast,
+ MachineCodeEmitter &MCE) {
+ // Machine code emitter pass for PowerPC.
+ PM.add(createPPCCodeEmitterPass(*this, MCE));
+ return false;
+}
diff --git a/lib/Target/PowerPC/PPCTargetMachine.h b/lib/Target/PowerPC/PPCTargetMachine.h
index af35cc5..a249952 100644
--- a/lib/Target/PowerPC/PPCTargetMachine.h
+++ b/lib/Target/PowerPC/PPCTargetMachine.h
@@ -69,10 +69,10 @@
virtual bool addPreEmitPass(FunctionPassManager &PM, bool Fast);
virtual bool addAssemblyEmitter(FunctionPassManager &PM, bool Fast,
std::ostream &Out);
- virtual bool addObjectWriter(FunctionPassManager &PM, bool Fast,
- std::ostream &Out);
virtual bool addCodeEmitter(FunctionPassManager &PM, bool Fast,
MachineCodeEmitter &MCE);
+ virtual bool addSimpleCodeEmitter(FunctionPassManager &PM, bool Fast,
+ MachineCodeEmitter &MCE);
};
/// PPC32TargetMachine - PowerPC 32-bit target machine.
diff --git a/lib/Target/X86/X86.h b/lib/Target/X86/X86.h
index b34df13..c7663be 100644
--- a/lib/Target/X86/X86.h
+++ b/lib/Target/X86/X86.h
@@ -46,12 +46,6 @@
FunctionPass *createX86CodeEmitterPass(X86TargetMachine &TM,
MachineCodeEmitter &MCE);
-/// addX86ELFObjectWriterPass - Add passes to the FPM that output the generated
-/// code as an ELF object file.
-///
-void addX86ELFObjectWriterPass(FunctionPassManager &FPM,
- std::ostream &o, X86TargetMachine &tm);
-
/// createX86EmitCodeToMemory - Returns a pass that converts a register
/// allocated function into raw machine code in a dynamically
/// allocated chunk of memory.
diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp
index 8f648d8..7a5a63d 100644
--- a/lib/Target/X86/X86TargetMachine.cpp
+++ b/lib/Target/X86/X86TargetMachine.cpp
@@ -163,15 +163,6 @@
return false;
}
-bool X86TargetMachine::addObjectWriter(FunctionPassManager &PM, bool Fast,
- std::ostream &Out) {
- if (Subtarget.isTargetELF()) {
- addX86ELFObjectWriterPass(PM, Out, *this);
- return false;
- }
- return true;
-}
-
bool X86TargetMachine::addCodeEmitter(FunctionPassManager &PM, bool Fast,
MachineCodeEmitter &MCE) {
// FIXME: Move this to TargetJITInfo!
@@ -185,3 +176,9 @@
PM.add(createX86CodeEmitterPass(*this, MCE));
return false;
}
+
+bool X86TargetMachine::addSimpleCodeEmitter(FunctionPassManager &PM, bool Fast,
+ MachineCodeEmitter &MCE) {
+ PM.add(createX86CodeEmitterPass(*this, MCE));
+ return false;
+}
diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h
index 565cdcf..0a4f1b5 100644
--- a/lib/Target/X86/X86TargetMachine.h
+++ b/lib/Target/X86/X86TargetMachine.h
@@ -53,22 +53,21 @@
}
virtual const TargetData *getTargetData() const { return &DataLayout; }
virtual const X86ELFWriterInfo *getELFWriterInfo() const {
- return &ELFWriterInfo;
+ return Subtarget.isTargetELF() ? &ELFWriterInfo : 0;
}
static unsigned getModuleMatchQuality(const Module &M);
static unsigned getJITMatchQuality();
-
// Set up the pass pipeline.
virtual bool addInstSelector(FunctionPassManager &PM, bool Fast);
virtual bool addPostRegAlloc(FunctionPassManager &PM, bool Fast);
virtual bool addAssemblyEmitter(FunctionPassManager &PM, bool Fast,
std::ostream &Out);
- virtual bool addObjectWriter(FunctionPassManager &PM, bool Fast,
- std::ostream &Out);
virtual bool addCodeEmitter(FunctionPassManager &PM, bool Fast,
MachineCodeEmitter &MCE);
+ virtual bool addSimpleCodeEmitter(FunctionPassManager &PM, bool Fast,
+ MachineCodeEmitter &MCE);
};
/// X86_32TargetMachine - X86 32-bit target machine.