Add a quick pass to optimize sign / zero extension instructions. For targets where the pre-extension values are available in the subreg of the result of the extension, replace the uses of the pre-extension value with the result + extract_subreg.
For now, this pass is fairly conservative. It only perform the replacement when both the pre- and post- extension values are used in the block. It will miss cases where the post-extension values are live, but not used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@93278 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 5ef3354..a1bacbf 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -713,9 +713,9 @@
}
bool
-X86InstrInfo::isCoalescableInstr(const MachineInstr &MI, bool &isCopy,
- unsigned &SrcReg, unsigned &DstReg,
- unsigned &SrcSubIdx, unsigned &DstSubIdx) const {
+X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
+ unsigned &SrcReg, unsigned &DstReg,
+ unsigned &SubIdx) const {
switch (MI.getOpcode()) {
default: break;
case X86::MOVSX16rr8:
@@ -733,10 +733,8 @@
if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
// Be conservative.
return false;
- isCopy = false;
SrcReg = MI.getOperand(1).getReg();
DstReg = MI.getOperand(0).getReg();
- DstSubIdx = 0;
switch (MI.getOpcode()) {
default:
llvm_unreachable(0);
@@ -747,22 +745,23 @@
case X86::MOVZX32rr8:
case X86::MOVSX64rr8:
case X86::MOVZX64rr8:
- SrcSubIdx = 1;
+ SubIdx = 1;
break;
case X86::MOVSX32rr16:
case X86::MOVZX32rr16:
case X86::MOVSX64rr16:
case X86::MOVZX64rr16:
- SrcSubIdx = 3;
+ SubIdx = 3;
break;
case X86::MOVSX64rr32:
case X86::MOVZX64rr32:
- SrcSubIdx = 4;
+ SubIdx = 4;
break;
}
+ return true;
}
}
- return isMoveInstr(MI, SrcReg, DstReg, SrcSubIdx, DstSubIdx);
+ return false;
}
/// isFrameOperand - Return true and the FrameIndex if the specified