implementation of some methods for inlineasm
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25951 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 5a191d9..068f6a8 100644
--- a/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -131,6 +131,10 @@
return NULL;
}
+//===----------------------------------------------------------------------===//
+// Optimization Methods
+//===----------------------------------------------------------------------===//
+
/// DemandedBitsAreZero - Return true if 'Op & Mask' demands no bits from a bit
/// set operation such as a sign extend or or/xor with constant whose only
/// use is Op. If it returns true, the old node that sets bits which are
@@ -139,7 +143,7 @@
/// desired.
bool TargetLowering::DemandedBitsAreZero(const SDOperand &Op, uint64_t Mask,
SDOperand &Old, SDOperand &New,
- SelectionDAG &DAG) {
+ SelectionDAG &DAG) const {
// If the operation has more than one use, we're not interested in it.
// Tracking down and checking all uses would be problematic and slow.
if (!Op.Val->hasOneUse())
@@ -302,6 +306,42 @@
return false;
}
+//===----------------------------------------------------------------------===//
+// Inline Assembler Implementation Methods
+//===----------------------------------------------------------------------===//
+
+TargetLowering::ConstraintType
+TargetLowering::getConstraintType(char ConstraintLetter) const {
+ // FIXME: lots more standard ones to handle.
+ switch (ConstraintLetter) {
+ default: return C_Unknown;
+ case 'r': return C_RegisterClass;
+ case 'i': // Simple Integer or Relocatable Constant
+ case 'n': // Simple Integer
+ case 's': // Relocatable Constant
+ case 'I': // Target registers.
+ case 'J':
+ case 'K':
+ case 'L':
+ case 'M':
+ case 'N':
+ case 'O':
+ case 'P': return C_Other;
+ }
+}
+
+bool TargetLowering::isOperandValidForConstraint(SDOperand Op,
+ char ConstraintLetter) {
+ switch (ConstraintLetter) {
+ default: return false;
+ case 'i': // Simple Integer or Relocatable Constant
+ case 'n': // Simple Integer
+ case 's': // Relocatable Constant
+ return true; // FIXME: not right.
+ }
+}
+
+
std::vector<unsigned> TargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint) const {
// Not a physreg, must not be a register reference or something.