added sign extend for boolean
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@20137 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 6c3614d..912bb69 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -56,9 +56,6 @@
setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand);
setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand);
- //what is the sign expansion of 1? 1 or -1?
- setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
-
setOperationAction(ISD::SREM , MVT::f32 , Expand);
setOperationAction(ISD::SREM , MVT::f64 , Expand);
@@ -959,6 +956,11 @@
case MVT::i8:
BuildMI(BB, Alpha::SEXTB, 1, Result).addReg(Tmp1);
break;
+ case MVT::i1:
+ Tmp2 = MakeReg(MVT::i64);
+ BuildMI(BB, Alpha::ANDi, 2, Tmp2).addReg(Tmp1).addImm(1);
+ BuildMI(BB, Alpha::SUB, 2, Result).addReg(Alpha::F31).addReg(Tmp2);
+ break;
}
return Result;
}