With setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand), Legalize
should be able to handle this case. The code is there, so let's see
if it works.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@22288 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 32c3bfa..c30cbd7 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -90,18 +90,21 @@
addRegisterClass(MVT::f32, Alpha::FPRCRegisterClass);
setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand);
- setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote);
- setOperationAction(ISD::EXTLOAD , MVT::f32 , Promote);
- setOperationAction(ISD::ZEXTLOAD , MVT::i1 , Expand);
- setOperationAction(ISD::ZEXTLOAD , MVT::i32 , Expand);
+ setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
+ setOperationAction(ISD::EXTLOAD, MVT::f32, Promote);
- setOperationAction(ISD::SEXTLOAD , MVT::i1 , Expand);
- setOperationAction(ISD::SEXTLOAD , MVT::i8 , Expand);
- setOperationAction(ISD::SEXTLOAD , MVT::i16 , Expand);
+ setOperationAction(ISD::ZEXTLOAD, MVT::i1 , Expand);
+ setOperationAction(ISD::ZEXTLOAD, MVT::i32 , Expand);
- setOperationAction(ISD::SREM , MVT::f32 , Expand);
- setOperationAction(ISD::SREM , MVT::f64 , Expand);
+ setOperationAction(ISD::SEXTLOAD, MVT::i1, Expand);
+ setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
+ setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
+
+ setOperationAction(ISD::SREM, MVT::f32, Expand);
+ setOperationAction(ISD::SREM, MVT::f64, Expand);
+
+ setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
if (!EnableAlphaCT) {
setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
@@ -1344,33 +1347,6 @@
return Result;
}
- case ISD::UINT_TO_FP:
- {
- //FIXME: First test if we will have problems with the sign bit before doing the slow thing
- assert (N.getOperand(0).getValueType() == MVT::i64
- && "only quads can be loaded from");
- Tmp1 = SelectExpr(N.getOperand(0)); // Get the operand register
- Tmp2 = MakeReg(MVT::i64);
- BuildMI(BB, Alpha::SRL, 2, Tmp2).addReg(Tmp1).addImm(1);
- Tmp3 = MakeReg(MVT::i64);
- BuildMI(BB, Alpha::CMPLT, 2, Tmp3).addReg(Tmp1).addReg(Alpha::R31);
- unsigned Tmp4 = MakeReg(MVT::f64), Tmp5 = MakeReg(MVT::f64), Tmp6 = MakeReg(MVT::f64);
- MoveInt2FP(Tmp1, Tmp4, true);
- MoveInt2FP(Tmp2, Tmp5, true);
- MoveInt2FP(Tmp3, Tmp6, true);
- Tmp1 = MakeReg(MVT::f64);
- Tmp2 = MakeReg(MVT::f64);
- Opc = DestType == MVT::f64 ? Alpha::CVTQT : Alpha::CVTQS;
- BuildMI(BB, Opc, 1, Tmp1).addReg(Tmp4);
- BuildMI(BB, Opc, 1, Tmp2).addReg(Tmp5);
- Tmp3 = MakeReg(MVT::f64);
- BuildMI(BB, Alpha::ADDT, 2, Tmp3).addReg(Tmp2).addReg(Tmp2);
- //Ok, now tmp1 had the plain covereted
- //tmp3 has the reduced converted and added
- //tmp6 has the conditional to use
- BuildMI(BB, Alpha::FCMOVNE, 3, Result).addReg(Tmp1).addReg(Tmp3).addReg(Tmp6);
- return Result;
- }
case ISD::SINT_TO_FP:
{
assert (N.getOperand(0).getValueType() == MVT::i64