The PPC64 ELF ABI is "intended to use the same structure layout and calling convention rules
as the 64-bit PowerOpen ABI" (Reference http://www.linux-foundation.org/spec/ELF/ppc64/).
Change all ELF tests to ELF32.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@35624 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 5ac8710..5efeaf4 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -1132,7 +1132,7 @@
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = PtrVT == MVT::i64;
bool isMachoABI = Subtarget.isMachoABI();
- bool isELF_ABI = Subtarget.isELF_ABI();
+ bool isELF32_ABI = Subtarget.isELF32_ABI();
unsigned PtrByteSize = isPPC64 ? 8 : 4;
unsigned ArgOffset = PPCFrameInfo::getLinkageSize(isPPC64, isMachoABI);
@@ -1165,7 +1165,7 @@
// entry to a function on PPC, the arguments start after the linkage area,
// although the first ones are often in registers.
//
- // In the ELF ABI, GPRs and stack are double word align: an argument
+ // In the ELF 32 ABI, GPRs and stack are double word align: an argument
// represented with two words (long long or double) must be copied to an
// even GPR_idx value or to an even ArgOffset value.
@@ -1187,7 +1187,7 @@
default: assert(0 && "Unhandled argument type!");
case MVT::i32:
// Double word align in ELF
- if (Expand && isELF_ABI && !isPPC64) GPR_idx += (GPR_idx % 2);
+ if (Expand && isELF32_ABI) GPR_idx += (GPR_idx % 2);
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
MF.addLiveIn(GPR[GPR_idx], VReg);
@@ -1198,7 +1198,7 @@
ArgSize = PtrByteSize;
}
// Stack align in ELF
- if (needsLoad && Expand && isELF_ABI && !isPPC64)
+ if (needsLoad && Expand && isELF32_ABI)
ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
// All int arguments reserve stack space in Macho ABI.
if (isMachoABI || needsLoad) ArgOffset += PtrByteSize;
@@ -1240,7 +1240,7 @@
}
// Stack align in ELF
- if (needsLoad && Expand && isELF_ABI && !isPPC64)
+ if (needsLoad && Expand && isELF32_ABI)
ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
// All FP arguments reserve stack space in Macho ABI.
if (isMachoABI || needsLoad) ArgOffset += isPPC64 ? 8 : ObjSize;
@@ -1344,7 +1344,7 @@
unsigned NumOps = (Op.getNumOperands() - 5) / 2;
bool isMachoABI = Subtarget.isMachoABI();
- bool isELF_ABI = Subtarget.isELF_ABI();
+ bool isELF32_ABI = Subtarget.isELF32_ABI();
MVT::ValueType PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
bool isPPC64 = PtrVT == MVT::i64;
@@ -1432,8 +1432,8 @@
// register cannot be found for it.
SDOperand PtrOff;
- // Stack align in ELF
- if (isELF_ABI && Expand && !isPPC64)
+ // Stack align in ELF 32
+ if (isELF32_ABI && Expand)
PtrOff = DAG.getConstant(ArgOffset + ((ArgOffset/4) % 2) * PtrByteSize,
StackPtr.getValueType());
else
@@ -1453,7 +1453,7 @@
case MVT::i32:
case MVT::i64:
// Double word align in ELF
- if (isELF_ABI && Expand && !isPPC64) GPR_idx += (GPR_idx % 2);
+ if (isELF32_ABI && Expand) GPR_idx += (GPR_idx % 2);
if (GPR_idx != NumGPRs) {
RegsToPass.push_back(std::make_pair(GPR[GPR_idx++], Arg));
} else {
@@ -1462,7 +1462,7 @@
}
if (inMem || isMachoABI) {
// Stack align in ELF
- if (isELF_ABI && Expand && !isPPC64)
+ if (isELF32_ABI && Expand)
ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
ArgOffset += PtrByteSize;
@@ -1516,7 +1516,7 @@
}
if (inMem || isMachoABI) {
// Stack align in ELF
- if (isELF_ABI && Expand && !isPPC64)
+ if (isELF32_ABI && Expand)
ArgOffset += ((ArgOffset/4) % 2) * PtrByteSize;
if (isPPC64)
ArgOffset += 8;
@@ -1548,8 +1548,8 @@
InFlag = Chain.getValue(1);
}
- // With the ELF ABI, set CR6 to true if this is a vararg call.
- if (isVarArg && isELF_ABI) {
+ // With the ELF 32 ABI, set CR6 to true if this is a vararg call.
+ if (isVarArg && isELF32_ABI) {
SDOperand SetCR(DAG.getTargetNode(PPC::SETCR, MVT::i32), 0);
Chain = DAG.getCopyToReg(Chain, PPC::CR6, SetCR, InFlag);
InFlag = Chain.getValue(1);