fit in 80 cols
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23051 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPCISelPattern.cpp b/lib/Target/PowerPC/PPCISelPattern.cpp
index 22082a4..da07b30 100644
--- a/lib/Target/PowerPC/PPCISelPattern.cpp
+++ b/lib/Target/PowerPC/PPCISelPattern.cpp
@@ -1522,7 +1522,7 @@
if (Tmp3 == 0) {
Tmp1 = SelectExpr(Node->getOperand(0));
switch (CC) {
- default: Node->dump(); assert(0 && "Unhandled SetCC condition"); abort();
+ default: Node->dump(); assert(0 && "Unhandled SetCC condition");abort();
case ISD::SETEQ:
Tmp2 = MakeIntReg();
BuildMI(BB, PPC::CNTLZW, 1, Tmp2).addReg(Tmp1);