(X & Y) & C == 0 if either X&C or Y&C are zero
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@23678 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index e4aa773..069a8f9 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -176,10 +176,15 @@
SrcBits = MVT::getSizeInBits(cast<VTSDNode>(Op.getOperand(1))->getVT());
return (Mask & ((1ULL << SrcBits)-1)) == 0; // Returning only the zext bits.
case ISD::AND:
+ // If either of the operands has zero bits, the result will too.
+ if (MaskedValueIsZero(Op.getOperand(1), Mask, TLI) ||
+ MaskedValueIsZero(Op.getOperand(0), Mask, TLI))
+ return true;
+
// (X & C1) & C2 == 0 iff C1 & C2 == 0.
if (ConstantSDNode *AndRHS = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
return MaskedValueIsZero(Op.getOperand(0),AndRHS->getValue() & Mask, TLI);
- // FALL THROUGH
+ return false;
case ISD::OR:
case ISD::XOR:
return MaskedValueIsZero(Op.getOperand(0), Mask, TLI) &&