commit eececbab32fe072f7d6b31786787dfea270b2dbb
author Andrew Lenharth <andrewl@lenharth.org> Sun Dec 25 17:36:48 2005 +0000
committer Andrew Lenharth <andrewl@lenharth.org> Sun Dec 25 17:36:48 2005 +0000
tree 195745d323b9899c73db5bf3ba84731e3f946a5d
parent b13d74a49a69a94246ae64479325fe580363a6c0

add br pattern, unify JSR and BSR ISel instrs, and add BSR support for DAG


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25011 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/Alpha/AlphaAsmPrinter.cpp

diff --git a/lib/Target/Alpha/AlphaAsmPrinter.cpp b/lib/Target/Alpha/AlphaAsmPrinter.cpp
index 59b9199..29627c5 100644
--- a/lib/Target/Alpha/AlphaAsmPrinter.cpp
+++ b/lib/Target/Alpha/AlphaAsmPrinter.cpp
@@ -136,9 +136,9 @@
   case MachineOperand::MO_GlobalAddress:
     //Abuse PCrel to specify pcrel calls
     //calls are the only thing that use this flag
-    if (MO.isPCRelative())
-      O << PrivateGlobalPrefix << Mang->getValueName(MO.getGlobal()) << "..ng";
-    else
+//     if (MO.isPCRelative())
+//       O << PrivateGlobalPrefix << Mang->getValueName(MO.getGlobal()) << "..ng";
+//     else
       O << Mang->getValueName(MO.getGlobal());
     return;