Add the necessary support to codegen condition register logical ops with
register allocated condition registers. Make sure that the printed
output is gas compatible.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21295 91177308-0d34-0410-b5e6-96231b3b80d8
diff --git a/lib/Target/PowerPC/PPC32ISelSimple.cpp b/lib/Target/PowerPC/PPC32ISelSimple.cpp
index 17f74cd..6306a8e 100644
--- a/lib/Target/PowerPC/PPC32ISelSimple.cpp
+++ b/lib/Target/PowerPC/PPC32ISelSimple.cpp
@@ -1115,7 +1115,7 @@
// Use crand for lt, gt and crandc for le, ge
unsigned CROpcode = (OpNum == 2 || OpNum == 4) ? PPC::CRAND : PPC::CRANDC;
// ? cr1[lt] : cr1[gt]
- unsigned CR1field = (OpNum == 2 || OpNum == 3) ? 4 : 5;
+ unsigned CR1field = (OpNum == 2 || OpNum == 3) ? 0 : 1;
// ? cr0[lt] : cr0[gt]
unsigned CR0field = (OpNum == 2 || OpNum == 5) ? 0 : 1;
unsigned Opcode = CompTy->isSigned() ? PPC::CMPW : PPC::CMPLW;
@@ -1165,9 +1165,10 @@
.addReg(ConstReg);
BuildMI(*MBB, IP, Opcode, 2, PPC::CR1).addReg(Op0r+1)
.addReg(ConstReg+1);
- BuildMI(*MBB, IP, PPC::CRAND, 3).addImm(2).addImm(2).addImm(CR1field);
- BuildMI(*MBB, IP, PPC::CROR, 3).addImm(CR0field).addImm(CR0field)
- .addImm(2);
+ BuildMI(*MBB, IP, PPC::CRAND, 5, PPC::CR0).addImm(2)
+ .addReg(PPC::CR0).addImm(2).addReg(PPC::CR1).addImm(CR1field);
+ BuildMI(*MBB, IP, PPC::CROR, 5, PPC::CR0).addImm(CR0field)
+ .addReg(PPC::CR0).addImm(CR0field).addReg(PPC::CR0).addImm(2);
return;
}
}
@@ -1204,9 +1205,10 @@
// cr0 = r3 ccOpcode r5 or (r3 == r5 AND r4 ccOpcode r6)
BuildMI(*MBB, IP, Opcode, 2, PPC::CR0).addReg(Op0r).addReg(Op1r);
BuildMI(*MBB, IP, Opcode, 2, PPC::CR1).addReg(Op0r+1).addReg(Op1r+1);
- BuildMI(*MBB, IP, PPC::CRAND, 3).addImm(2).addImm(2).addImm(CR1field);
- BuildMI(*MBB, IP, PPC::CROR, 3).addImm(CR0field).addImm(CR0field)
- .addImm(2);
+ BuildMI(*MBB, IP, PPC::CRAND, 5, PPC::CR0).addImm(2)
+ .addReg(PPC::CR0).addImm(2).addReg(PPC::CR1).addImm(CR1field);
+ BuildMI(*MBB, IP, PPC::CROR, 5, PPC::CR0).addImm(CR0field)
+ .addReg(PPC::CR0).addImm(CR0field).addReg(PPC::CR0).addImm(2);
return;
}
}
diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index bfc6167..4acaca7 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -138,6 +138,26 @@
O << "-\"L0000" << LabelNumber << "$pb\")";
}
}
+ void printcrbit(const MachineInstr *MI, unsigned OpNo,
+ MVT::ValueType VT) {
+ unsigned char value = MI->getOperand(OpNo).getImmedValue();
+ assert(value <= 3 && "Invalid crbit argument!");
+ unsigned RegNo, CCReg = MI->getOperand(OpNo-1).getReg();
+ switch (CCReg) {
+ case PPC::CR0: RegNo = 0; break;
+ case PPC::CR1: RegNo = 1; break;
+ case PPC::CR2: RegNo = 2; break;
+ case PPC::CR3: RegNo = 3; break;
+ case PPC::CR4: RegNo = 4; break;
+ case PPC::CR5: RegNo = 5; break;
+ case PPC::CR6: RegNo = 6; break;
+ case PPC::CR7: RegNo = 7; break;
+ default:
+ std::cerr << "Unhandled reg in enumRegToRealReg!\n";
+ abort();
+ }
+ O << 4 * RegNo + value;
+ }
virtual void printConstantPool(MachineConstantPool *MCP) = 0;
virtual bool runOnMachineFunction(MachineFunction &F) = 0;
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index 6d845eb..181f2b3 100644
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -309,8 +309,22 @@
// 1.7.7 XL-Form
class XLForm_1<bits<6> opcode, bits<10> xo, bit ppc64, bit vmx,
- dag OL, string asmstr>
- : XForm_base_r3xo<opcode, xo, 0, ppc64, vmx, OL, asmstr> {
+ dag OL, string asmstr> : I<opcode, ppc64, vmx, OL, asmstr> {
+ bits<3> CRD;
+ bits<2> CRDb;
+ bits<3> CRA;
+ bits<2> CRAb;
+ bits<3> CRB;
+ bits<2> CRBb;
+
+ let Inst{6-8} = CRD;
+ let Inst{9-10} = CRDb;
+ let Inst{11-13} = CRA;
+ let Inst{14-15} = CRAb;
+ let Inst{16-18} = CRB;
+ let Inst{19-20} = CRBb;
+ let Inst{21-30} = xo;
+ let Inst{31} = 0;
}
class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, bit ppc64, bit vmx,
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index b40d0d4..a06099a 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -45,6 +45,9 @@
def symbolLo: Operand<i32> {
let PrintMethod = "printSymbolLo";
}
+def crbit: Operand<i8> {
+ let PrintMethod = "printcrbit";
+}
// Pseudo-instructions:
def PHI : Pseudo<(ops), "; PHI">;
@@ -332,14 +335,30 @@
// XL-Form instructions. condition register logical ops.
//
-def CRAND : XLForm_1<19, 257, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
- "crand $D, $A, $B">;
-def CRANDC : XLForm_1<19, 129, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
- "crandc $D, $A, $B">;
-def CRNOR : XLForm_1<19, 33, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
- "crnor $D, $A, $B">;
-def CROR : XLForm_1<19, 449, 0, 0, (ops u5imm:$D, u5imm:$A, u5imm:$B),
- "cror $D, $A, $B">;
+def CRAND : XLForm_1<19, 257, 0, 0, (ops CRRC:$D, crbit:$Db,
+ CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
+ "crand $Db, $Ab, $Bb">;
+def CRANDC : XLForm_1<19, 129, 0, 0, (ops CRRC:$D, crbit:$Db,
+ CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
+ "crandc $Db, $Ab, $Bb">;
+def CREQV : XLForm_1<19, 289, 0, 0, (ops CRRC:$D, crbit:$Db,
+ CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
+ "creqv $Db, $Ab, $Bb">;
+def CRNAND : XLForm_1<19, 225, 0, 0, (ops CRRC:$D, crbit:$Db,
+ CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
+ "crnand $Db, $Ab, $Bb">;
+def CRNOR : XLForm_1<19, 33, 0, 0, (ops CRRC:$D, crbit:$Db,
+ CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
+ "crnor $Db, $Ab, $Bb">;
+def CROR : XLForm_1<19, 449, 0, 0, (ops CRRC:$D, crbit:$Db,
+ CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
+ "cror $Db, $Ab, $Bb">;
+def CRORC : XLForm_1<19, 417, 0, 0, (ops CRRC:$D, crbit:$Db,
+ CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
+ "crorc $Db, $Ab, $Bb">;
+def CRXOR : XLForm_1<19, 193, 0, 0, (ops CRRC:$D, crbit:$Db,
+ CRRC:$A, crbit:$Ab, CRRC:$B, crbit:$Bb),
+ "crxor $Db, $Ab, $Bb">;
def MCRF : XLForm_3<19, 0, 0, 0, (ops CRRC:$BF, CRRC:$BFA),
"mfcr $BF, $BFA">;