diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index 47388ea..c566b48 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -207,6 +207,24 @@
 ///
 MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const {
   switch (MI->getOpcode()) {
+  case X86::SHUFPSrri: { // A = SHUFPSrri B,C, M -> A = SHUFPSrri C,B, rotl(M,4)
+    unsigned A = MI->getOperand(0).getReg();
+    unsigned B = MI->getOperand(1).getReg();
+    unsigned C = MI->getOperand(2).getReg();
+    unsigned M = MI->getOperand(3).getImmedValue();
+    if (B == C) return 0;
+    return BuildMI(X86::SHUFPSrri, 3, A).addReg(C).addReg(B).
+      addImm(((M & 0xF) << 4) | ((M & 0xF0) >> 4));
+  }
+  case X86::SHUFPDrri: { // A = SHUFPDrri B,C, M -> A = SHUFPDrri C,B, rotl(M,1)
+    unsigned A = MI->getOperand(0).getReg();
+    unsigned B = MI->getOperand(1).getReg();
+    unsigned C = MI->getOperand(2).getReg();
+    unsigned M = MI->getOperand(3).getImmedValue();
+    if (B == C) return 0;
+    return BuildMI(X86::SHUFPDrri, 3, A).addReg(C).addReg(B).
+      addImm(((M & 0x1) << 1) | ((M & 0x2) >> 1));
+  }
   case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
   case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
   case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td
index ca6ed88..5ea6d92 100644
--- a/lib/Target/X86/X86InstrSSE.td
+++ b/lib/Target/X86/X86InstrSSE.td
@@ -1218,7 +1218,7 @@
 
 // Shuffle and unpack instructions
 let isTwoAddress = 1 in {
-let isConvertibleToThreeAddress = 1 in // Convert to pshufd
+let isCommutable = 1, isConvertibleToThreeAddress = 1 in // Convert to pshufd
 def SHUFPSrri : PSIi8<0xC6, MRMSrcReg, 
                      (ops VR128:$dst, VR128:$src1, VR128:$src2, i32i8imm:$src3),
                      "shufps {$src3, $src2, $dst|$dst, $src2, $src3}",
@@ -1231,6 +1231,7 @@
                      [(set VR128:$dst, (v4f32 (vector_shuffle
                                                VR128:$src1, (load addr:$src2),
                                                SHUFP_shuffle_mask:$src3)))]>;
+let isCommutable = 1 in
 def SHUFPDrri : PDIi8<0xC6, MRMSrcReg, 
                      (ops VR128:$dst, VR128:$src1, VR128:$src2, i8imm:$src3),
                      "shufpd {$src3, $src2, $dst|$dst, $src2, $src3}",