commit f000a7a212590bfd45e23c05bff5e1b683d25dd6
author Michael J. Spencer <bigcheesegs@gmail.com> Tue Oct 05 06:00:43 2010 +0000
committer Michael J. Spencer <bigcheesegs@gmail.com> Tue Oct 05 06:00:43 2010 +0000
tree c9d85f17f40de5d500d0195f4f2850fe6766dc1d
parent 2bbb76909126db5bed6bde84b16d94ab5de4d372

fix MSVC 2010 build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115594 91177308-0d34-0410-b5e6-96231b3b80d8

lib/Target/ARM/ARMBaseInstrInfo.cpp

diff --git a/lib/Target/ARM/ARMBaseInstrInfo.cpp b/lib/Target/ARM/ARMBaseInstrInfo.cpp
index 2d729bf..0ccf7b6 100644
--- a/lib/Target/ARM/ARMBaseInstrInfo.cpp
+++ b/lib/Target/ARM/ARMBaseInstrInfo.cpp
@@ -1470,7 +1470,8 @@
     case ARM::COPY: {
       // Walk down one instruction which is potentially an 'and'.
       const MachineInstr &Copy = *MI;
-      MachineBasicBlock::iterator AND(next(MachineBasicBlock::iterator(MI)));
+      MachineBasicBlock::iterator AND(
+        llvm::next(MachineBasicBlock::iterator(MI)));
       if (AND == MI->getParent()->end()) return false;
       MI = AND;
       return isSuitableForMask(MI, Copy.getOperand(0).getReg(),